KR100217708B1 - Image signal processing device - Google Patents

Abstract

The present invention relates to a video signal processing apparatus suitable for a camera integrated video tape recorder (VTR) or the like, wherein the video signal processing apparatus of the present invention writes one desired field or one frame of a moving image signal reproduced from a video tape recorder. And a three-port type memory means for obtaining two outputs independently from each other, and a crossfade means, which obtains a time-axis corrected output signal from one output of the memory means, and at the same time the video camera starts operation. This is to crossfade the moving picture signal from the video camera and the still picture signal read out from the output of the other side of the memory means.

Description

Video signal processing device

1 is a block diagram showing the configuration of an embodiment of a video signal processing apparatus according to the present invention.

2 is a time chart for explaining the operation of one embodiment of the present invention.

Figure 3 is a schematic diagram for explaining the operation of one embodiment of the present invention.

4 is a block diagram showing the configuration of another embodiment of the present invention.

5 is a time chart for explaining the operation of another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1: video camera 4: monitor

5: VTR 6: System control circuit (microcomputer)

10, 10C: Image signal processing device 11, 11T: Field memory

12: crossfade circuit 13, 14, 19: counter

16, 16S: memory control circuit

The present invention relates to a video signal processing apparatus suitable for a camera integrated video tape recorder (VTR).

The present invention provides a video signal processing apparatus having a field memory or a frame memory, wherein a desired video signal reproduced from a VTR is written into a memory and at the same time a moving picture signal from the video camera starts to operate. By crossfading the still picture signals read out from the memory, it is possible to smoothly switch scenes with a simple configuration.

When editing a program material (source) of a conventional video or audio, in order to remove the discontinuity at the edit point, the signal level of the preceding source is gradually decreased and faded out, while the signal level of the subsequent source is gradually increased and faded in. Techniques, so-called dissolves or crossfades, are often used.

However, in order to perform the conventional crossfade, in addition to two signal sources, for example, a video camera and a VTR, another VTR is required to record a crossfade video signal. There was a problem of cost.

In view of these problems, it is an object of the present invention to provide a video signal processing apparatus capable of smoothly changing a scene at an edit point with a simple configuration.

The present invention includes a three-port type memory means for writing desired one field or one frame of a moving picture signal reproduced from a video tape recorder and obtaining two outputs independently from each other, and a crossfade means. While obtaining the time-axis corrected output signal from one output of the means, when the video camera starts to operate, it crosses the moving image signal from this video camera and the still image signal read out from the output of the other memory means. It is a video signal processing apparatus which fades.

According to the present invention, it is possible to smoothly switch scenes at edit points with a simple configuration.

Hereinafter, an embodiment of a video signal processing apparatus according to the present invention will be described with reference to FIGS. 1 to 3.

The configuration of one embodiment of the present invention is shown in FIG.

In FIG. 1, reference numeral 10 denotes the video signal storage device as a whole, and is mainly composed of the field memory 11 and the crossfade circuit 12. The crossfade circuit 12 is, for example, 1 It consists of a pair of counters 13 and 14 and an adder 15.

Both counters 13 and 14 include, for example, a read-only memory (ROM), and required number of data are stored in each ROM.

The input video signal Si from the video camera 1 passes through the rec side fixed contact and the movable contact of the changeover switch 2 to the ee side fixed contact of the field memory 11, the counter 13, and the changeover switch 3. Commonly supplied. The video signal Sd delayed by one field period from the field memory 11 is supplied to the counter 14, and the outputs of both counters 13 and 14 are supplied to the adder 15. The crossfade video signal Sf output from the adder 15 is commonly supplied to the monitor (viewfinder) 4 and the VTR 5 via the mry side fixed contact and the movable contact of the switch 3, and the VTR ( The output of 5) is supplied to the fixed contact on the pb side of the switch (2).

The control signal output from the memory control circuit 16 is supplied to the field memory 11. The memory control circuit 16, the changeover switches 2, 3, the counters 13, 14 are provided with a key 7e from the system control circuit (microcomputer) 6 for the VTR (5). Various control signals corresponding to the operations of (7f), (7p), (7r), (7ss) ... are supplied. In addition, the output of the power source 9 is supplied to each part via the switch 8.

Next, the operation of one embodiment of the present invention will be described with reference to FIGS. 2 and 3.

First, the edit playback key 7e is operated so that the VTR 5 enters the edit playback (edit search) mode as shown in FIG. 2 (a). At this time, as shown in the figures (b) and (c), the switch control signals Scb and Scc are H and L, respectively, the switch 2 is connected to the Pb side, and the switch 3 is connected to the mry side, respectively. Connected. In addition, as shown in Figs. (D) and (e), both the memory control signal Scd and the crossfade control signal Sce are L, the memory 11 is in a writable (dru) state, and the two counters 13 ) And (14) become k = 0.

Thereby, the reproduced video signal Spb from the VTR 5 is supplied to the monitor B via the memory 11, and the image of the preceding scene which the user has previously taken and wants to edit from now on the screen of the monitor 4 For example, an image of a mountain as shown in FIG. 3 (a) is produced.

At the time t1, when the start stop key 7ss is operated and the VTR 5 is in the stop (stop) mode as shown in FIG. 2, the traveling of the magnetic tape is stopped and the drawing (b) and As shown in (c), the control signal Scb is switched from H to L and the control signal Scc is switched from L to H, so that the switch 2 is switched to the rec side and the switch 3 is switched to the ee side, respectively. In addition, as shown in this drawing (d), the control signal Scd is switched from L to H, so that the memory 11 is switched from the draw state to the write inhibit (hold) state. At this time, the switch 8 is in an on state, and the output of the power supply 9 is supplied to each part.

As a result, at the switching time t1, the video signal of the picture reproduced from the VTR 5, for example, the mountain image as shown in FIG. 3 (a), is held in the memory 11. In addition, an image of the same mountain is drawn on the screen of the monitor 4.

At the time t2, the recording key 7r and the pause value 7p are operated at the same time so that the VTR 6 enters the recording pause mode (repose) mode as shown in FIG. 2 (a). Is maintained.

In this state, for example, it is connected to the reproduction image of the VTR 5 as shown in FIG. 3 (a), and the subject of the next scene, for example, a person jogging as shown in this figure (c). The camera 1 is pointed at, and the fader key 7f is operated to determine a scene to be crossfaded.

At the time t3, when the start stop key 7ss is operated and the VTR 5 is in the recording mode as shown in Fig. 2 (a), as shown in Figs. (b) and (c), The control signal Scb is left as it is, the control signal Scc is switched from H to L, and the switch 3 is switched to the mry side as it is on the rec side.

As shown in the figures (d) and (e), the period control signal Scd from this time point t3 to the time point t4 after a predetermined time (for example, one second) is held at H to hold the memory 11. At the same time, the control signal Sce becomes H, and the crossfade circuit 12 operates as follows.

The coefficients of the counters 13 and 14 are k (1-k) (0≤k≤1), respectively, and the output of the adder 15, i.e., the crossfade video signal Sf, is expressed by the following expression (1).

In this case, for example, if k is incremented from 0 to 1 in one second, as shown in Figs. 2 (f) and (g), the still picture image signal Sd read out from the memory 11 simultaneously fades out. The input moving image signal Si from the camera 1 fades in.

In the crossfade period t3-t4, as shown in FIG. 3 (b), the image of the preceding scene and the subsequent scene overlaps and is displayed on the screen of the monitor 4, and the still image of the preceding scene. The signal overlaps with the moving picture signal of the subsequent scene and is recorded on the magnetic tape.

After the time point t4, a moving picture of a person jogging as shown in FIG. 3 (c) is drawn on the screen of the monitor 4 and recorded on the magnetic tape.

Therefore, when the magnetic tape is played back, the scene before and after the edit point is smoothly switched with the overlap portion interposed therebetween.

Next, another embodiment of the video signal processing apparatus according to the present invention will be described with reference to FIGS. 4 and 5. FIG.

The configuration of another embodiment of the present invention is shown in FIG. In FIG. 4, parts corresponding to those of FIG. 1 are denoted by the same reference numerals and redundant description thereof is omitted.

In Fig. 4, (10C) displays the video signal processing apparatus as a whole, and a three-port type field memory 11T is formed so as to correspond to the time base correction (TBC) of the VTR 5, A cyclic crossfade circuit is formed. The circuit structure of this iterative type is similar to the known noise reduction circuit. (See Japanese Patent Application Center 62 (1987) -3639).

As is well known, in the case of time-base correction, the timing specified from the memory varies according to the jitter of the reproduction signal of the VTR. On the other hand, in the case of noise reduction, crossfade, etc., the memory is extracted from the memory with one field period delay. Therefore, in this embodiment, a three-port type field memory that uses two outputs independent of each other is used.

The input video signal Si from the video camera 1 passes through the rec side fixed contact and the movable contact of the switch 2, and is common to the ee side fixed contact, the adder 17 and the adder 18 of the switch 3. The output signal Sf of the adder 17 is supplied to the field memory 11T. The first delayed calculation signal Sd1 extracted from the field memory 11T is supplied to the fixed contact of the mry side of the switch 3, and the input video signal Sd2 is subtracted from the second delayed video signal Sd2 delayed by one field period. 18), and the input video signal Si is subtracted from this delayed video signal Sd2. The output of the subtractor 18 is supplied to the adder 17 through the counter 19.

The control signal of the memory control circuit 16S is supplied to the field memory 11T, and the control signal from the system control circuit 6 is supplied to the memory control circuit 165 and the counter 19. The rest of the configuration is the same as that of FIG.

Next, the operation of another embodiment of the present invention will be described with reference to FIG.

Initially, the switch 8 is opened and the whole is in a power-off state as shown in FIG. 5 (a). In addition, as shown by the broken line in this figure (b)-(e), each control signal Scb-Sce is not output and the connection state of the switches 2 and 3 is undecided.

At the time t11, when the switch 8 is turned on and the start stop value 7ss is operated and the VTR 5 is in the stop mode as shown in Fig. 5 (a), the figures (b) and ( As shown in c), the control signal Scb becomes L, the control signal Scc becomes H, and the switch 2 is connected to the rec side and the switch 3 is connected to the ee side, respectively. In addition, as shown in this drawing (d), the control signal Scd becomes H, and the memory 11T is held.

This state is the same as the time point t1 in FIG. 2, but in this embodiment, the VTR 5 is configured so that the tape is slightly rewound at the time of transition from the previous recording mode to the stop mode so that the connection is made clean at the next recording start point. As shown in FIG. 5 (h), the position of the magnetic head (not shown) on the tape is slightly in the rewind (rw) direction with respect to the last recording point.

At the time t12, when the VTR 6 is switched to the rack pose board, as shown in Figs. 5 (b) and 5 (e), for example, the VTR 5 is not available until t13 after a little less than 1 second. In the regeneration mode, the switch control signals Scb and Scc become H and L, respectively, and the memory control signal Scd and the crossfade control signal Sce become L, as before the time point t1 in FIG. Then, the switch 2 is connected to the pb side, the switch 3 is connected to the rec side, and the memory 11T is brought into the draw state, and the coefficients of the quantum counters 13 and 14 are k = 0. It is in a state.

In addition, as shown in FIG. 5 (h), the tape travels in the forward (fw) direction, and the image of the preceding scene previously photographed from the VTR 5, for example, as shown in FIG. The mountain image as described above is reproduced, and the reproduced video signal Spb is supplied to the monitor 4 via the memory 11T.

At time t13, the VTR 5 returns to the repose mode, and as shown in Figs. 5 (b) and 5 (e), each control signal Scb-Sce is switched to the same state as the time t11. The memory 11T is again held.

As a result, a video signal of an image reproduced from the VTR 5 at the time t13, for example, a mountain image as shown in FIG. 3 (a), is held in the memory 11T. In addition, the tape is slightly rewound as shown in FIG. 5 (h).

At time t14, when the VTR 5 is switched to the recording mode as shown in Fig. 5 (a), the control signals Scb and Scc become L as shown in Figs. (b) and (c). The switch 2 is switched to the rec side, and the switch 3 is switched to the mry side. In addition, as shown in this drawing (d), the control signal Scd becomes L, and the memory 11T is switched to the draw state.

As shown in this figure (e), the period control signal Sce from time t15 to time t15 after a predetermined time (for example, one second) becomes H, and the following crossfade operation is performed.

Assuming that the coefficient of the counter 19 is k (0 ≦ k ≦ 1), the output signal Sf of the adder 17 is expressed by the following expression (2).

In this case, in contrast to the previous embodiment of FIG. 1, for example, if k gradually decreases from 1 to 0 for one second, it is read out from the memory 11T as shown in FIGS. 5 (f) and (g). The frozen still picture signal Sd2 fades out and the input moving picture signal Si from the camera 1 fades in.

As shown in this figure (h), the tape is running in the forward direction, including the trough period immediately before the t14 time point, and as described above in the crossfade period t14-tl5. The images of the preceding scene and the subsequent scene are overlapped and recorded on the magnetic tape. After t15, the moving picture of the subsequent scene is recorded so that the scene before and after the edit point is smoothly switched.

In the embodiment of Fig. 4, the crossfade circuit is formed in a loop type by forming a loop, and the video signals read out from the memory 11T in line order are written to the memory 11T again via this loop. Due to the signal saving time in the counter 19 or the like, the line on which the video signal after the coefficient multiplication is written is the same as the line from which the original and the video signal are read.

Therefore, in the embodiment of FIG. 4, the timing control of the field memory 11T becomes simpler than that of the embodiment of FIG. 1, and the scale of the memory control circuit 16S is reduced.

In the above embodiment, the field memory is used, but the frame memory may be used.

In addition, when the crossfade circuit forms a closed loop and is configured in a circulation type as in the embodiment of FIG. 4, by appropriately setting the data pattern of the counter, it is also used in noise reduction, so-called multistrobo, clean steel / slow reproduction, and the like.

As described above, according to the present invention, the desired video signal reproduced from the VTR is written into the field memory or the frame memory, and the moving picture signal from the video camera and the still picture read out from the memory when the video camera starts operation. Since the signal is crossfaded, a video signal processing apparatus capable of smoothly switching scenes at edit points with a simple configuration is obtained.

Claims (1)

A three-port type memory means for writing desired one field or one frame of a moving picture signal reproduced from a video tape recorder and obtaining two outputs independently from each other, and a crossfade means; Obtain a time-axis corrected output signal from the output of the video signal and crossfade the moving picture signal from the video camera and the still picture signal read out from the output of the memory means when the video camera starts to operate. Image signal processing apparatus, characterized in that.