KR100217368B1 - Error flag generating circuit and method of computer compact disk rom drive - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

A circuit and method for generating an error flag for a header / subheader of a data block in a compact disk-ROM (CD-ROM) drive.

2. Technical problem to be solved by the invention

It provides an error flag generating circuit and method that can generate an error flag of a header / subheader even when a separate error flag is not used.

3. Summary of Solution to Invention

An error flag is generated and stored in a register when P code word data is read in code word units among the data stored in the data RAM and error correction processing is performed.

4. Important uses of the invention

It is used to generate header / subheader error flag when only data RAM is used.

Description

Error Flag Generation Circuit and Method of Compact Disc-ROM Drive

1 is a block diagram of an error flag generating circuit according to the present invention.

2 is a data block format diagram of a conventional CD-ROM.

3 is an ECC memory map for general error correction.

4 is a codeword read and error correction operation timing diagram of FIG.

5 is an operation timing diagram according to the error correction section designation of FIG.

6 is a Q code read and error correction operation timing diagram of FIG.

7 is a P code read and error correction operation timing diagram of FIG.

8 is a timing diagram illustrating a storage operation of headers and subheaders of FIG.

9 is an error flag storing operation timing diagram of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Compact Disk-Read Only Memory (hereinafter referred to as CD-ROM) drive, particularly for a header / subheader of a data block. A circuit and method for generating an error flag are disclosed.

A typical CD-ROM drive has a random access memory (RAM) and an error flag outside of error correction. When error correction is completed, an error flag for header and subheader bytes is displayed. Stored in RAM. Therefore, if necessary, the value stored in the error flag is read and transferred to the microcomputer, etc. that controls the CD-ROM drive as a whole.

On the other hand, in order to simplify the structure of the CD-ROM, an error flag may not be used externally. In this case, error correction is performed without referring to the error flag. At this time, the error flag that occurs during error correction is discarded. Accordingly, an error flag for header / subheader byte cannot be generated. Therefore, in this case, the error correction rate is lower than that of error correction by referring to the error flag.

As described above, the error flag is not stored in the CD-ROM drive using only the data RAM connected to the external device without using the error flag, so the error flag for the header and subheader bytes cannot be referred to by the microcomputer. There was this.

Accordingly, an object of the present invention is to provide an error flag generating circuit and method that can generate an error flag of a header / subheader even when a separate error flag is not used in a CD-ROM drive.

In order to achieve the above object, the present invention is characterized in that an error flag is generated and stored in a register when P codeword data of the data stored in the data RAM is read in codeword units for error correction processing.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description and the annexed drawings, many specific details are set forth in order to provide a more thorough understanding of the present invention, such as specific number of bits or bytes, operation timing, logic state, and the like. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

First, referring to FIG. 1 showing a block diagram of an error flag generating circuit according to the present invention, the data RAM 10 is a data RAM connected to the outside as described above, and temporarily stores playback data in a prescribed block unit. . In general, in a CD-ROM system, one data block is 2352 bytes in both modes 1 and 2 as shown in FIG. Of the 2,352 bytes of such data blocks, the synchronous 12 bytes have a data pattern of 00 FF FF FF FF FF FF FF FF FF FF 00 as data for classifying one block by a specific pattern. When the sync pattern is detected, a sync clock pulse SYN_CP is generated. 2340 bytes of data excluding 12 synch bytes are subjected to ECC (Error Correction Code). At this time, the storage area of the RAM 10 is divided into a left plane and a right plane, and the even-most byte of the 2340 bytes is stored in the left plane and the odd-numbered byte is stored in the right plane. Therefore, the ECC performs correction on 1170 bytes for each plane.

The ECC is divided into a Q codeword and a P codeword. The Q codeword is composed of bytes read while scanning in a diagonal direction as shown in the ECC memory map of FIG. That is, the Q codeword consists of 45 bytes and has a total of 26 codewords, and the P codeword consists of 26 bytes and has a total of 43 codewords. Therefore, Q and P codewords are applied to the same byte, respectively. Accordingly, error correction is performed twice. The positions of the 4-byte header and the 8-byte subheader byte on the ECC memory map of FIG. 3 are shown in Table 1 below.

Referring to FIG. 4 which shows the codeword read and error correction operation timing, 2352 bytes are input and stored in the data RAM 10 during one period of the synchronous clock pulse SYN_CP.

At this time, data is input in units of 1 byte. In this manner, one block of data is input to each sync clock pulse SYN_CP and accumulated in the data RAM 10. The error correction is a block for which input has been completed by the previous sync clock pulse SYN_CP.

The error correction is performed by the error correction unit 12 of FIG. 1, which is started by the synchronous clock pulse SYN_CP. The error correction unit 12 performs an error correction process on the data stored in the RAM 10 and generates a header / subheader byte EC_DATA and its error flag EC_FLAG in codeword units. In this case, the codeword counter 14 generates control signals RL_P, PQ_AR, EDC_AR, CD_ST, and CR_ST for controlling error correction in the error correction unit 10, and includes a header / subheader register 16 and an error flag register. At 18, control signals HD_EN, SH_EN, HF_EN, SF_EN are generated for controlling the header / subheader byte and error flag EC_FLAG storage, respectively. The RL_P is a plane designation signal. When RL_P is low, the left plane is designated, and when it is high, the RL_P is designated. The PQ_AR is a sequence interval signal, and when it is low, it specifies a Q sequence and when it is high, it specifies a P sequence. The EDC_AR is an EDC (Error Detect Code) section signal and indicates an EDC section when it is high. The CD-ST designates read start of P and Q code words by a high pulse as a code word start signal. The CR-ST designates the start of error correction by a high pulse as an error correction start signal. The HD_EN is a header storage enable signal and is a signal that enables the storage of the header byte by a high pulse.

The SH_EN is a subheader enable signal, which enables the storage of the subheader byte by a high pulse. The HF_EN is an error flag storage enable signal of the header and is a signal that enables the storage of the error flag of the header by a high pulse. The SF_EN is an error flag storage enable signal of the subheader and is a signal for enabling the storage of the error flag of the subheader by a high pulse.

The process of error correction performed by the error correction unit 12 described above is typically QL as shown in the timing diagram of FIG. PL QR PR It is performed in the order of EDC.

The QL denotes a process of processing a Q codeword of a left plane, the PL denotes a P codeword of a left plane, the QR denotes a process of processing a Q codeword of a right plane, and the PR The process refers to a process of processing a P code word of a light plane, and the EDC refers to a process of performing an EDC as described above. The error correction is completed for the entire 2340 bytes through the above-described process in the error correction unit 12. At this time, an error flag is generated in units of codewords for each codeword correction. Accordingly, in the present invention, in order to obtain an error flag for the header / subheader byte, a value for the header / subheader byte is taken using the error flag generated in the PR and PL processes, which are the last part of the error correction process.

This will be described in more detail with reference to the operation timing diagrams of FIGS. 6 and 7 as follows. First, the error correction unit 12 reads the first Q codeword 45 bytes from the data RAM 10 in the P1 codeword read section, and calculates an error value in the second P2 codeword read section. An error flag is generated for the P codeword.

The error flag value at this time becomes an error flag for header byte 0. Thereafter, the error flag value in the P2 codeword error correction section is stored in the error flag register 18 in the same manner. In this case, since the left plane and the right plane are P1 codewords and P2 codewords, 4 bits are generated. In this way, error flags for header and subheader bytes can be obtained. Through this process, an error flag value is obtained and data of the header byte and the subheader byte are stored in the header / subheader register 16 in the EDC section, and finally the value of each byte and the error flag value are simultaneously output.

Referring now to FIG. 8, which shows the timing of the storage operation of the header and subheader, the header / subheader data EC_DATA output from the error correction 12 is generated when the header storage enable signal HD_EN occurs. 16). After that, when the request of the microcomputer (not shown) is sent to the microcomputer. At this time, the header store enable signal HD_EN is enabled for 4 bytes after the EDC interval signal EDC_AR is activated. The subheader storage enable signal SH-EN is enabled after the header storage enable signal HD_EN is disabled and is enabled for an 8-byte period.

Next, referring to FIG. 9 showing the error flag storage operation timing, the control signal for storing the error flag is the error flag storage of the header in the correction section of the first and second codewords of the PL and PR processes in the error correction process. The enable flag HF_EN is enabled so that the error flag for the header byte is stored in register 18. The error flag for the subheader byte is stored in the error flag register 18 by enabling the error flag storage enable signal SF_EN of the subheader in the correction section of the third to sixth codewords. In FIG. 9, when the plane designation signal RL_P is low, it corresponds to a PL error correction process. When the plane designation signal RL_P is high, it corresponds to a PR error correction process.

Therefore, the error flag for header / subheader byte, which is particularly important among 1 block of CD-ROM data block, is generated and the value is stored in the register, so that the data reliability of the header / subheader in the microcomputer can be improved.

As described above, the present invention can improve the data reliability of the header / subheader byte by generating the error flag for the header / subheader byte and storing it in a register even in a system that does not use an external RAM for an error flag. There is this.

In the above description of the present invention, specific embodiments have been described, but various modifications can be made without departing from the scope of the present invention. In particular, the embodiment of the present invention illustrates that the error flag is generated in the P codeword correction section because the ECC process is corrected after the Q codeword correction, but the ECC process generates the Q codeword after the P codeword correction. If correction is to be made later, an error flag may be generated in the Q codeword correction section. Therefore, the scope of the invention should not be defined by the described embodiments, but should be defined by the equivalents of the claims and the claims.

Claims (4)

In the error flag generation circuit of a compact disc-ROM drive, a RAM for temporarily storing playback data in a prescribed block unit, an error correction process for data stored in the RAM, and corresponding header / subheader bytes and an error flag thereof A codeword counter for generating error correction in codeword units, control signals for controlling the error correction, control signals for controlling the header / subheader byte and error flag storage, and the error correction. A header / subheader storage register for storing the header / subheader byte generated from the government by the control signals, and an error flag for the header / subheader generated from the error correction by the control signals. And an error flag register for storing the error flag. The error flag generating circuit according to claim 1, wherein the codeword counter causes the error flag to be stored in the error flag register for a codeword including a header byte and a subheader byte. A method of generating an error flag of a compact disc-ROM drive having a RAM and a register for temporarily storing reproducible data in a prescribed block unit, the method comprising: reading data of a Q code word left plane among the data stored in the RAM in code word units. An error correction process; a process of error correction processing by reading data of a P codeword left plane of data stored in the RAM in codeword units; and a codeword of data of a Q codeword write plane among data stored in the RAM A process of error correction processing by reading unit, a process of error correction processing by generating data of P code word write plane in codeword unit among data stored in the RAM, generating an error flag, and checking an error detection code Storing an error flag in the register. Error flag generation method. 4. The method of claim 3, wherein the error flag is stored with respect to a codeword including a header byte and a subheader byte.