KR100216585B1 - Half-pixel motion estimating apparatus of frame or field - Google Patents

Abstract

The present invention relates to a frame or field half-pixel motion estimation apparatus that can be used for half-pixel motion estimation of a frame or field, and can be commonly used for frame or field half-pixel motion estimation using simple hardware. First storage means for storing search area data to provide a pixel motion estimation apparatus; Second storage means for storing reference block data; First counting means for generating a memory output address of the search area data and outputting the memory address to the first storage means; Second counting means for generating a memory output address of reference block data and outputting it to the second storage means; Interpolation means for receiving interpolation search area data from the first storage means and generating interpolated search area data for half-pixel motion estimation at each half-pixel location; Half-pixel motion estimation means for receiving interpolated search area data from the interpolation means, receiving reference block data from the second storage means, and calculating a motion estimation error at each half-pixel position; And a comparison means for receiving a motion estimation error from the half-pixel motion estimation means and comparing the motion estimation error at each half-pixel position to perform half-pixel motion estimation for a frame or field using a simple device. It has the effect of providing flexibility.

Description

Frame or field half-pixel motion estimation device

1 is an exemplary configuration diagram of a search area and reference block data when estimating frame half-pixel motion used in the present invention.

2 is a diagram showing the configuration of a search area and reference block data when estimating field half-pixel motion used in the present invention.

Figure 3 is a block diagram of an embodiment of a frame or field half-pixel motion estimation apparatus according to the present invention.

4 is a detailed configuration example of an interpolator of a frame or field half-pixel motion estimation apparatus according to the present invention.

5 is a detailed configuration example of a frame or field half-pixel motion estimation apparatus according to the present invention.

6 is a detailed configuration example of an error accumulator of the half-pixel motion estimation apparatus of FIG.

* Explanation of symbols for main parts of the drawings

31: first memory 32: second memory

33: first counter 34: second counter

35: interpolator 36: half-pixel motion estimation device

37: comparator

The present invention relates to a frame or field half-pixel motion estimation apparatus for half-pixel motion estimation of a frame or field.

The conventional half-pixel motion estimation apparatus considers only half-pixel motion estimation for a frame or uses a method of obtaining approximate half-pixel positions using a mathematical model.

Therefore, in order to estimate the half-pixel motion of the field using the half-pixel motion estimation apparatus considering only the frame, additional complicated logic must be additionally implemented. In addition, when half-pixel motion estimation is performed using a mathematical model, very inaccurate results may be obtained, and there is a problem in that all motion estimation errors in one pixel unit need to be stored.

An object of the present invention is to provide a frame or field half-pixel motion estimation apparatus that can be commonly used for half-pixel motion estimation of a frame or field using simple hardware.

In order to achieve the above object, the present invention provides a frame or field half-pixel motion estimation apparatus comprising: first storage means for storing search area data; Second storage means for storing reference block data; First counting means for generating a memory output address of the search area data and outputting the memory address to the first storage means; Second counting means for generating a memory output address of reference block data and outputting the memory output address to the second storage means; Interpolation means for receiving interpolated search area data from the first storage means and generating interpolated search area data for half-pixel motion estimation at each half-pixel position, interpolated search area data from the interpolation means, Half-pixel motion estimation means for receiving reference block data from the second storage means and calculating a motion estimation error at each half-pixel position, and receiving motion estimation error from the half-pixel motion estimation means at each half-pixel position. And comparison means for comparing the motion estimation error of the signals.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

FIG. 1 is a diagram showing the configuration of search area and reference block data when estimating frame half-pixel motion used in the present invention, and FIG. 2 is a diagram showing the configuration of search area and reference block data when estimating field half-pixel motion used in the present invention. to be.

As shown in the figure, in the case of frame motion estimation, the reference block data has a size of 16 × 16, and the size of the search area data is 18 × 8. In the case of field half-pixel motion estimation, the reference block data has a value of 16 ×. It consists of a top field and a bottom field having a size of 8, and the search area data is 18 × 10 search area data for a reference top field and 18 × for a reference borrom field. It consists of 10 search area data.

Therefore, in case of frame half-pixel motion estimation and field half-pixel motion estimation, search area data having different sizes should be used, which requires complicated control logic. In order to solve this problem, the present invention configures reference blocks and search region data for each case of frame or field half-pixel motion estimation as shown in FIGS. 1 and 2.

That is, in the case of frame half-pixel motion estimation, the reference block having the size of 16 × 16 is divided into the reference block T of the upper 16 × 8 and the reference block B of the lower 16 × 8, as shown in FIG. 1, and has the size of 18 × 18. The search area is divided into a search area T of the upper 18 × 10 that is the search area for the reference block T and a search area B of the lower 18 × 10 that is the search area for the reference block B. At this time, the lower two rows of the upper search area T and the upper two rows of B, which is the lower search area, are composed of the same data.

In the case of field half-pixel motion estimation, the reference block and the search region data are configured as shown in FIG. In the case of frame half-pixel motion estimation, the configuration shown in FIG. 1 of the reference block and the search region data enables the frame half-pixel motion estimation to be handled in the same way as the field half-pixel motion estimation in FIG. 2. Thus, it is easy to use only simple control logic. To be implemented. In the case of frame or field half-pixel motion estimation in FIGS. 1 and 2, each reference position is both (0, 0).

3 is a configuration diagram of an apparatus for estimating a frame or field half-pixel motion according to an embodiment of the present invention, and includes a first memory 31, a second memory 32, a first counter 33, and a second counter 34. And an interpolator 35, a half-pixel motion estimation device 36, and a comparator 37.

As shown in the figure, the frame or field half-pixel motion estimation apparatus includes a first memory 31 for storing search area data, a second memory 32 for storing reference block data, and a memory output address of the search area data. A first counter 33 that generates and outputs the first output to the first memory 31; a second counter 34 and a first memory 31 that generate and output a memory output address of the reference block data to the second memory 32; Search area interpolated from interpolator 35 and interpolator 35 for receiving interpolated search area data from the integer positions and generating interpolated search area data required for half-pixel motion estimation at each half-pixel location A half-pixel motion estimation device 36 that receives data and receives reference block data from the second memory 32 and calculates a motion estimation error at each half-pixel position, and moves from the half-pixel motion estimation device 36. It receives the estimation error comprises a comparator 37 for comparing the motion estimation error in each of the half-pixel location.

Looking at the specific operation is as follows.

The second counter 34 generates a address for outputting the reference block T and the reference block B from the second memory 32 to the half-pixel motion estimation device 36 in order, and outputs the address to the second memory 32. . In the case of frame half-pixel motion estimation, the output reference block T and the reference block B are shown in FIG. 1, and in the case of field half-pixel motion estimation, the output reference block T and the reference block B are shown in FIG. At this time, the reference block T and the reference block B are output in the order of top down, left to right.

The first counter 33 generates a address for outputting the search area T and the search area B from the first memory 31 to the interpolator 35 in order and outputs the address to the first memory 31. In the case of frame half-pixel motion estimation, the search region T and the search region B outputted are the same as those in FIG. 1, and in the case of the field half-pixel motion estimation, the search region T and the search region B, which are output, are shown in FIG. At this time, the search area T and the search area B are output from the interpolator 35 in the order of top to bottom and left to right.

4 is a detailed configuration example of an interpolator of a frame or half-pixel motion estimation apparatus according to the present invention.

As shown in the figure, interpolated interpolation search area data (B) required for calculating a motion estimation error at each half-pixel position using a delay element and an adder by receiving search area data from a first memory. , C, D) are output to the half-pixel motion estimation apparatus.

That is, the interpolator is a first delay element 41 receives the search area data from the first memory and delays it for 10 clock cycles, and outputs the first delay element 41 and a delay delayed for 1 clock cycle. Receives the outputs of the first rounding adder 45 and the first rounding adder 45 that receive the outputs of the second delay element 42 and the first and second delay elements 41 and 42. A third delay element 48 that outputs interpolated search area data B delayed for a clock cycle to a half-pixel motion estimation device, and receives search area data from a first memory and outputs the first delay element 41. And a fourth delay element 43, a second round adder 44, which delays the output of the second round adder 44, the second round adder 44, and receives the output of the second round adder 44 for one clock cycle. Rounded addition is performed by receiving the output of the fourth delay element 43. A fifth delay element 49 that receives the outputs of the third rounding adder 46 and the second rounding adder 44 and outputs interpolated search area data C to the half-pixel motion estimation device by delaying for one clock cycle And a sixth delay element 47 that receives the output of the third rounding adder 46 and delays it for one clock cycle to output interpolated search area data D to the half-pixel motion estimation device.

5 is a detailed configuration example of a half-pixel motion estimation apparatus of a frame or field half-pixel motion estimation apparatus according to the present invention.

As shown in the figure, reference block data is input to all eight error accumulators, in which a delay element is used to match timing with search region data input to each error accumulator.

The half-pixel motion estimation device receives an eighth delay element 58 that receives reference block data from a second memory and delays it for one clock cycle and an eighth delayed for nine clock cycles by receiving an output of the seventh delay element 58. The ninth delay element 60, which receives the input of the delay element 59, the eighth delay element 59, and delays for one clock cycle, receives the reference block data from the second memory, and receives the reference block data from the output D of the interpolator. The first accumulator 50, which receives the search area data necessary for calculating the motion estimation error at the pixel position (-0.5, -0.5), accumulates the difference value, receives the reference block data from the second memory, Input the outputs of the second accumulator 51 and the sixth delay element 58 that receive the search area data necessary for calculating the motion estimation error at the half-pixel position (-0.5, 0) from the output C and accumulate the difference values. From the output D of the interpolator Interpolates and receives the outputs of the third accumulator 52 and the eighth delay element 59 that receive the search area data necessary to calculate the motion estimation error at the reduced position (-0.5, +0.5) and accumulate the difference values. The fourth accumulator 53 and the ninth delay element 60 that receive the search area data necessary for calculating the motion estimation error at the return location (0, -0.5) from the output B of the device and accumulate the difference value. A fifth accumulator 54 and an eighth delay element that receive the output and accumulate the difference value by receiving the search area data necessary for calculating the motion estimation error at the half-pixel position (0, + 0.5) from the output B of the interpolator A sixth accumulator that receives the output of (59) and receives the search area data necessary for calculating the motion estimation error at the half-pixel position (+0.5, -0.5) from the output D of the interpolator; 55) and the output of the eighth delay element 59 is interpolated. Of the seventh accumulator 56 and the ninth delay element 60 which receive the search area data necessary for calculating the motion estimation error at the half-pixel position (+0.5, 0) from the output C of An eighth accumulator (57) which receives the output and receives the search area data necessary for calculating the motion estimation error at the half pixel position (+0.5, +0.5) from the output D of the interpolator and accumulates the difference value. do.

FIG. 6 is a detailed structural example of an error accumulator of the half-pixel motion estimation apparatus of FIG. 5, and is a detailed structural diagram of each accumulator for accumulating errors between search area data and reference block data at each half-pixel position.

Each accumulator receives the inverted most significant 1 bit and the remaining 8 bits among the 9-bit outputs of the first adder 61 and the first adder 61 that calculates the difference between the input search area data and the reference block data. Eight exclusive OR gates 62 exclusively ORing the bits with the remaining eight bits, a register 64 for storing the motion estimation error value, and an inverted most significant one bit of the output of the first adder 61, and are exclusively received. A second adder 63 which receives the logic sum gate 62 and the output of the register 64 and adds the result is stored in the register 64 again.

When the process of accumulating the difference between the search area data and the reference block data is completed, the motion estimation error value stored in the register 64 is output to the comparator.

The comparator compares the motion estimation errors at the eight half-pixel positions output from the half-pixel motion estimation apparatus with the motion estimation errors at the (0, 0) position already obtained in the motion estimation of one pixel unit, and calculates the smallest motion estimation. The position with the error is output as a half-pixel motion vector.

In another embodiment of the present invention, the search region data is input to the interpolator from left to right and top to bottom, the first delay element is delayed for 18 clock cycles, and the eighth delay element is delayed for 17 clock cycles. The same results can be achieved if possible.

The present invention as described above has the effect of providing flexibility to perform half-pixel motion estimation for a frame or field using a simple device.

Claims (7)

A frame or field half-pixel motion estimation apparatus, comprising: first storage means for storing search area data, second storage means for storing reference block data, and a memory output address of search area data is generated and output to the first storage means A first counting means, a second counting means for generating a memory output address of the reference block data and outputting the memory output address to the second storage means, and receiving the search area data from the first storage means and half-pixels at each half-pixel position; Interpolation means for generating interpolated search area data necessary for motion estimation, interpolated search area data received from the interpolation means, reference block data received from the second storage means, and motion estimation at each half-pixel position From half-pixel motion estimation means for calculating an error, and from the half-pixel motion estimation means Receiving the jikim estimation error frame comprising a comparison means for comparing the motion estimation error in each of the half-pixel locations or fields half-pixel motion estimator. The reference block data and the search region data of claim 1, wherein the reference block having a size of 16 × 16 is divided into a reference block T of an upper 16 × 8 and a reference block B of a lower 16 × 8, and has a size of 18 × 18. A search area having a subfield is divided into a search area T of the upper 18 × 10 search area T for the reference block T and a search area B of the lower 18 × 10 search area B for the reference block B. And the upper two rows of B, which are the lower search region, are composed of the same data. The apparatus of claim 1, wherein the interpolation means comprises: first delay means for receiving and delaying outputting search area data from the first storage means, second delay means for receiving and delaying the output of the first delay means; First adding means for receiving the output of the first and second delay means for performing the addition, and outputting the interpolated search region data to the half-pixel motion estimation means by receiving the output of the first adding means and delaying the input. A third delay means, a second addition means for receiving search area data from the first storage means, an output of the first delay means for performing addition, and a fourth delaying for receiving an output of the second addition means; Third adding means for receiving the output of the delay means, the second adding means and the fourth delay means and performing addition; Fifth delay means for receiving the output of the second addition means and outputting the reinforcement-reinforced search region data to the half-pixel motion estimation means, and search region data for which the third addition means is delayed by receiving the output. And a sixth delay means for outputting the to the half-pixel motion estimation means. 4. The apparatus of claim 3, wherein the half-pixel motion estimating means comprises: seventh delay means for receiving and delaying reference block data from the second storage means, and eighth delay means for receiving and delaying the output of the seventh delay means. And ninth delay means for receiving and delaying the output of the eighth delay means, and search region data required to receive reference block data from the second storage means and calculate a motion estimation error at a half-pixel position from the interpolation means. Receives the reference block data from the first accumulation means and the second storage means and accumulates the difference value, and receives the search area data necessary to calculate the motion estimation error at the half-pixel position from the interpolation means. A second accumulating means for accumulating a value, an output of the seventh delay means and receiving a half pixel position from the interpolation means; A third accumulating means for receiving the search area data necessary for calculating a motion estimation error of the second accumulating means and an output of the eighth delay means and calculating a motion estimation error at a half-pixel position from the interpolation means. A fourth accumulating means for receiving the required search region data and accumulating a difference value; an input of an output of the ninth delay means, and receiving a search region data necessary for calculating a motion estimation error at a half-pixel position from the interpolation means. Fifth accumulating means for accumulating a value, and sixth accumulating means for accumulating a difference value by receiving the output of the eighth delay means and receiving search area data necessary for calculating a motion estimation error at a half-pixel position from the interpolation means. And receives the output of the eighth delay means from the half-pixel position from the interpolation means. Seventh accumulating means for receiving the area data necessary for calculating the motion estimation error and accumulating the difference value, and inputting the output of the ninth delay means and calculating the motion estimation error at the half pixel position from the interpolation means. And an eighth accumulating means for receiving the search area data and accumulating a difference value. 5. The apparatus of claim 4, wherein each accumulating means comprises: fourth adding means for calculating a difference between input search area data and reference block data, and receiving the inverted most significant bit and the remaining bits from the output of the fourth adding means; A plurality of exclusive OR operation means for exclusively ORing the inverted most significant bit with the remaining bits, third storage means for storing a motion estimation error value, and an exclusive OR operation means for receiving the inverted best bit of the fourth addition means. And fifth adding means for receiving an output of the third storage means and adding the result to the third storage means. 5. The method of claim 4, further comprising inputting search region data into the interpolation means from left to right and from above, causing the first delay means to be delayed for 18 clock cycles, and causing the eighth delay means to be delayed for 17 clock cycles. A frame or field half-pixel motion estimation device. 2. The apparatus according to claim 1, wherein the comparing means has already performed motion estimation errors at eight half-pixel positions, motion estimation errors at half-pixel positions, and one pixel-based motion estimation output from the half-pixel motion estimation means. And outputting the frame having the smallest motion estimation error as a half-pixel motion vector by comparing the motion estimation errors at the obtained (0,0) position with each other. Frame or field half-pixel motion estimation device, characterized in that.