KR100210384B1 - A quantizer - Google Patents

Abstract

The present invention relates to a quantizer including a RAM, a RAM controller, an operation control unit, and an operation unit. The RAM controller 30 writes the quantization matrix so that a pair of matrix data is not stored in the same memory regardless of a scanning method. Write address generating means for generating an address; Data distributing means (16) for distributing the quantization matrix data stored according to the write address to the RAM (26); Read address generating means for generating a corresponding read address according to a scan method to read a quantization matrix stored in the RAM 26 when a macroblock for quantization is started; And data combining means for combining the data output by the RAM accessed by the read address generating means according to a coding method and a scanning method and outputting the data to the operation controller 32, wherein the RAM has a plurality of sub-RAMs. It is composed of the first and second memory banks RAM0 and RAM1 to prevent data collision according to the scanning method and to store the quantization matrix using a small amount of memory, thereby making it easier to convert a dedicated chip (ASIC). .

Description

Quantizer

1 is a block diagram showing a general video encoder.

2 (a) is a view showing a natural image stored in the frame memory unit shown in FIG.

FIG. 2 (b) shows an image obtained by dividing the natural video shown in FIG. 2 (a) into 8 × 8 pixel blocks.

FIG. 2 (c) shows an image in which 8x8 pixel blocks shown in FIG. 2 (b) are converted by a discrete cosine transformer (DCT).

FIG. 2 (d) shows an image in which the discrete cosine transformed image shown in FIG. 2 (c) is quantized by a quantizer.

3 is a block diagram illustrating a quantizer according to the present invention.

FIG. 4 is a block diagram illustrating a RAM and a RAMCON shown in FIG. 3.

* Explanation of symbols for main parts of the drawings

10,12: first and second counter 14,18: first and second PLA

16: DIV 20: CAT

22,24: first and second multiplexer 26: RAM

30: RAMCON 32: operation control unit

34: core

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quantizer in an image encoder, and is particularly suitable according to a zigzag scan method or an alternate scan method of image data downloaded in a zigzag method and stored in a memory. The present invention relates to a quantizer that is addressed to perform quantization.

In general, in an image encoder, image data input to a quantizer is discrete cosine transformed by a discrete cosine converter (DCT) and then directly input to a quantizer.

1 is a block diagram showing a general image encoder, which includes a frame memory unit 100, a subtractor 120, a discrete cosine transformer (DCT: 120), a quantizer (Q: 140), and a variable length encoder (VLC). 150), an inverse quantizer (IQ: 160), an inverse discrete cosine transformer (IDCT: 170), an adder 180, and a motion compensator (MC: 190).

As the image encoder is well known, the current image signal input through the frame memory unit 100 and the previous image signal input from the motion compensator 190 (MC) are input to the subtractor 102, and then. The image data from the subtractor 102 is input to the discrete cosine converter 130 to perform discrete cosine conversion. Next, the discrete cosine-transformed image data by the discrete cosine converter 130 is input to the quantizer 140 to perform quantization, and the compression coding is performed by performing zigzag scan with run length coding and variable length coding. Will be.

2 (a) to (d) are diagrams for explaining a concept of converting and quantizing discrete cosine by converting a natural image photographed through a video camera into digital.

FIG. 2 (a) shows a natural image stored in the frame memory unit shown in FIG. 1, and FIG. 2 (b) shows an image obtained by dividing the natural image shown in FIG. 2 (a) into 8 × 8 pixel blocks. FIG. 2 (c) shows an image in which the 8x8 pixel block shown in FIG. 2 (b) is converted by the discrete cosine converter (DCT), and FIG. 2 (d) is the second (c). FIG. 11 shows an image of an abnormal cosine transformed image quantized by a quantizer.

Here, the diagram shown in FIG. 2 (a) shows one natural image, for example, 352 × 288 pixels divided into 8 × 8 pixel square pixel blocks, and then each pixel block is sequentially input to a discrete cosine converter. Indicates.

2 (b) shows that 8 × 8 pixel blocks of the natural image shown in FIG. 2 (a) are allocated from a ₁ to a ₆₄ in a two-dimensional space, ) shows the turning of claim 2 (b) is Ido 8 × 8 pixel block illustrated in the discrete cosine transform from the low-frequency section (1) separated by a high frequency, wherein (2) the distribution in sequence (b ₁ ~b _64).

FIG. 2 (d) shows a quantized block by dividing each coefficient after the discrete cosine transform into a predetermined divisor, that is, a quantization step and a quantization matrix as shown in FIG. 2 (c). It can be seen that data is compressed through DCT and quantization, as shown sequentially in FIGS. 2 (a) to (d).

In the conventional video encoder, the scanning process is conventionally performed after the quantization of the image data. However, in the practical aspect of designing the image encoder, the scanning process is performed after the discrete cosine transform, that is, before the quantization. It was required to be processed.

However, when a scan operation is performed before quantization as described above, since the scan operation supported by MPEG-2 includes a zigzag method and an alternate method, the quantizer must support at least these two methods.

In other words, in MPEG, quantization is an adaptive quantization scheme in which weights are varied according to spatial frequencies. For this purpose, an intra block is a weight matrix for quantization (hereinafter, referred to as an intra quantizer matrix) and a weight matrix for quantization of an interblock. In this case, the input (or transmission) order of these matrices is recommended as one of the zigzag methods, but the input order of the image data varies depending on the scanning method. Therefore, in order to scan before quantization, the order of the matrix and the order of data must be matched according to the scanning method.

In particular, in order to process image encoding quickly, it is necessary to accurately match the input data pair and the matrix pair when the quantizer simultaneously processes two pixels.

Accordingly, the present invention is to meet the above-mentioned needs, and by simplifying the capacity of the memory in quantizing the image data input by the zigzeg scan method or alternate scan method according to the corresponding quantization matrix and quantization scale It is an object of the present invention to provide a quantizer for facilitating an ASIC.

In order to achieve the above object, according to the present invention, a RAM controller appropriately addresses and quantizes a predetermined quantization matrix, which is downloaded in a zigzag manner and stored in a RAM according to a scanning method of input image data. In the quantizer configured to read the matrix, obtain the inverse of the quantization matrix and the inverse of the quantization scale value input from the system control unit, and then calculate the reciprocals and the input image data in the operation unit. A write address generating means for generating a write address for storing the quantization matrix so that a RAM controller does not store a pair of matrix data in the same memory according to a scan method; Data distribution means for distributing the quantization matrix data stored according to the write address to a RAM; Read address generating means for generating a corresponding read address according to a scan method to read a quantization matrix stored in the RAM when a macroblock for quantization is started; and coding data output by a RAM accessed by the read address generating means A data combining means for combining and outputting to the operation control unit according to a scanning method and a scanning method, wherein the RAM comprises first and second memory banks for storing intra and inter quantization matrices, and each of the memory banks It is characterized by consisting of a plurality of sub-ram.

As described above, since the quantizer according to the present invention uses two memory banks and each memory bank is divided into three sub-RAMs, when a pair of matrix data stored in a zigzag method is read in alternate manner, the pair of matrix data is the same sub-band. It can be stored in RAM to prevent collision. Therefore, the capacity of the RAM for storing the quantization matrix can be reduced, thereby facilitating the dedicated chip (ASIC).

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in MPEG-2, quantization is processed in 8 × 8 block units, such as a discrete cosine transform (DCT). The quantization of the discrete cosine transformed coefficients according to a coding scheme (either intra coding or inter coding) is performed. After dividing by the matrix, the amount of data generated by dividing by the quantization scale determined by the rate control method is reduced.

As described above, the quantization matrix is designed to assign weights differently according to spatial frequencies in consideration of human visual characteristics in the adaptive quantization scheme. The quantization matrix has an 8x8 matrix and corresponds to image data. An intra quantizer matrix for quantization of blocks and a non_intra quantizer matrix for quantization of inter coded blocks are divided. In this case, MPEG2 recommends that a user defined matrix or a default matrix is used as an intra and inter quantization matrix. Therefore, when the user randomly defines and uses a matrix, the quantization matrix should be transmitted from the encoding end (transmitter) to the decoding end (reception) as a header on the MPEG bitstream. And as shown in Table 2. At this time, it is recommended that the quantization matrix is downloaded in a zigzag manner.

As shown in Table 1, the intra quantization matrix narrows (quantizes) the quantization interval in the low frequency band and performs quantization coarse in the high frequency band. This affects the picture quality of the low frequency part but does not affect the high frequency part. In addition, since the interblock is obtained by encoding a differential image by motion compensation, most of the data is only in the low frequency part and the high frequency part is small, so that the weight is evenly distributed as shown in Table 2 above.

In addition, the quantization scale is determined by the complexity of the original image and the fullness of the buffer in order to properly control the amount of data generated at the time of encoding according to the rate control (or also called buffer control) method. In MPEG2, the quantization scale value determined at the time of encoding is transmitted to the decoder through a header (eg, q_scale_type, quantizer_scale_code) of the bitstream.

Next, the quantizer according to the present invention will be described based on the above understanding of MPEG quantization.

FIG. 3 is a block diagram showing a quantizer according to the present invention, and FIG. 4 is a detailed block diagram showing a RAM and a RAMCON shown in FIG.

As shown in FIG. 3, the quantizer of the present invention is composed of a RAM controller 30, a RAM 26, an operation controller 32, and an operation unit 34. quant_scale_type, quant_scale_code) are downloaded, and image data is input from a discrete cosine converter to perform quantization.

First, in order to facilitate understanding in FIG. 3 and FIG. 4, the signals inputted to and outputted from each block are generally defined, and then described for each component block.

In FIG. 3, CLK is a system clock and RST is a reset signal operating in active low.

ID_CD is an identifier (ID) of a quantization matrix input from a system controller (not shown) and quantization matrix data (CD) input following the identifier, and flag_ID is a signal indicating whether the ID_CD currently input is an identifier (ID). If flag_ID is 'high', ID is inputted to ID_CD. Here, ID is a matrix identifier defined in order to distinguish the quantization matrix from the encoder, and it can distinguish whether the input quantization matrix is intra or inter.

Also, mbs is a signal indicating a macroblock start, and quant_scale_code and quant_scale_type are signals defined in MPEG2 to indicate the value of the quantization scale, and quant_scale_type is defined as in the MPEG recommendation (MPEG IS: Table 7-6). The value of the quantization scale is determined by 0 or 1 and a 5-bit quant_scale_code value.

These values are determined by a rate controller and a system controller (not shown), input to the quantizer according to the present invention, and transmitted to the decoding end.

In addition, dc_pre is a 2-bit signal in the picture_coding_extension in MPEG2, which indicates the magnitude (precision) of the DC coefficient in the intra block. For example, 0 indicates that the DC coefficient is expressed in 8 bits and 3 indicates 11 bits. Indicates that

In addition, data_even and data_odd are data of a unit of 2 pixels input from the discrete cosine transformer, and Quant_even and Quant_odd represent data that is output by quantizing the input 2 pixel data.

In FIG. 3, the RAM 26 is a memory for storing a user-defined matrix or a default matrix, which is input from a system controller (not shown), and is divided into an intra quantization matrix and an inter quantization matrix as described above. At least two 8-bit 64-word memory banks are required to store each.

However, since the quantization matrix is downloaded in a zigzag manner but the image data is input in a zigzag manner or an alternate manner, an address conversion is required in order to read the matrix stored in the zigzag manner in the alternate manner. Furthermore, in order to simultaneously process the quantization process in units of 2 pixels, it is necessary to read a pair of matrices. When an 8-bit 64 word is implemented as one RAM, a pair of matrix data stored at different addresses of the same memory can be simultaneously accessed. Therefore, in the RAM 26 according to the present invention, when a 64 word memory is divided into three sub-RAMs which can be accessed at the same time, a pair of matrix data is the same when the data stored in the zigzag method is read in the alternate method. It is not stored in the sub ram.

To this end, the RAM 26 of the present invention is divided into a first memory bank RAM0 for storing an intra quantization matrix and a second memory bank RAM1 for storing an inter quantization matrix, as shown in FIG. It is. The first memory bank RAM0 includes two sub-RAMs OP_RAM0-1 and OP_RAM0-2 composed of 8 bits × 22 words and one sub-RAM OP_RAM1 composed of 8 bits × 20 words. The two memory banks RAM0 are composed of two sub-RAMs OP_RAM0-1 'and OP_RAM0-2' composed of 8 bits x 22 words and one sub-RAM (OP_RAM1 ') composed of 8 bits x 20 words.

The first sub-rams OP_RAM0-1 and OP_RAM-1 'are respectively accessed by the address add1 to input and output 8-bit data dat1a and data2a, respectively, where the address add1 is 22 words as described above. Since it is 00-15, it is input from the 1st PLA 14 and the 1st multiplexer 22. As shown to FIG. The second sub-rams OP_RAM0-2 and OP_RAM-2 'are each accessed by the address add2 to input and output 8-bit data dat1b and data2b, respectively. In this case, since the address add2 is 22 words as described above, 00 It is -15 and is input from the 1st PLA 14 and the 1st multiplexer 22. In FIG. The third sub-rams OP_RAM0-3 and OP_RAM-3 'are respectively accessed by the address add3 to input and output 8-bit data dat1c and data2c, respectively. In this case, the address add3 has 20 words as described above. Since it is 00-13, it is input from the 1st PLA 14 and the 1st multiplexer 22. As shown to FIG.

In addition, the RAM controller 30 operates according to the system clock CLK and the reset RST signal to store the quantization matrix input through ID_CD in the RAM 26, and reads the quantization matrix stored in the RAM 26. This is for outputting to the control unit 32.

As shown in FIG. 4, the RAM controller 30 includes a first counter 10, a first PLA 14, a DIV 16, a second counter 12, a second PLA 18, and a first multi. It consists of a flexor 22, a second multiplexer 24, and a CAT 20, and interprets the ID inputted through ID_CD while the flag_ID is high. After identifying whether it is a quantization matrix, the quantization matrix data (CD) which is subsequently input is stored in the corresponding memory bank of the RAM 26 and the matrix stored in the memory bank in synchronization with the start signal (mbs) of the macroblock. The data is read and output to the operation control unit 32.

In FIG. 4, the first counter 10 and the first PLA 14 of the RAM controller 30 generate a write address for storing matrix data input from a system controller not shown in the memory banks RAM0 and RAM1. DIV 16 is a distribution unit for distributing the matrix data input by ID_CD to the corresponding sub-RAM of the memory bank, the second counter 12 and the first and second PLAs 14 and 18, and The first multiplexer 22 is a read address generator for reading the quantization matrix stored in the RAM 26, and the second counter 12, the CAT 20, and the second multiplexer 24 are connected to the read address. Is a data combiner for combining the data read by the data and outputting the data properly according to the scanning method.

That is, the first counter 10 clears the count value by the reset signal RST and counts according to the clock CLK to generate a count value. At this time, while the flag_ID is high, the ID data inputted to the ID_CD is analyzed to determine whether it is an intra or inter quantization matrix, and if the ID is correct, the count value is set to the first PLA 14. And to DIV (16).

Subsequently, when the first PLA 14 reads the zigzag matrix data stored in the zigzag method alternately according to the output of the first counter 10, the first PLA 14 does not store the pair of matrix data in the same sub-RAM as shown in Table 3 below. Addresses add1 to add3 are generated.

As shown in Table 3, when the count value of the first counter is 0, the first PLA 14 is 00 (add1) as the first subram (OP_RAM0-1, OP_RAM0-1 '), and the second subram (OP_RAM0_2, OP_RAM0-2 ') outputs an address 00 (add2). Therefore, when the count value is 0, the matrix data is stored at address 0 of the first sub-ram (OP_RAM0-1 and OP_RAM0-1 ') and address 0 of the second subram (OP_RAM0-2 and OP_RAM0-2'). . Subsequently, when the count value is 1, the first PLA 14 outputs one address add2 to the second sub-ram (OP_RAM0-2. OP_RAM0-2 ') and 0 to the third sub-ram (OP_RAM2 and OP_RAM2'). Output the address. Therefore, when the count value is 1, the matrix data is stored in address 1 of the second subram and address 0 of the third sublam. In the same manner, as the count value changes from 00 to 1F (0 to 31), the first and second subrams output addresses (add1 and add2) from 00 to 15 (0 to 21), and the third subram To add addresses 3 to 00 to 13 (0 to 19). In other words, the first PLA 14 generates an address for accessing the first and second subrams and an address for accessing the third subram according to the output of the first counter.

In this case, when the input quantization matrix is intra, the quantization matrix is stored in the sub-rams of the first memory bank RAM0. If the input quantization matrix is intra, it is stored in the sub-rams of the second memory bank RAM1.

In addition, the DIV 16 properly distributes the matrix data input in 16 bits through the ID-CD according to the output of the first counter and outputs the data to three sub-rams (each 8-bit RAM). Data assigned to the sub-RAM is shown in Table 4 below. Here, the quantization matrix input through ID_CD is loaded in a zigzag manner and sequentially stored in the memory.

In Table 4, when the count value input from the first counter is 0, the 16-bit matrix data input through the ID-CD and the first subram (OP_RAM0-1 and OP_RAM0-1 ') and the first sub-RAM are input. It divides and stores 2 sub-rams (OP_RAM0-2 and OP_RAM0-2 '). If the counter value is 1, 16-bit matrix data input through ID-CD is distributed to 3 sub ram and 2 sub ram. . In the same manner, 16 bits of data are appropriately distributed through the data buses data1a / data2a, data1b / data2b, and data1c / data2c to the three subrams until the count value is 00 to 1F. At this time, the sub-RAM to which the address is allocated according to Table 3 and the sub-RAM to which data is distributed according to Table 4 must match for the same count value. Since the order of the quantization matrix input from the system control unit is in the order of the zigzag method, the first PLA 14 eventually stores the data input in the zigzag method sequentially in each sub-ram, and thus the input image data is zigzag. In the case of the scheme, the first PLA may also be used for generating a read address.

On the other hand, the second counter 12 counts according to the clock signal after clearing the count value by the reset signal RST. After the rising signal of the macroblock start signal mbs is detected, the second counter 12 outputs the count (counter sequence stream). It starts with the: counter sequence stream and sends it to the translation address generator 19 and the data combiner (CAT: 20).

The conversion address generating unit 19 generates an address for reading the first PLA 14 to generate an address for reading the zigzag matrix data stored in the zigzag manner and the quantization matrix stored in the zigzag manner alternately. It is composed of a second PLA (18). Here, the first PLA 14 is configured in the same manner as the first PLA 14 of the write address generator, and generates a zigzag read address according to the second counter output (count value) as shown in Table 3 above.

In addition, according to the output of the second counter 12, the second PLA 18 generates an address for reading matrix data stored in a zigzag manner in the alternate manner as shown in Table 5 below.

In Table 5,-is don't care, and as shown in Table 5, the second PLA 18 is moved from the first to third subrams according to the output (count value) of the second counter. Addresses (add1 to add3) for reading the matrix data are generated. That is, when the count value is 0, an address is generated to read data from 00 of the first and third subrams, and when 1, the address is stored at 01 of the second sublamb and 02 of the third sublamb. Generates an address to read data. In the same way, when the count value is 2, it reads the data by accessing address 01 of the first subram and address 00 of the second sublam, and when 3 counts 01 of the second subram and 01 of the third sublam. Access the address to read the data. Here, it can be seen that an address generated by the second PLA 18 is generated out of order in order to read matrix data stored in a zigzag manner in an alternate manner. This is because the order of the data is different according to the scanning method. When storing the matrix data so that no data collision occurs when reading a pair of matrix data by the second PLA 18, the first PLA 14 properly stores the data in three sub-RAMs. Dispersed.

In addition, the first multiplexer 22 receives a scan method signal zz_alter from a system controller (not shown) and selects one of an output of the first PLA 14 and an output of the second PLA 18, thereby selecting an address bus ( Output to memory via add1 to add3).

For example, if the scan signal is 0 and the data inputted from the ideal cosine converter to the computing unit 34 of the quantizer is zigzag, the quantization matrix stored in the RAM 26 is also zigzag scanned according to the first PLA 14 of the write address generator. In this way, the first multiplexer 22 selects the output of the first PLA 14 to read the quantization matrix as shown in Table 3 above. On the contrary, when the scan method signal zz_alter is 1 and the data inputted from the ideal cosine converter to the operation unit 34 of the quantizer is the alternate method, the first multiplexer 22 selects the second PLA 19 to subram. The matrix stored in the field is read by the alternate scan method according to Table 5 above.

On the other hand, the second multiplexer 24 selects the data outputs (data1a, 1b, 1c) of the first memory bank in which the intra quantization matrix is stored in the intra coding scheme according to the coding identification signal inter_intra input from the system controller. In the case of the intercoding method, the outputs data2a, 2b, and 2c of the second memory bank in which the inter quantization matrix is stored are selected. For example, when the intrablock is quantized, if the coding identification signal inter_intra input from the system controller is 1 (in the embodiment of the present invention, inter_intra is 1, the intra coding scheme is defined). Accordingly, the second multiplexer 24 ) Selects the outputs (data1a, 1b, 1c) of the first memory bank.

In addition, the data combiner CAT 20 selects 8 bits of the corresponding sub-RAM according to the output of the second counter 12 from 8 bits x 3 data of the memory bank output by the second multiplexer 24. After the selection, the 16 bit matrix data is combined and output to the operation control unit 32. For example, when the input image data is an alternate method, the CAT 20 selects and combines two of the outputs of the three sub-ramms according to the output of the second counter as shown in Table 6 below.

As shown in Table 6, when the output of the second counter is 0, the CAT 20 selects and combines outputs of the first and third subrams, and if 1, outputs the outputs of the second and first subrams. 2, the output of the second subram and the first subram.

In FIG. 3, the operation unit 34 actually processes an operation performed by the quantizer, and divides the input image data into a quantization matrix and a quantization scale value to perform quantization. However, in general, in order to perform a division operation, hardware becomes complicated and a processing speed becomes slow. Therefore, in the quantizer to which the present invention is applied, the inverse of the data to be divided is calculated in advance in the operation control unit 32, and then the operation unit 34 multiplies them. It is supposed to process by.

That is, the operation control unit 32 operates according to the reset and the system clock to calculate and output the inverse of the even / odd matrix input from the RAM controller 32, respectively, and the quantization scale from the quantization type and the quantization code input from the system controller. After calculating the value, the reciprocal is obtained and the output is divided into even / odd. After receiving the dc_prec from the system controller, the predetermined DC value is calculated and the reciprocal is obtained.

The operation unit 34 multiplies the inverse of the quantization scale input from the operation control unit by a pair of data scanned and input from the discrete cosine converter in a predetermined manner, and then multiplies the result of the quantization matrix by the inverse of the quantization matrix and then rounds the result. Output even / odd data. In this case, the operation unit 34 multiplies the pair of data (data_even, data_odd) input from the operation control unit 32 with the pair of data in a pipelined manner to improve the processing speed and according to the present invention. According to the scanning method of the data, the matrix order is also matched to perform quantization.

On the other hand, the reference numerals written in the configuration requirements of the claims of the present application to facilitate the understanding of the present invention, not intended to limit the technical scope of the present invention to the embodiments shown in the drawings.

As described above, according to the present invention, quantization is performed on the matrix data input by the zigzag scan method and the alternate scan method, and data collision at the time of reading is performed by appropriately dividing the 64 word matrix data into three sub-rams and storing them. Can be prevented. Therefore, it is possible to prevent the data collision according to the scan method and to store the quantization matrix using a small memory, so that the ASIC can be easily formed.

Claims (6)

The RAM controller 30 reads the quantization matrix appropriately according to the scanning method of the image data inputted by the predetermined scan method that the predetermined quantization matrix is downloaded in a zigzag manner and stored in the RAM 26, and the quantization matrix is read. After calculating the inverse of the matrix, the inverse of the quantization matrix input from the system controller, and the inverse of the quantization scale value input from the system controller, the operation controller 32 calculates the inverses and the input image data. A write address generating means for generating a write address for storing the quantization matrix so that the RAM controller 30 does not store a pair of matrix data in the same memory regardless of the scanning method. The quantum stored according to the write address Data distributing means (16) for distributing speech matrix data to the RAM (26); Read address generating means for generating a corresponding read address according to a scan method to read a quantization matrix stored in the RAM 26 when a macroblock for quantization is started; And data combining means for combining the data output by the RAM accessed by the read address generating means according to a coding method and a scanning method, and outputting the combined data to the operation control unit 32, wherein the RAM 26 is intra and inter. A quantizer, comprising: first and second memory banks (RAM0, RAM1) for storing a quantization matrix, wherein each of the memory banks comprises a plurality of sub-RAMs. The method according to claim 1, wherein the write address generating means clicks on a count value according to a reset (RST) signal, and if a flag ID flag_ID is high, a matrix identifier ID is interpreted to determine a quantization matrix, and then a clock ( A first counter 10 that counts according to CLK and generates a write address; And a first PLA (14) for generating a write address according to the output of the first counter (10). 2. The apparatus of claim 1, wherein the read address generating means comprises: a second counter 12 counted by a clock CLK in accordance with a macro block start signal mbs; An address conversion unit (19) for generating an address for reading the quantization matrix stored in the RAM (26) in a zigzag manner in a zigzag or alternate manner according to the output of the second counter; And a first multiplexer (22) for selecting the output of said address conversion section (19) in accordance with a scanning method. 4. The apparatus of claim 1 or 3, wherein the address conversion unit (19) comprises: a first PLA (14) for generating an address for accessing the RAM (26) in a zigzag manner; And a second PLA (18) for generating a read address for reading the matrix data stored in a zigzag manner in an alternate manner. 2. The apparatus of claim 1, wherein the data combining means comprises: a second multiplexer (24) for selecting one of a quantization matrix and an inter quantization matrix stored in the RAM (26) according to a coding scheme (inter_intra); And a combiner (CAT) for selecting and combining the output of the second multiplexer (24) according to the output of the second counter (12) to output matrix data. The first and second memory banks of claim 1, wherein the first to second memory banks each include an 8-bit 22-word first subram (OP_RAM0-1 and OP_RAM0-1 ') and an 8-bit 22-word second subram (OP_RAM0-2, OP_RAM0-2 '), and 8-bit 20-word third subrams (OP_RAM1, OP_RAM1'), respectively.