KR100209196B1 - A recording/reproducing speed controller in dvcr - Google Patents

Abstract

In the digital VCR, a predetermined clock is recorded on a video tape during recording, and the reproduction speed is controlled to be the same as the recording speed on the basis of the predetermined clock when the video tape is reproduced, thereby eliminating a time error occurring during recording and reproduction, The present invention provides a recording / reproducing speed control apparatus for a digital VCR, which is capable of controlling the recording / reproducing speed of the digital VCR, A dividing means for recording on a tape through a recorder; And counting means for counting the clock and outputting the switching pulses to the servo system at predetermined intervals so as to control the drum speed at the time of recording. The apparatus for controlling the reproduction speed of the digital VHSR according to the present invention comprises: Amplifying means for amplifying a signal of a sinusoidal waveform read at a predetermined level; Comparing means for comparing a sinusoidal signal output from the amplifying means with a reference clock and outputting a clock in the form of a square wave having the same frequency and phase as the sinusoidal signal; A PLL means for receiving a clock output from the comparison means and locking the PLL to output a stable clock having the same frequency and phase as that of the PLL to a reproduction system; And counting means for counting a clock output from the PLL unit and outputting a switching pulse to the servo system at predetermined intervals so as to control the drum speed during reproduction.

Description

Recording / playback speed control device of digital VHSR

In the digital VCR, a clock of a certain frequency is recorded on an audio track of a video tape during recording, and the clock is read at the time of reproduction to control the drum motor on the basis of the clock, And a recording / reproducing speed control apparatus for a digital VCR that can reduce a size of an output buffer for buffering reproduction data by eliminating a time error between data to be reproduced and a data to be reproduced.

Generally, in a recorder for recording data on a video tape, a clock of 1/30 second (30 Hz) is reproduced based on a clock generated from a vertical sync signal of data to be recorded, so that the drum is rotated 30 times per second The data is recorded by controlling the speed of the drum motor.

In addition, at the time of reproduction, a 1/30 second clock is generated based on the clock generated from the crystal oscillator inside the digital V-serial and the data recorded on the tape is reproduced by controlling the drum motor by this clock.

However, in this conventional technique, a clock by a vertical synchronizing signal is used for data recording, and a time error occurs by using an oscillator inside the digital V-series during reproduction.

In order to absorb this error, an output buffer is provided at the output stage of the reproducing system. Since the size of the output buffer is limited, an error is accumulated between the reproduction data applied to the output buffer over time, The data can not be output from the output terminal due to discarding, and stable reproduction can not be performed.

In order to improve the above disadvantages, in order to improve the above disadvantages, a clock of a certain frequency related to a recording speed is recorded in an audio track of a video tape at the time of recording, and the drum motor is controlled on the basis of this clock, So that stable reproduction can be achieved even when the size of the buffer is reduced to a minimum.

FIG. 1 is a block diagram of a recording speed control apparatus for a digital VCR according to the present invention. FIG.

FIG. 2 is a block diagram showing an apparatus for controlling the speed of reproduction of digital Vinyls according to the present invention. FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

100,231 divider 110,240 counter

200: audio head 210:

220: comparison unit 230:

232: phase comparison unit 233: damping unit

234: Voltage control oscillation portion

In order to accomplish the above object, the apparatus for controlling the recording speed of a digital VHS according to the present invention includes a divider 100 for dividing a clock CLK having a predetermined frequency by N and recording it on a tape through an audio recorder (not shown) ); And a counter 117 for counting the clock CLK and outputting a switching pulse (SW pulse) to the servo system (not shown) at predetermined intervals so as to control the drum speed at the time of recording .

Also, an apparatus for controlling the reproduction speed of a digital VHS signal according to the present invention includes: an amplifier 210 for amplifying a signal of a sinusoidal waveform read from an audio head 200 by a predetermined level; A comparator 220 for comparing a sinusoidal signal output from the amplifier 210 with a reference clock signal CLK 'and outputting a clock having a square wave form having the same frequency and phase as the sinusoidal signal; A PLL unit 230 which receives a clock output from the comparator 220 and locks it and outputs a stable clock CLK having the same frequency and phase as that of the PLL to a reproduction system; A counter 240 for counting a clock CLK output from the PLL unit 230 and outputting a switching pulse (SW) to the servo system (not shown) at predetermined intervals so as to control the drum speed during reproduction And a control unit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, it is assumed that the clock source used at the time of recording and at the time of reproduction has a clock frequency of 5.76 Mbps.

The recording speed control apparatus for a digital V-shaped signal according to the present invention will be described. A clock CLK inputted at a frequency of 5.76 MHz is applied from a divider 100 and divided into 64 clocks to generate a clock frequency of 90 KHz. Not shown).

At this time, the clock frequency of 90 KHz is recorded in the audio track by the audio recorder (not shown) because the bias of the audio track in VHS is 70 KHz, so that the frequency in the vicinity is the most suitable frequency to record.

The reason for using the audio track is that in the case of the digital VCR, both the video data and the audio data are recorded on the video track, so that the audio track is empty without any data.

On the other hand, the counter 110 counts an input clock CLK with a frequency of 5.76 MHz and outputs one pulse per 192000 bits, thereby switching a 30 Hz switching pulse (SW) to a servo system (not shown) And the drum speed at the time of recording is controlled to be constant.

Therefore, by reading the 90 KHz clock frequency recorded on the audio track at the time of reproduction, it is possible to have the same reproduction speed as at the time of recording.

The audio head 200 reads a signal of 90 KHz recorded on an audio track by the recording apparatus described above and applies the read signal to the amplification unit 217 The amplification unit 210 amplifies the signal to a level suitable for processing the signal and outputs the amplified signal.

At this time, the signal read from the audio head 200 is a sinusoidal signal.

The comparator 220 compares a sine wave signal of 90 KHz outputted from the amplifier 210 with a reference clock signal CLK 'to generate a square wave clock having the same frequency and phase as the reproduced sine wave signal, (230).

The PLL unit 230 receives the clock output from the comparator 220 and outputs a clock signal CLK of 5.76 Mb7s having a stable frequency and phase as in the case of recording to the reproduction system. do.

The phase comparator 232 compares the phases of the 90 kHz pulses received at the frequency of 5.76 Mbps from the divider 231 with the pulse of 90 kHz outputted from the comparator 220 and divides them into 64 phases, When the phase difference is detected, the damping unit 233 corrects the phase difference by reducing the phase difference detected from the phase comparing unit 232.

The 90 KHz pulse whose phase difference has been corrected by the damping unit 233 is applied to the voltage control oscillator 234 and oscillated by the control voltage to oscillate a clock CLK having a frequency of 5.76 Mbps, which is the same as that at the time of recording.

The clock CLK oscillated in this way is fed back to the divider 231 and divided into 64 clocks, whereby a clock having a frequency of 90 KHz is input to the phase comparator 232 to form a PLL loop.

The counter 240 receives a clock of 5.76 Mbps output from the voltage control oscillator 234 of the PLL unit 230 and counts a pulse for every 192,000 bits to output a switching pulse SW, To the servo system (not shown) to control the drum speed at the time of reproduction to be constant.

As described above in detail, according to the present invention, a recording / reproducing speed control apparatus for a digital VHS is configured such that a predetermined clock is recorded on an audio track at the time of recording, and then, The size of the output buffer can be prevented by preventing the data temporarily stored in the buffer from being overflowed or from being leaked, and stable reproduction can be achieved.

Claims (12)

Dividing means for dividing N clocks having a predetermined frequency by N and recording them on a tape through an audio recorder; And counting means for counting the clock and outputting a switching pulse to the servo system every predetermined time so as to control the drum speed at the time of recording. The apparatus of claim 1, wherein the frequency of the clock input to the frequency divider is 5.76 Mbps. The apparatus of claim 1, wherein the frequency divider divides the input clock by 64 times. The apparatus of claim 1, wherein the 64 clocks divided by the divider means are recorded on an audio track on the tape through an audio recorder. The apparatus of claim 1, wherein the counting means counts the input clock so that one pulse is output every 192000 bits. Amplifying means for amplifying a signal of a sinusoidal waveform read from the audio head at a predetermined level; Comparing means for comparing a sinusoidal signal output from the amplifying means with a reference clock and outputting a clock having a square wave form having the same frequency and phase as the sinusoidal signal; A PLL means for receiving a clock output from the comparison means and locking the PLL to output a stable clock having the same frequency and phase as that of the PLL to a reproduction system; And counting means for counting a clock output from the PLL means and outputting a switching pulse to the servo system at predetermined intervals so as to control the drum speed during reproduction. 7. The apparatus of claim 6, wherein the audio signal reads a signal from an audio track on the tape. 7. The apparatus according to claim 6, wherein the reference clock applied to the comparing means is 90 KHz. The PLL circuit according to claim 6, wherein the PLL means comprises: phase comparison means for receiving a clock output from the comparison means and a clock output from the frequency division means and detecting a phase difference therebetween; Damping means for reducing the phase difference detected by said phase comparing means; A voltage control oscillating means for receiving a clock whose phase difference is reduced by the damping means, oscillating a clock having a predetermined frequency by a control voltage, and outputting the clock to a regeneration system and a frequency division means; And the frequency divider means receives the clock output from the voltage control oscillator means and divides the frequency of the clock signal by N, and outputs the frequency divider means. The apparatus according to claim 9, wherein the frequency divider divides the input clock by 64 times. The apparatus according to claim 9, wherein the clock frequency output from the voltage control oscillation means is 5.76 Mbps. 7. The apparatus according to claim 6, wherein the counting means counts the input clock so that one pulse is output every 192000 bits.