KR100208389B1 - Method and apparatus for uniformly scaling adigital image - Google Patents

Abstract

The present invention is an apparatus used to process a raw digital image with (N) consecutive original image data in order to obtain a uniformly scaled desired digital image with (M) consecutive desired image data.

If (M) is greater than (N), divide (MN) by (N-1) to produce the remainder (S), and (n) becomes (n) when (s) varies from 1 to (S) A minimum number that satisfies +1) * (S) 1 (s) * (N) is used to generate the remaining interpolation image data inserted between the (n) th and (n + 1) th original image data. Linear interpolation of the n) th and (n + 1) th original image data is performed. When (M) is smaller than (N), the address generator 37 controls the memory 2 to output the selected original image data. When the quotient generated by dividing (N) by (M) is (V), the subsequent original image data output by the memory 2 is (V) or (V +) from the immediately preceding original image data output. Offset by 1).

Description

Apparatus and method for uniformly scaling digital images

The present invention relates to an image processing apparatus and method, and more particularly, to an apparatus and method capable of two-dimensional uniform scaling of a digital image in real time.

The ability to combine digital images is very important for multimedia applications in computers. In general, digital images are preprocessed before being combined with other digital images. The preprocessing process usually increases the size of the digital image (hereinafter referred to as scaling up), reduces it (hereinafter referred to as scaling down), crops only selected portions of the digital image, or moves the selected portion of the digital image to another location. It is carried out by a method such as.

Scaling up and scaling down of digital images are usually performed by specially programmed computers. Scaling-up performs linear interpolation every two scan lines of the digital image to obtain at least one interpolated scan line inserted between the two scan lines, and also performs linear interpolation for every two pixel data of each scan line to give two pixel data. By obtaining at least one interpolated pixel data inserted in between.

Scaling down is performed by deleting part of the scan lines of the digital image, and also deleting part of the pixel data of each scan line which remains undeleted.

In scaling up digital images, linear interpolation of original image data by a computer is relatively slow. Therefore, in order to solve this problem, various dedicated hardware devices have been developed to enable real-time scaling up of digital images.

However, most dedicated hardware devices can only scale up digital images in a limited range. When scaling up a digital image with (N) scan lines, in order to insert the same number of interpolated scan lines between every two original scan lines of the original digital image to maintain uniformity, the total number of interpolated scan lines is It should be a multiple of (N-1) pieces. The same applies to scaling up a scan line having (N ') pixel data.

Currently, two-dimensional scaling of digital images to variably enlarge and reduce the image is possible by using a special graphics processor or by using a dedicated hardware device. Initially, the original image is stored in the frame memory. At this time, the original image is scaled in the first dimension, and the scaled one-dimensional image is stored in the frame memory. The scaled image is then scaled in a second dimension, and as a result the scaled two-dimensional image is stored in frame memory before being transferred to an output device such as a computer display device or a printer. Conventional scaling methods require relatively large memory and are therefore not cost effective. This is especially true if you zoom in at a large rate. In addition, conventional scaling methods require a number of processing steps, and therefore, before scaling an image in a second dimension, the scaled image in one dimension must be stored in the frame memory, and before a two-dimensional scaled image is provided to the output device. Since the two-dimensional scaled image must be stored in a frame memory, the efficiency is relatively low. Thus, conventional scaling methods are not suitable for use in live video applications.

An object of the present invention is to provide an apparatus and method for enabling two-dimensional uniform scaling of a digital image in real time.

More specifically, it is an object of the present invention to provide an inexpensive and highly efficient scaling apparatus and method that is particularly suitable for use in live video applications.

1 is a schematic circuit block diagram of a preferred embodiment of a scaling apparatus according to the present invention.

2 is a schematic circuit block diagram of a binary linear adder of a preferred embodiment.

3 is a schematic circuit block diagram of a vertical scaling controller of the preferred embodiment.

4 is a schematic circuit block diagram of the remaining disperser of the vertical scaling controller.

5 is a schematic circuit block diagram of a serial alpha generator of a vertical scaling controller.

6 is a schematic circuit block diagram of an address generator of a vertical scaling controller.

7 is a timing diagram illustrating the vertical scaling up operation of the vertical scaling unit when N = 5 and | $ N = 2.

8 is a timing diagram illustrating the vertical scaling up operation of the vertical scaling unit when N = 5 and | $ N = 6.

9 is a timing diagram illustrating a vertical scaling down operation of the vertical scaling unit when N = 5 and | $ N = 2.

Fig. 10 is a timing diagram illustrating the horizontal scaling up operation of the horizontal scaling unit in the preferred embodiment when N '= 5 and | N' = 2.

11 is a timing diagram illustrating a horizontal scaling down operation of the horizontal scaling unit when N '= 5 and | $ N' = 2.

In accordance with the present invention, an apparatus may process a raw digital image to obtain a uniformly scaled desired digital image. The device includes a frame memory for storing the original digital image. The original digital image has (N) consecutive original scan lines and (N ') continuous original pixel data per original scan line. The apparatus comprises a vertical scaling unit for scaling the original digital image in the vertical direction to obtain (M) continuous desired scan lines and (M ′) continuous desired per scan line by horizontally scaling the desired scanning line from the vertical scaling unit. The apparatus further includes a horizontal scaling unit for obtaining pixel data.

In order for the vertical scaling unit to scale the original digital image when (M) is greater than (N), the vertical scaling unit

A line memory coupled to the frame memory for storing an (n + 1) th original scan line from a frame memory;

a line buffer coupled to said line memory for storing an (n) th original scan line;

A first linear interpolator connected to the line memory and a line buffer; And

And a vertical scaling controller coupled to the frame memory, line buffer, and first linear interpolator.

The vertical scaling controller controls the storage of the original scan line into the line memory and the line buffer, and furthermore, the remainder of dividing (MN) by (N-1) is (S), which is in the range from 1 to (S) ( (n) and (n + 1) th from the line memory and linebuffer when (n) is the minimum number satisfying (n + 1) * (S) 1 (s) * (N) for s) The first linear interpolator is controlled to linearly interpolate the original scan line of to generate an excess interpolated scan line inserted therebetween.

In order for the vertical scaling unit to scale the original digital image when (M) is less than (N), the vertical scaling controller

A first address generator coupled to said frame memory for controlling said frame memory and outputting a first original scan line for storage in said line memory;

First generating means for generating a remainder (U) generated by dividing (N) by (M);

A first data register;

First adder means connected to said first generating means and said first data register to obtain a sum by adding the numbers stored in said (U) and said first data register; And

Connected to the first adder means, the first address generator and the data register, comparing the sum with (M), activating the first address generator, controlling the frame memory to store in the line memory (N) is divided by (M) and the quotient is (V), the sum is (M) by (V) when the sum is less than (M) from the previous original scanning line output by the frame memory. And first calculating means for outputting another original scanning line offset by (V + 1) when at least equal to (V + 1).

The first calculating means stores a difference in agreement with (M) in the first data register when the sum is at least equal to (M), and stores the sum in the first data register when the sum is less than (M).

In order to scale desired scan lines from the vertical scaling portion when the horizontal scaling portion M 'is greater than (N'), the horizontal scaling portion

A dot register coupled to the first linear interpolator to store (n '+ 1) th pixel data of one scan line from the first linear interpolator;

A dot buffer connected to the dot register to store (n ') th pixel data of the scan line;

A second linear interpolator connected to the dot register and the dot buffer; And

And a horizontal scaling controller coupled to the line memory, line buffer, dot buffer, and the second linear interpolator. The horizontal scaling controller controls the storage of the pixel data in the dot register and the dot buffer, and furthermore, the remainder obtained by dividing (M'-N ') by (N'-1) is (S'), from 1 to (S '). The dot register and dot when (n ') is the minimum number satisfying (n' + 1) * (S ') 1 (s') * (N ') for (s') in the range up to Redundant interpolated pixel data inserted between the (n ') and (n' + 1) th pixel data by performing linear interpolation of the (n ') th and (n' + 1) th pixel data from the buffer The second linear interpolator is controlled to generate a.

In order for the horizontal scaling portion to scale the desired scan line from the vertical scaling portion when (M ') is smaller than (N'), the horizontal scaling controller

A second address generator connected to the line memory and configured to control the line memory to output first original pixel data of one original scan line;

Second generating means for generating a remainder (U ') generated by dividing (N') by (M ');

A second data register;

Second adder means connected to said second generating means and said second data register to obtain a sum by adding the number stored in said U 'and said second data register; And

Connected to the second adder means, the second address generator and the second data register, compare the sum with M ', activate the second address generator to control the line memory, and (N When ') is divided by (M') and the quotient is (V '), when the sum is less than (M') from the previous original pixel data output by the line memory, the sum is (M '). And second calculating means for outputting another original pixel data of the one original scanning line, offset by (V '+ 1) when at least equal to'). The second calculating means stores a difference in agreement with (M ') in a second data register when the sum is at least equal to (M'), and stores the sum in the second data register when the sum is less than (M '). Save it.

The output of the second linear interpolator of the horizontal scaling unit may be directly provided to the output device.

According to one aspect of the invention, the original digital image has (N) consecutive original image data, the desired digital image has (M) consecutive desired image data, and (M) is greater than (N) When large, the method of processing the original digital image to obtain a uniformly scaled desired digital image is

Providing a linear interpolator; And

Dividing (MN) by (N-1), the remainder is called (S), and when (s) varies from 1 to (S), (n) is (n + 1) * (S) 1 (s If the minimum number satisfies) * (N), linear interpolation of the (n) th and (n + 1) th image data of the original image data is performed, and the (n) th and (n + 1) th original image data is performed. Controlling a linear interpolator to generate redundant interpolation image data interposed therebetween.

According to another aspect of the invention, the original digital image has (N) consecutive original image data, the desired digital image has (M) consecutive desired image data, and (M) is greater than (N) When small, the method of processing the original digital image to obtain a uniformly scaled desired digital image

(I-1) storing original image data in a memory unit;

(I-2) providing an address generator for controlling the memory unit to output the first data of the original image data;

(I-3) storing the remainder (U) by dividing (N) by (M) in a data register;

(I-4) adding up (U) and the number stored in the data register to obtain a sum;

(I-5) comparing the sum with (M);

(I-6) When (N) is divided by (M) and the quotient is (V), when the sum is less than (M) from the original image data output by the memory section immediately before controlling the memory section, Activating the address generator to output another image data subtracted by (V + 1) when the sum is at least equal to (M);

(I-7) storing the difference generated in the data register by subtracting (M) from the sum when the sum is at least equal to (M), and storing the sum in the data register when the sum is less than (M); And

(I-8) Steps (I-4) to (I-7) are repeated until (M) original image data is outputted by the memory unit.

According to another aspect of the invention, the original digital image has (N) consecutive original image data, the desired digital image has (M) consecutive desired image data, and (M) (N) When larger, the apparatus for processing the original digital image to obtain a uniformly scaled desired digital image

Linear interpolator; And

Dividing (MN) by (N-1), the remainder is called (S), and when (s) varies from 1 to (S), (n) is (n + 1) * (S) 1 (s If the minimum number satisfies) * (N), the linear interpolator is controlled to perform linear interpolation of the (n) th and (n + 1) th image data of the original image data, and the (n) th and (n + 1) Control means connected to a linear interpolator for generating redundant interpolation image data inserted between the < RTI ID = 0.0 > th < / RTI > original image data.

According to another aspect of the invention, the original digital image has (N) consecutive original image data, the desired digital image has (M) consecutive desired image data, and (M) (N) When smaller, the apparatus for processing the original digital image to obtain a uniformly scaled desired digital image

A memory unit for storing original image data;

An address generator connected to the memory unit for controlling a memory unit to output first data of original image data;

Generating means for generating a remainder (U) generated by dividing (M) by (N);

Data registers;

An adder means connected to the generating means and the data register to add a sum of the numbers stored in the data register and (U); And

Connected to the adder means and the address generator and the data register, comparing the sum with (M), dividing (N) by (M), and controlling the memory portion when the quotient is (V). Activate the address generator to output another image data subtracted by (V) when the sum is less than (M) and (V + 1) when the sum is at least equal to (M) from the original image data output by the Calculation means for causing; When the sum is at least equal to (M), the difference between the value of (M) and the sum of the data register is stored, and when the sum is less than (M), the calculation means stores the sum in the data register.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, and features and advantages of the present invention will be described.

As shown in FIG. 1, a preferred embodiment of the apparatus for uniformly scaling a digital image according to the present invention includes a vertical scaling unit and a horizontal scaling unit. The vertical scaling unit may scale up or scale down the digital image in the vertical direction and includes a line memory 3, a line buffer 4, a binary linear adder 5, and a vertical scaling controller 6. The horizontal scaling unit may scale up or scale down the digital image in the horizontal direction, and includes a dot resist 7, a dot buffer 8, a binary linear adder 9, and a horizontal scaling controller 10.

In actual use, the digital image processed through the preferred embodiment of the apparatus is first stored in the frame memory 2. Digital video comes from a video decoder or video capture system. The vertical scaling controller 6 controls the frame memory 2 to supply the selected scan lines of the digital image to the line memory 3. The vertical scaling controller 6 also controls the line buffer 4 to store the previous scan line output from the line memory 3 in the line buffer 4. The binary linear adder 5 receives the scan line data from the line memory 3 and the line buffer 4 and performs binary interpolation from the vertical scaling controller 6 according to a pair of weighting factors | A and 1- | A.

The output of the binary linear adder 5 is input to the do register 7. The horizontal scaling controller 10 controls the dope buffer 8 to store previous pixel data from the do register 7 into the dot buffer 8. The binary linear adder 9 receives pixel data from the dosistor 7 and the dot buffer 8, and performs binary linear interpolation from the horizontal scaling controller 10 according to a pair of weighting factors | A and 1- | A. do.

2 is a schematic block diagram of the circuit of the binary linear adder 5. As shown in Fig. 2, the scan line data output from the line buffer 4 corresponding to the (n) th scan line of the digital image in the frame memory 2 is multiplied by the coefficient 1- | A. On the other hand, the scan line data output from the line memory 3 corresponding to the (n + 1) th scan line of the digital image in the frame memory 2 is multiplied by the coefficient | A. Therefore, the result is added to obtain the interpolated scan line when the coefficient | A is a non-integer fraction of 0 or 1. The operation of the binary linear adder 5 is described in more detail below.

The structure of the binary linear adder 9 is similar to that of the binary linear adder 5 shown in FIG. However, in the binary linear adder 9, the pixel data output from the binary linear adder 5 from the dot buffer 8 corresponding to the (n ') th pixel data of the scan line data) is multiplied by a coefficient 1- | A. On the other hand, the pixel data output from the dopistor 7, which corresponds to the (n '+ 1) th pixel data of the scan line data from the binary linear adder 5, is multiplied by the coefficient | A. Thus, the dosistor 7 serves as the line memory 3 of the vertical scaling unit, while the dot buffer 8 serves as the line buffer 4 of the vertical scaling unit.

As shown in FIG. 3, the vertical scaling controller 6 includes a programmable register set 30 consisting of a first register 30a, a second register 30b, and a third register 30c. The first register 30a is for storing (N) original scan lines of the digital image of the frame memory 2, and the second register 30b is for storing (| $ N) scan lines that are interpolated or deleted. The third register 30c is a register for storing an INC / DEC flag 38 indicating whether the digital image is performed with scaling up or scaling down in the vertical direction. In addition, the vertical scaling controller 6 includes first, second and third calculation circuits 31, 32 and 33 for reading the contents of the first, second and third registers 30a, 30b and 30c. . The first calculation circuit 31 outputs the quotient T generated by dividing (| $ N) by (N-1). On the other hand, the second calculation circuit 32 outputs the remaining S generated by dividing (| $ N) by (N-1). The quotient T corresponds to the minimum value of the interpolated scan line inserted between every two original scan lines of the digital image stored in the frame memory 2, while the remaining S is stored in the frame memory 2 when the digital image is scaled up. It corresponds to the total number of redundant interpolation scan lines uniformly distributed among the original scan lines of the stored digital image. The third calculating circuit 33 outputs the remaining U generated when dividing (N) by (N- | $ N). The remaining U corresponds to the total number of remaining scan lines that are deleted from the digital image stored in the frame memory 2 when scaling down the digital image.

The two input signal selectors 34 receive the remaining U output from the third calculating circuit 33 as the first input signal, and receive the remaining S output from the second calculating circuit as the second input signal. In addition, the selector 34 receives the INC / DEC flag 38 from the third register 30c as a control input signal, and the output signal 42 of the selector 34 is input to the remaining spreaders 35. The remaining disperser 35 receives the quotient T output from the first calculation circuit 31 as an input and receives the INC / DEC flag 38 output from the third register 30c as an input control signal and receives a serial alpha generator ( 36 and an output control signal 39 to the address generator 37. The remaining disperser 35 also determines the point at which the redundant interpolation step is performed during scaling up of the digital image and the point at which the residual scan line is deleted during scaling down. The serial alpha generator 36 receives the quotient T from the first calculating means 31 and the INC / DEC flag 38 from the third register 30c as inputs for the coefficient | A and 1- for the binary linear adder 5. Generates A and outputs a store command signal for the line buffer 4 (see FIG. 1). The address generator 37 also passes from the first calculation means 31 to the quotient T and the third register 30c. The line address data is supplied to the frame memory 2 from the INC / DEC flag 38 as an input signal.

As shown in FIG. 4, the remaining disperser 35 uses the calculation circuit 40 for outputting the difference between (N) and (| $ N) and the output signal of the calculation circuit 40 as the first input signal. It includes two input signal selectors 41 using the number N of the first register 30a as a second input signal and the INC / DEC flag 38 of the third register 30c as a control input signal. The intermediate data register 56 receives the output 42 of the selector 34 (see FIG. 3) and has an output connected to one of the two inputs of the two-input adder 43. The other input of the adder 43 receives the output 42 of the selector 34. The output of the adder 43 and the output of the selector 41 are used as inputs to the calculation circuit 44, which calculates the latter from the former and the output 43 of the adder is the output 41 of the selector. Generate an enable signal at the control output when greater than or equal to. The two input selectors 45 have a first input receiving the output of the adder 43, a second input receiving the difference between the output of the adder 43 and the output of the selector 41 from the calculating circuit 44, It has a control input connected to the control output 39 of 44 and an output connected to the intermediate data register 56.

The clock correction circuit 46 receives the original input line clock, and corrects the original input line clock according to the signal from the control output 39 and the quotient T output from the first calculation circuit 31. The raw input line clock may also be a display scan line clock so that vertical scaling operations occur while the raw image data is output for display on an output device such as a printer or computer display. When the control output 39 is logically in a high state, the clock correction circuit 46 outputs a (T + 2) divided clock having a length (T + 2) times the original input line clock. When the control output 39 is logically in a low state, the clock correction circuit 46 outputs a (T + 1) divided clock having a length (T + 1) times the original input line clock. The output of the clock correction circuit 46 and the original input line clock are used as control inputs of the selector 47. The INC / DEC flag 38 output from the third register 30c is provided to the control input of the selector 47. The intermediate data register 56 has a load terminal LD that receives the clock signal mClock1 from the selector 47.

As shown in FIG. 5, the alpha series generator 36 is connected to the control output 39 of the calculation circuit 44 and receives a quotient T from the original input line clock and the first calculation circuit 31. 363). When control output 39 is logically in a high state, coefficient generator 363 is delimited by 1, 1 / (T + 2), 2 / (T + 2), ... generate the (T + 1) / (T + 2) alpha coefficients, and when the control output 39 is in the logical state, the coefficient generator 363 is each in successive (T + 1) line clock periods. Generate successive 1, 1 / (T + 1), 2 / (T + 1), ... (T) / (T + 1) alpha coefficients. The selector 364 has a first input fixed at 1, a second input receiving the output of the coefficient generator, and a control input receiving the INC / DEC flag 38. The output of the selector 364 is the coefficient | A, which is used as one of the inputs of the subtraction circuit 365. The other input of the subtraction circuit 365 is fixed at one. One of the outputs of the subtraction circuit 365 is coefficient 1- | A, and the other output is a store command signal used as an input of the line buffer 4 as shown in FIG. The subtraction circuit 365 generates a storage command signal when the coefficient 1- | A is zero, that is, | A = 1.

As shown in Fig. 6, the address generator 37 includes a calculation circuit 371 that outputs a quotient V generated when (N) is divided by (N- | $ N). The quotient V corresponds to the offset number between two selected scan lines of the digital image in the frame memory 2 when the digital image is scaled down. The quotient V and control output 39 are used as inputs to the adder 372. The output of adder 372 is used as one of the inputs of selector 373. The other input of the selector 373 is fixed at one. The INC / DEC flag 38 is used as a control input of the selector 373. The selector 373 generates an offset number provided to the adder 374. The output of adder 374 is coupled to address register 375. The output of the address register 375 is line address data and enters an input to the adder 374. The address register 375 has an input signal start, which presets the first line address of the original scan lines in the frame memory 2. The address register 375 also has a load terminal LD that controls the next address therein.

The latch circuit 376 samples and holds at the control output 39 in accordance with the original input line clock. The clock correction circuit 377 receives the original input line clock and modifies the original input line clock according to the output of the latch circuit 376 and the quotient T of the first calculation circuit 31. When the output of the latch circuit 376 is in a logic high state, the clock correction circuit 377 outputs a (T + 2) division clock having a length (T + 2) times the original input line clock. When the output of the latch circuit 376 is in the logical state, the clock correction circuit 377 outputs a (T + 1) divided clock having a length (T + 1) times the original input line clock. The selector 378 receives the input of the original input line clock and the output of the clock correction circuit 377 as inputs, and is controlled by the INC / DEC flag to output the clock input mClock2 used as the input terminal LD of the address register 375. .

The structure of the horizontal scaling controller 10 is substantially similar to that of the horizontal scaling controller 6 shown in FIGS. 3 to 6. There is only a small difference between the two controllers 6, 10. For example, in the horizontal scaling controller 10, the first register of the programmable register set is used to store the number N 'of pixel data per original scan line of the digital image in the frame memory 2, and the second register. The register is used to store the number of pixel data (| $ N ') that is interpolated or deleted per scan line. The third register stores an INC / DEC flag indicating whether scaling up or scaling down of the digital image is performed in the horizontal direction. The first calculation circuit generates a quotient T 'corresponding to the minimum number of interpolated pixel data to be inserted between every pixel data of scan line data coming out of the binary linear adder 5. The second calculation circuit generates the remaining S 'corresponding to the total number of redundant interpolated pixel data uniformly distributed among the pixel data of the scan line data from the binary linear adder 5 when the digital image is scaled up. The third calculation circuit generates the remaining U 'corresponding to the total number of redundant pixel data deleted from the scan line data from the binary linear adder 5 when the digital image is scaled down. Instead of the store command signal, the alpha series generator of the horizontal scaling controller 10 generates a latch command signal for the dot buffer 8. The clock inputs for the address generator, alpha series generator, and the remainder spreader are the one pixel clock. The one pixel clock may also be a display dot clock so that horizontal scaling operations occur while the raw image data is output for display on an output device such as a printer or computer display. The address output of the address register of the horizontal scaling controller 10 is a dot address used to control the line memory 3 and the line buffer 4. Thus, while scaling up in the horizontal direction, if there is any pixel data of the (n) th and (n + 1) th scan lines, and if there are interpolated scanlines between the (n) th and (n + 1) th scan lines, All pixel data of the interpolated scan lines pass through the binary linear adder 5. When scaling down in both the vertical and horizontal directions, only the selected pixel data of the selected scanning line of the circumferential line passes through the binary linear adder 5.

Therefore, the preferred embodiment operates to simultaneously perform scaling up or scaling down in the vertical direction, scaling up or scaling down in the horizontal direction. The operation of the preferred embodiment will be described below.

A. To facilitate the description of the vertical scaling up operation of the preferred embodiment, a raw digital image with five original scan lines and five pixel data per scan line may produce a desired digital image with seven desired scan lines and five pixel data per scan line. Let's take an example of scaling up to get.

As shown in FIG. 3, the programmable register set 30 of the vertical scaling controller 6 has a number '5' for the first register 30a, a number '2' for the second register 30b, and a third register. It is initially programmed by storing logic '1' in 30c. The number '5' corresponds to the number N of the circumferential lines of the one digital image in the frame memory 2. The number '2' corresponds to the total number of interpolated scan lines (| $ N). A logic '1' of the third register 30c indicates that scaling up of the original digital image is performed in the vertical direction. At this time, the programmable register set of the horizontal scaling controller 10 has five pixel data on each original scan line, no interpolated pixel data on the original scan line, and scaling up of the original digital image in the horizontal direction will be carried out. It is programmed to turn on.

The first calculation circuit 31 outputs a quotient T generated by dividing (| $ N) by (N-1). The quotient T is zero because (| $ N) is less than (N-1). The second calculation circuit 32 outputs the remaining S generated by dividing (| $ N) by (N-1). In the case of the above example, the remaining S is two. The output of the third calculation circuit 33 is inappropriate because the selector 34 provides the output of the second calculation circuit 32 to the remaining disperser 35 during the scale up operation. The first, second and third calculation circuits of the horizontal scaling controller 10 are zero because no horizontal scaling up or scaling down operation is performed.

As shown in Figs. 1 and 3 to 7, the address register 375 of the address generator 37 sets the line address of the first scan line among the circumferential scan lines initially stored in the frame memory 2, and the frame memory ( 2), the first scan line of the original scan lines is supplied to the line memory 3 during the start line clock. At the same time, the remaining S is stored in the intermediate data register 56, at which time the adder 43 adds the contents of the remaining S and the intermediate data register 56. At this time, since the output of the adder 43 having a value of '4' is smaller than (N) having a value of '5', the control output 39 of the calculation circuit 44 is in a logic low state. do. The selector 45 supplies the output of the adder 43 to the intermediate data register 56, and the clock input mClock1 supplied to the intermediate data register 56 is a (T + 1) division clock because the quotient T is zero. Same as the original input line clock.

Since the control output 39 is logically in the low state, and the quotient T is zero, the coefficient generator 363 supplies the selector 364 with the number '1'. Since the INC / DEC flag 38 is logically '1', the selector 364 selects the output of the coefficient generator 363 as the weighting factor | A. Since the coefficient | A is 1, the coefficient 1- | A is 0, and the storage command signal is used to control the line buffer 4 to store the first scan line of the circular scan line from the line memory 3 to the line buffer 4 Is generated. In this step, the output of the binary linear adder 5 is the first scan line of the circular scan line.

The selector 373 supplies an offset number to the adder 374 and the offset number is one. Therefore, the adder 374 increases the output of the address register 375 by one unit when the next clock pulse mClock2 arrives, and then controls the frame memory 2 to supply the second scan line of the circular scan line to the line memory 3.

When the next clock pulse mClock1 arrives, the intermediate data register 56 stores the previous output of the adder 43 of the number '4'. At this time, since the output of the adder 43 having a value of '6' is larger than the number N having a value of '5', the control output 39 of the calculation circuit 44 is in a logic high state. .

The selector 45 supplies the difference between the output of the adder 43 and the selector 41 to the intermediate data register 56, and the clock input mClock1 to the intermediate data register 56 is now twice the original input line clock. It becomes a (T + 2) division clock having a length.

Since control output 39 is logically high, coefficient generator 363 generates two outputs 1 and 1/2 in succession within one mClock1 pulse, i.e., two consecutive original input line clocks. do. Within the first circle input line clock, the binary linear adder 5 outputs the second scan line of the circular scan lines, and at the same time the latter is stored in the line buffer 4 because the coefficient | A is one. Within the second one input line clock, the contents of the address register 375 are incremented by one by receiving the next mClock2 pulse, controlling the frame memory 2 to supply the third of the circle scan lines to the line memory 3. At this time, the output of the coefficient generator 363 is 1/2, and since the coefficient | A is 1/2, the coefficient 1- | A is 1/2. And no save command signal is generated. Thus, the second of the circumferential lines remains in the line buffer 4. At this stage, the output of the binary adder 5 is the binary interpolation of the second and third ones of the circular scan line.

The contents of the intermediate data register 56 are updated to '1' which is the difference between the output of the adder 43 and the number N when the next mClock1 pulse arrives. Since the output of the adder 43 is 3 smaller than the number N, the control output 39 is in a logical low state. The selector 45 supplies the output of the adder 43 to the intermediate data register 56, the clock input mClock1 supplied to the intermediate data register 56 is a (T + 1) division clock, and the serial alpha generator 36 The coefficient | A outputted from) is 1. The output of the binary adder 5 is the third of the circular scan line. And since the coefficient | A is 1, the third one of the circular scanning lines is stored in the line buffer 4.

The subsequent operation of the vertical scaling portion is similar to the previous one until the fifth of the circumferential line is output from the binary linear adder 5.

Fig. 7 is a timing diagram illustrating the scaling up operation of the preferred embodiment when, for example, N = 5 and | $ N = 2.

Dividing (| $ N) by (N-1), the remainder is called (S), and (n) is (n + 1) * (S) 1 when (s) varies from 1 to (S) If the minimum number satisfies (s) * (N), the vertical scaling controller 6 controls the binary linear adder 5, which is the (n) th and the line memory of the original scanning line stored in the line buffer 4; The binary interpolation of the (n + 1) th of the original scan lines stored in (3) is performed to generate a redundant interpolation scan line inserted between the (n) th and (n + 1) th original image data.

Referring back to FIG. 1, since the horizontal scaling operation is not performed, the horizontal scaling controller 10 controls the line memory 3 and the line buffer 4 to sequentially process the pixel data stored in the pixel buffer 4 in the binary line. It is provided to the mold adder 5. The original pixel data and the interpolated pixel data from the binary linear adder 5 are passed to the doresistor 7 to the binary linear adder 9, which in turn is passed to the binary linear adder 9. At the same time, the coefficient | A is always equal to 1, and the output of the dot buffer 8 is ignored by the binary linear adder 9. The output of the binary linear adder 9 is the same as the output of the binary linear adder 5, and may be provided directly to an output device (not shown).

In the above example, the quotient (T) that occurs when dividing (| $ N) by (N-1) is zero. If the quotient T is not zero, i.e. (| $ N) is greater than or equal to (N-1), the vertical scaling controller 6 controls the binary linear adder 5 to Binary interpolation is performed on the (n) th and (n + 1) th of the circumferential line to generate additional T consecutive interpolated scanlines inserted between the (n + 1) th scan lines. 8 shows a timing diagram of a sample scaling up operation performed by the preferred embodiment when N = 5 and | $ N = 6. In this example, the quotient T is 1 and the remainder S is 2. Clearly, there is an additional interpolated scanline inserted between every interval of the (n) th and (n + 1) th of the circumferential line.

B. In the following example, a raw digital image with five original scan lines and five pixel data per scan line is scaled down to obtain a desired digital image with three desired scan lines and five pixel data per scan line.

Referring again to FIG. 3, the programmable register set 30 has a number '5' for the first register 30a, a number '2' for the second register 30b, and a logic '0' for the third register 30c. It is programmed initially by storing '. The number '5' corresponds to the number N of the circumferential lines of the one digital image in the frame memory 2. The number '2' corresponds to the total number of scan lines (| $ N) to be deleted. Logic '0' of the third register 30c indicates that scaling down of the original digital image is performed. At this time, the programmable register set of the horizontal scaling controller 10 has five pixel data in each of the original scan lines, no interpolated pixel data for each of the original scan lines, and scaling up of the original digital image in the horizontal direction is performed. It is programmed to indicate that it should.

The outputs of the first and second calculation circuits 31 and 32 are inappropriate during the scale down operation. The third calculation circuit 33 outputs the remaining U generated when dividing (N) by (N- | $ N), where (N- | $ N) is the number of retained circular lines. In the above example, the remaining U is two. The selector 34 supplies the output of the third calculating circuit 33 to the remaining dispersers 35.

1, 3-6, and 9, the address register 375 of the address generator 37 sets the line address of the first one of the circumferential lines stored in the frame memory 2 initially. The frame memory 2 is controlled to supply the first of the circumferential lines to the line memory 3 during the start line clock. At the same time, the remaining U is stored in the intermediate data register 56, at which time the adder 43 adds the contents of the remaining U and the intermediate data register 56. The calculation circuit 44 subtracts (N- | $ N) of the selector from the output of the adder 43. At this time, the output of the adder 43 having a value of 4 is larger than (N- | $ N) having a value of 3, and the control output 39 of the calculation circuit 44 is in a logic high state. The selector 45 supplies the intermediate data register 56 with the difference between the output of the adder 43 and the output of the selector 41. The one-line clock is supplied to the intermediate data register 56 via the selector 47.

3 and 5, the selector 364 maintains the coefficient | A at 1 since the logic '0' is stored in the third register 30c. Therefore, the coefficient 1- | A becomes 0, and a storage command signal is always generated to activate the line buffer 4 and continuously store the circumferential lines of the line memory 3 in the line buffer 4. In addition, the output of the binary adder 5 always becomes the output of the line memory 3.

Referring to Fig. 6, the calculation circuit 371 outputs the quotient V generated by dividing (N) by (N- | $ N). In this example, the quotient V is one. The adder 372 generates the sum of the quotient V and the logic state of the control output 39 which is currently high. The selector 373 selects the output of the adder 372 having a value of 2 to supply the same value to the adder 374. Therefore, when the next mClock2 pulse is reached, the output of the address register 375 is increased by two units, thereby controlling the frame memory 2 to supply the third of the circumferential lines to the line memory 3.

Referring again to FIG. 4, when the next line clock pulse arrives, the intermediate data register 56 stores the number '1', which is the previous difference calculated by the computation circuit 44. At this time, the output of the adder 43 having the value 3 is the same as the output of the selector 41. The control output 39 of the calculation circuit 44 is in a logical high state, and the selector 45 supplies the intermediate data register 56 with the difference between the output of the adder 43 and the output of the selector 41.

Referring back to FIG. 6, the adder 372 generates the sum of the quotient V and the current logical state of the control output 39 once more. The output of adder 372 having a value of 2 is supplied to adder 374 via selector 373. Therefore, when the next mClock2 pulse arrives, the output of the address register 375 is again increased by two units, thereby controlling the frame memory 2 to supply the fifth of the circumferential lines to the line memory 3. Fig. 9 is a timing diagram illustrating the vertical scaling down operation of the preferred embodiment when N = 5 and | $ N = 2 in the above example. The horizontal scaling unit for this example is similar to that described above, and the description thereof will not be repeated herein.

From the foregoing, it is shown that the address generator 37 of the vertical scaling controller 6 controls the frame memory 2 to output only selected ones of the circumferential lines. Circular scanning lines not output by the frame memory 2 are virtually ignored. The circumferential line output by the frame memory 2 is equal to the number V when the output of the adder 43 of the remaining disperser 35 is smaller than the difference N- | $ N, and the output of the adder 43 is different ( It should be noted that when at least equal to N- | $ N), the number (V + 1) is offset from the immediately preceding circumferential line output by the frame memory 2.

A raw digital image having five original scan lines and five pixel data per scan line is scaled up to provide a desired digital image with five desired scan lines and seven pixel data per scan line, for example, the horizontal scaling of the above embodiment. The up operation will be described.

The programmable register set 30 of the vertical scaling controller 6 initially has five circular scan lines in the frame memory 2, no scan lines should be interpolated, and scaling up of the original digital image in the vertical direction is not performed. It is programmed to indicate that it should not be. The programmable register set of horizontal scaling controller 10 is then programmed by storing the number 5 in the first register, the number 2 in the second register, and the logic 1 in the third register. The number 5 corresponds to the number N 'of pixel data of each of the original scan lines in the frame memory 2. The number 2 corresponds to the total number (| $ N ') of pixel data to be interpolated per scan line. Logic 1 stored in the third register indicates that scaling up of the original digital image should be performed in the horizontal direction.

The outputs of the first, second and third calculating means 31, 32, 33 of the vertical scaling controller 6 are zero since no vertical scaling up or scaling down operation is performed. The first calculation circuit of the horizontal scaling controller 10 outputs the quotient T 'generated by dividing (| $ N') by (N'-1). Since (| $ N ') is less than (N'-1), the quotient T' is zero. The second calculation circuit of the horizontal scaling controller 10 outputs the remaining S 'generated by dividing (| $ N') by (N'-1). In this example, the remaining S 'is equal to two. The output of the third calculating circuit of the horizontal scaling controller 10 is inappropriate because the output of the second calculating circuit is provided to the remaining disperser during the horizontal scale up operation.

Since the vertical scaling operation should be performed, the vertical scaling controller 6 controls the frame memory 2 to sequentially provide the original scan line to the line memory 3. The horizontal scaling controller 10 controls the line memory 3 and the line buffer 4 to sequentially provide the pixel data stored in the line memory 3 and the line buffer 4 to the binary linear adder 5. At this time, the coefficient | A from the vertical scaling controller 6 is always equal to 1, and the output of the line buffer 4 is ignored by the binary linear adder 5. The output of the binary linear adder 5 is the same as the output of the line memory 3.

As described above, the scaling up operation of the horizontal scaling unit is substantially similar to that of the vertical scaling unit. However, unlike the vertical scaling controller 6, the horizontal scaling controller 10 controls the binary linear adder 9 to store the (n ′) th pixel data and the dosistor 7 stored in the dot buffer 8. By performing binary linear interpolation of the (n '+ 1) th pixel data stored in, divide (| $ N') by (N'-1) and call the rest (S ') (N ') is the smallest number that satisfies (n' + 1) * (S ') 1 (s') * (N ') when varying from 1 to (S'). Generates redundant interpolation pixel data inserted between the nth and (n '+ 1) th original pixel data. Therefore, when (N '), (| $ N'), and (S ') are 5, 2, and 2, respectively, the interpolated pixel data is divided between the second one-pixel data and the third one-pixel data of the scan line. It is inserted between the four-one pixel data and the fifth one-pixel data.

The horizontal scaling controller 10 initially sets the dot address of the first pixel data of the scan line data stored in the line memory 3 and is received by the dot register 7 during the starting pixel clock. The line memory 3 is controlled to provide the first pixel data to the binary linear adder 5. The coefficient | A from the horizontal scaling controller 10 is equal to 1, and the latch command is used to control the dot buffer 8 to store the first one-pixel data from the dot register 7 in the dot buffer 8. The signal is generated. In this stage, the output of the binary linear adder 9 is the first one pixel data, which may be directly provided to an output device (not shown). At this time, the horizontal scaling controller 10 Control is provided to the binary linear adder 5 for the second one pixel data for reception into the dot register 7. Horizontal scaling controller 10 generates two | A coefficients, 1 and 1/2, in succession within two consecutive one-pixel clocks. Within the first one pixel clock, the binary linear adder 9 outputs the second one pixel data, and at the same time the latter is stored in the dot buffer 8 since the coefficient | A is one. Within the second pixel one pixel clock, the line memory 3 provides the third one pixel data to the binary linear adder 5 for reception into the do register 7. The coefficient | A is now 1/2, and the second one pixel data remains in the dot buffer 8. In this stage, the output of the binary linear adder 9 is binary linear interpolation of the second and third one pixel data.

During the next one pixel clock, the coefficient | A from the horizontal scaling controller 10 again becomes 1, and the output of the binary linear adder 9 is the third one pixel data stored simultaneously in the dot buffer 8.

The subsequent operation of the horizontal scaling portion is similar to that described above until the fifth one-pixel data of one scan line is output by the binary linear adder 9.

Fig. 10 is a timing diagram illustrating the horizontal scaling up operation when the above preferred embodiment, i.e., N '= 5 and | $ N' = 2.

In this example, the quotient (T ') resulting from dividing (| $ N) by (N'-1) is zero. If the quotient T 'is not zero, i.e. (| $ N') is greater than or equal to (N'-1), then the horizontal scaling controller 10 has the (n ') th and (n' + 1) th one pixels. The binary linear adder 9 is controlled to generate an additional number T 'of consecutive interpolated pixel data interleaved between the data, so that the (n') and (n '+ 1) Perform binary linear interpolation.

D. In the following example, the original digital image with five circular scan lines and five pixel data per scan line is scaled down to obtain a desired digital image with five desired scan lines and three pixel data per scan line.

The programmable register set 30 of the vertical scaling controller 6 initially has five circular scan lines in the frame memory 2, no scan lines should be interpolated, and scaling up of the original digital image in the vertical direction is not performed. It is programmed to indicate that it should not be. The programmable register set of horizontal scaling controller 10 is then programmed by storing the number 5 in the first register, the number 2 in the second register, and the logic 0 in the third register. The number 5 corresponds to the number N 'of pixel data per original scan line of the digital image in the frame memory 2. The number 2 corresponds to the total number (| $ N ') of pixel data to be deleted per scan line. Logic 0 stored in the third register indicates that scaling down of the original digital image should be performed in the horizontal direction.

The outputs of the first, second and third calculating means 31, 32, 33 of the vertical scaling controller 6 are zero since no vertical scaling up or scaling down operation is performed. Accordingly, the vertical scaling controller 6 controls the frame memory 2 to sequentially provide the circumferential line to the line memory 3. The horizontal scaling controller 10 controls the line memory 3 and the line buffer 5 to provide the binary linear adder 5 with the selected pixel data stored in the line memory 5 and the line buffer 5. . For this example, the coefficient | A from the vertical scaling controller 6 is always equal to one, and the output of the line buffer 4 is ignored by the binary linear adder 5. The output of the binary linear adder 5 is the same as the output of the line memory 3.

The scaling down operation of the horizontal scaling portion is substantially similar to that of the vertical scaling portion. However, in the horizontal scaling unit, the horizontal scaling controller 10 controls the line memory 3 and the line buffer 4 to output only the selected one pixel data. The one pixel data output by the line memory 3 and the line buffer 4 is output by the latter when the adder output of the remaining disperser of the horizontal scaling controller 10 is smaller than (N'- | $ N '). It is offset by V 'which is the quotient of dividing (N') by (N'- | $ N ') from the previous one-pixel data, otherwise it is offset by (V' + 1).

The output of the first and second calculation circuits of the horizontal scaling controller 10 is inappropriate during the horizontal scale down operation. The third summation circuit outputs the remaining U 'that occurs when (N') is divided by the number of one-pixel data (N'- | $ N ') held per scan line. In this example, the remaining U 'is equal to two and provided to the remaining disperser of the horizontal scaling controller 10.

The horizontal scaling controller 10 sets the dot address of the first pixel data of the scan line data stored in the line memory 3 initially, and controls the line memory 3 to control the first during the starting pixel clock. The second pixel data is supplied to the binary linear adder 5. Since logic 0 is stored in the third register of the horizontal scaling controller 10, the coefficient | A of the horizontal scaling controller 10 is maintained at one. Thus, the dot buffer 8 continues to be activated for storing pixel data from the dosistor 7, and the output of the binary linear adder 9 is always the output of the dosistor 7. As shown in FIG.

When the next pixel clock pulse arrives, the adder output of the remaining disperser of horizontal scaling controller 10 is the difference (N'- | $ N '), thereby generating an offset (V'-2) or two. The horizontal scaling controller 10 controls the line memory 3 and the line buffer 4 to transfer the fifth pixel data of the scanning lines stored in the line memory 3 and the line buffer 4 to the do register 7. It is supplied to the binary linear adder 5 for reception.

FIG. 11 is a timing diagram illustrating the horizontal scaling down operation of the preferred embodiment for this example, N '= 5 and | $ N' = 2.

The device of the present invention is a dedicated hardware device that allows real-time two-dimensional scaling of digital images. In addition, the device of the present invention is relatively inexpensive, has fewer processing steps, and can achieve higher efficiency from the viewpoint of requiring a relatively small memory regardless of the scaling ratio. This is because the output of the vertical scaling unit is directly supplied to the horizontal scaling unit without having to store the same data in the intermediate frame buffer, and the output of the horizontal scaling unit can be directly supplied to the output device without the need to store the output in the output frame buffer. . Thus, the present invention is ideal for use in live video applications.

Claims (16)

A frame memory 2 for storing original digital images having (N) consecutive original scanning lines and (N ') continuous original pixel data per said original scanning line, wherein (M) is larger than (N) ( When M ') is larger than (N'), the vertical scaling unit for vertically scaling the original digital image to obtain (M) consecutive desired scan lines and (M ') continuous desired pixel data per scan line are obtained. An apparatus for processing an original digital image for obtaining a uniformly scaled desired digital image, further comprising a horizontal scaling unit for horizontally scaling a desired scanning line from the vertical scaling unit. Vertical scaling unit; And It characterized in that it comprises a horizontal scaling, The vertical scaling part A line memory (3) connected to said frame memory (2) for storing an (n + 1) th circular scan line from a frame memory (2); a line buffer 4 connected to the line memory 3 storing the (n) th circular scan line; A first linear interpolator 5 connected to the line memory 3 and the line buffer 4; And It is connected to the frame memory 2, the line buffer 4 and the first linear interpolator 5, and controls the storage of the original scan line in the line memory 3 and the line buffer 4, furthermore ( The remainder of MN) divided by (N-1) is (S), and for (s) in the range from 1 to (S), (n) is (n + 1) * (S) 1 (s) * When the minimum number satisfies (N), the linear interpolation of the (n) th and (n + 1) th original scan lines from the line memory 3 and the line buffer 4 is performed, and the interpolated scan lines inserted therebetween are inserted. A vertical scaling controller 6 for controlling the first linear interpolator 5 to produce The horizontal scaling unit A do register (7) connected to said first linear interpolator (5) for storing (n '+ 1) th pixel data of one scan line from said first linear interpolator (5); A dot buffer 8 connected to the dot register 7 to store (n ') th pixel data of the scan line; A second linear interpolator (9) connected to the dosistor (7) and the dot buffer (8); And Connected to the line memory 3, the line buffer 4, the dot buffer 8, and the second linear interpolator 9, and the pixel data is stored in the do register 7 and the dot buffer 8. In addition, the remainder of (M'-N ') divided by (N'-1) is (S') and (n ') for (s') in the range from 1 to (S'). When (n '+ 1) * (S') 1 is the minimum number satisfying (s ') * (N'), the (n ') th and (n') from the dosistor 7 and the dot buffer 8 The second linear interpolator 9 generates linearly interpolated pixel data inserted between the (n ') th and (n' + 1) th pixel data by performing linear interpolation of the +1) th pixel data. Horizontal scaling controller 10 for controlling the), And the output of the second linear interpolator can be directly supplied to an output device by including the vertical scaling unit and the horizontal scaling unit. The method of claim 1, wherein the vertical scaling controller (6) Perform linear interpolation of the (n) th and (n + 1) th original scan lines, and insert between the (n) th and (n + 1) th original scan lines when (MN) is greater than (N-1) Further control of the first linear interpolator 5 to generate an additional number T of the successive interpolated scan lines, i.e., MN divided by (N-1). Original digital image processing device characterized in that. The method of claim 2, wherein the first linear interpolator (5) An original digital image processing device, which is an additional feature of being a binary linear adder. The method of claim 1, wherein the horizontal scaling controller 10 Performs linear interpolation of the (n ') th and (n' + 1) th pixel data, so that when the (M'-N ') is greater than (N'-1), the (n') th and (n ') A quotient (T ') generated by dividing the additional number (T'), i.e., M'-N ', by (N'-1) of consecutive interpolated pixel data inserted between the +1) th original pixel data. And further controlling the second linear interpolator (9) in order to generate a). The method of claim 4, wherein the second linear interpolator (9) An original digital image processing device, which is an additional feature of being a binary linear adder. A frame memory 2 for storing original digital images having (N) consecutive original scanning lines and (N ') continuous original pixel data per said original scanning line, wherein (M) is larger than (N) ( When M ') is smaller than (N'), the vertical scaling unit for vertically scaling the original digital image to obtain (M) consecutive desired scan lines and (M ') continuous desired pixel data per scan line are obtained. An apparatus for processing an original digital image for obtaining a uniformly scaled desired digital image, further comprising a horizontal scaling unit for horizontally scaling a desired scanning line from the vertical scaling unit. Vertical scaling unit; And It characterized in that it comprises a horizontal scaling, The vertical scaling part A line memory (3) connected to said frame memory (2) for storing an (n + 1) th circular scan line from a frame memory (2); a line buffer 4 connected to the line memory 3 storing the (n) th circular scan line; A linear interpolator 5 connected to the line memory 3 and the line buffer 4; And It is connected to the frame memory 2, the line buffer 4 and the linear interpolator 5, and controls the storage of the original scan line in the line memory 3 and the line buffer 4, furthermore (MN) Divided by (N-1) is (S) and (n) is (n + 1) * (S) 1 (s) * (N for (s) in the range of 1 to (S) When the minimum number is satisfied, linear interpolation is performed between the (n) th and (n + 1) th original scan lines from the line memory 3 and the line buffer 4 to generate a redundant interpolated scan line inserted therebetween. A vertical scaling controller 6 for controlling the linear interpolator 5 to The horizontal scaling unit includes a horizontal scaling controller 10, the horizontal scaling controller 10 An address generator 37 connected to the line memory 3 and the line buffer 4 to control the line memory 3 and the line buffer 4 to output the first original pixel data of one original scan line. ); Generating means 33 for generating the remainder U 'generated by dividing (N') by (M '); Data register 56; An adder means (43), connected to said generating means (33) and said data register (56), for adding a number stored in said U 'and said data register to obtain a sum; And Connected to the adder means 43, the address generator 37 and the data register 56 to compare the sum with M ', activate the address generator 37, and activate the line memory 3; ) And the line buffer 4, where (N ') is divided by (M') and the quotient is (V '), the circle immediately before the output by the line memory 3 and the line buffer 4 is output. Another original pixel of the one scan line, offset from the pixel data by (V ') when the sum is less than (M') and by (V '+ 1) when the sum is at least equal to (M'). Outputs the data, and if the sum is at least equal to (M '), the difference between (M') and sum is stored in the data register 56; A calculation means 44 for storing, And an output of the horizontal scaling unit directly to an output device by including the vertical scaling unit and the horizontal scaling unit. 7. The vertical scaling controller (6) of claim 6, wherein Perform linear interpolation of the (n) th and (n + 1) th original scan lines, and insert between the (n) th and (n + 1) th original scan lines when (MN) is greater than (N-1) Further controlling the linear interpolator 5 to generate an quotient T generated by dividing the additional number T, i.e., MN, by (N-1) of successive interpolated scan lines. One digital image processing device. 8. The linear interpolator (5) according to claim 7, An original digital image processing device, which is an additional feature of being a binary linear adder. A frame memory 2 for storing original digital images having (N) consecutive original scanning lines and (N ') continuous original pixel data per said original scanning line, wherein (M) is smaller than (N) ( When M ') is larger than (N'), the vertical scaling unit for vertically scaling the original digital image to obtain (M) consecutive desired scan lines and (M ') continuous desired pixel data per scan line are obtained. An apparatus for processing an original digital image for obtaining a uniformly scaled desired digital image, further comprising a horizontal scaling unit for horizontally scaling a desired scanning line from the vertical scaling unit. Vertical scaling unit; And It characterized in that it comprises a horizontal scaling, The vertical scaling unit includes a vertical scaling controller 6 and a line memory 3 connected to the frame memory 2, and the vertical scaling controller 6 An address generator (37) connected to the frame memory (2) for controlling the frame memory (2) to output a first original scan line for storage in the line memory (3); Generating means (33) for generating the remainder (U) generated by dividing (N) by (M); Data register 56; An adder means (43) connected to the generating means (33) and the data register (56) to obtain a sum by adding the numbers stored in the (U) and the data register (56); And Connected to the adder means 43, the address generator 37 and the data register 56, comparing the sum to M and activating the address generator 37 to enable the frame memory 2; When (N) is divided by (M) and the quotient is (V) for controlling and storing in the line memory 3, the sum is equal to (M) from the original scanning line immediately outputted by the frame memory 2 (M). Outputs another original scan line offset by (V) when less than) and by (V + 1) when the sum is at least equal to (M); and when the sum is at least equal to (M), the data register ( Calculating means (44) for storing the difference between the sum in (M) and the sum in the data register (56) when the sum is less than (M), The horizontal scaling unit A do register (7) connected to said line memory (3) for storing (n '+ 1) th pixel data of one scanning line from said line memory (3); A dot buffer (8) connected to said do register (7) for storing (n ') th pixel data of said one scanning line from said line memory (3); A linear interpolator (9) connected to the dosistor (7) and the dot buffer (8); And It is connected to the line memory 3, the dot buffer 8 and the linear interpolator 9, and controls the storage of the pixel data into the do register 7 and the dot buffer 8, (M'-N ' ) Divided by (N'-1) is (S '), and (n') is (n '+ 1) * (S') for (s ') in the range from 1 to (S'). ) Linear interpolation of the (n ') th and (n' + 1) th pixel data from the do register 7 and the dot buffer 8 when the minimum number satisfies 1 (s ') * (N'). A horizontal scaling controller 10 which further controls the linear interpolator 9 to generate redundant interpolated pixel data inserted between the (n ') th and (n' + 1) th pixel data. Including, And the output of the linear interpolator (9) can be supplied directly to an output device by including the vertical scaling unit and the horizontal scaling unit. 10. The system of claim 9 wherein the horizontal scaling controller 10 Linear interpolation of the (n ') th and (n' + 1) th pixel data of the one scanning line from the line memory 30 is performed when (M'-N ') is larger than (N'-1). An additional number T 'of consecutive interpolated pixel data inserted between the (n') th and (n '+ 1) th original pixel data, T', that is, (M'-N ') is represented by (N'-1 And further controlling the linear interpolator (9) to generate a quotient (T ') generated by dividing by. 11. The linear interpolator (9) according to claim 10, wherein An original digital image processing device, which is an additional feature of being a binary linear adder. A frame memory 2 for storing original digital images having (N) consecutive original scanning lines and (N ') continuous original pixel data per said original scanning line, wherein (M) is smaller than (N) ( When M ') is smaller than (N'), the vertical scaling unit for vertically scaling the original digital image to obtain (M) consecutive desired scan lines and (M ') continuous desired pixel data per scan line are obtained. An apparatus for processing an original digital image for obtaining a uniformly scaled desired digital image, further comprising a horizontal scaling unit for horizontally scaling a desired scanning line from the vertical scaling unit. Vertical scaling unit; And It characterized in that it comprises a horizontal scaling, The vertical scaling unit includes a vertical scaling controller 6 and a line memory 3 connected to the frame memory 2, and the vertical scaling controller 6 A first address generator (37) connected to the frame memory (2) for controlling the frame memory (2) to output a first original scan line for storage in the line memory (3); First generating means (33) for generating the remainder (U) generated by dividing (N) by (M); First data register 56; First adder means (43) connected to said first generating means (33) and said first data register (56) to add a number stored in said (U) and said data register (56) to obtain a sum; And Connected to the first adder means 43, the first address generator 37 and the first data register 56 to compare the sum with M and activate the first address generator 37 The original circle outputted by the frame memory 2 when the share is (V) by dividing (N) by (M) for controlling the frame memory 2 and storing it in the line memory 3. Output another original scan line offset from the scan line by (V) when the sum is less than (M) and by (V + 1) when the sum is at least equal to (M), and the sum is at least (M) The first calculation means 44 for storing the difference between the (M) and the sum in the first data register 56 when the sum is less than (M) in the first data register 56 when ), The horizontal scaling unit includes a horizontal scaling controller 10, the horizontal scaling controller 10 A second address generator (37) connected to said line memory (3) for controlling said line memory (3) for outputting first original pixel data of one original scanning line; Second generating means (33) for generating the remainder (U ') generated by dividing (N') by (M '); Second data register 56; Second adder means (43) connected to said second generating means (33) and said second data register (56) to obtain a sum by adding the number stored in said U 'and said data register; And Connected to the second adder means 43, the second address generator 37 and the second data register 56, comparing the sum with M ', and comparing the second address generator 37 with And the line memory 3 is controlled, and immediately before the line memory 3 and the line buffer 4 are output when (N ') is divided by (M') and the quotient is (V '). The original pixel data of is offset by (V ') when the sum is less than (M') and (V '+ 1) when the sum is at least equal to (M'). Output another one-pixel data, and store the difference of sum with (M ') in the second data register 56 when the sum is at least equal to (M') and add the sum when the sum is less than (M '). Calculating means (44) for storing in the second data register (56), And an output of the horizontal scaling unit directly to an output device by including the vertical scaling unit and the horizontal scaling unit. A method for processing a raw digital image having (N) consecutive original image data when (M) is larger than (N) to obtain a uniformly scaled desired digital image having (M) continuous desired image data To Providing a first linear interpolator (5); And Dividing (MN) by (N-1), the remainder is called (S), and when (s) varies from 1 to (S), (n) is (n + 1) * (S) 1 (s If the minimum number satisfies) * (N), linear interpolation of the (n) th and (n + 1) th image data of the original image data is performed to perform the (n) th and (n + 1) th original image data. And controlling said first linear interpolator (5) to generate redundant interpolation image data interposed therebetween. A method for processing a uniform digital image having (N) consecutive original image data when (M) is smaller than (N) to obtain a uniformly scaled desired digital image having (M) continuous desired image data. In (I-1) step of storing the original image data in the memory unit 3; (I-2) controlling the memory unit 3 to provide an address generator 37 for outputting the first pixel data of the original image data; A step (I-3) of storing the number U, the remainder generated when the number N is divided by the number M, in the data register 56; A step (I-4) of adding a number U and a number stored in the data register 56 to obtain a sum; (I-5) comparing the sum with the number M; When (N) is divided by (M) and the quotient is (V), the sum is (M) from the original image data immediately outputted by the memory unit 2 by controlling the memory unit 2. (I-6) activating the address generator 37 to output another image data offset by (V) when smaller and (V + 1) when the sum is at least equal to (M); When the sum is at least equal to the number M, the difference generated by subtracting the number M from the sum is stored in the data register 56. When the sum is less than the number M, the sum is stored in the data register 56. (I-7) storing in); And And a step (I-8) of repeating step (I-7) to step (I-4) from step (I-4) until (M) original image data is output by the memory unit (2). And uniformly scaling the original digital image. An apparatus for processing a raw digital image having (N) consecutive original image data when (M) is larger than (M) to obtain a uniformly scaled desired digital image having (M) continuous desired image data. , A first linear interpolator 5; And Dividing (MN) by (N-1), the remainder is called (S), and when (s) varies from 1 to (S), (n) is (n + 1) * (S) 1 (s If the minimum number satisfies ** (N), the first linear interpolator 5 is controlled to perform linear interpolation of the (n) th and (n + 1) th image data of the original image data, and (n A first controller means (6) connected to said first linear interpolator (5) for generating redundant interpolation image data inserted between the < RTI ID = 0.0 > th < / RTI > A device for uniformly scaling a digital image made. A device for processing a uniform digital image with (N) consecutive original image data when the number (M) is smaller than the number (M) to obtain a uniformly scaled desired digital image with (M) continuous desired image data. To A first memory unit 2 for storing original image data; A first address generator (37) connected to the first memory unit (2) for controlling the first memory unit (2) to output first data of image data; First generating means 33 for generating a number U which is a quotient generated by dividing the number N by the number M; First data register 56; First adder means (43) connected to said first generating means (33) and said first data register (56) to obtain a sum by adding a number (U) and a number stored in said first data register (56); And It is connected to the first adder means 43, the first address generator 37, and the first data register 56 to compare the sum and the number M, divide (N) by (M), and share. When (V) is controlled from the original image data output by the first memory unit 2 by controlling the first memory unit 2, the sum is less than (M) by (V). Output another image data offset by (V + 1) when the sum is at least equal to (M), and sum in the number (M) and the data register 56 when the sum is at least equal to the number (M) And first calculating means 44 for activating the first address generator 37 to store the difference in the and the sum in the data register 56 when the sum is less than the number M. An apparatus for uniformly scaling a digital image, characterized in that.