KR100206534B1 - Zero power ic module - Google Patents

Zero power ic module Download PDF

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Publication number
KR100206534B1
KR100206534B1 KR1019910009439A KR910009439A KR100206534B1 KR 100206534 B1 KR100206534 B1 KR 100206534B1 KR 1019910009439 A KR1019910009439 A KR 1019910009439A KR 910009439 A KR910009439 A KR 910009439A KR 100206534 B1 KR100206534 B1 KR 100206534B1
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KR
South Korea
Prior art keywords
battery
power
lead
terminal
integrated circuit
Prior art date
Application number
KR1019910009439A
Other languages
Korean (ko)
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KR920001691A (en
Inventor
퀴작 다니엘
Original Assignee
아치 케이. 말론
에스티 마이크로일렉트로닉스 인코포레이티드
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Publication of KR920001691A publication Critical patent/KR920001691A/en
Application granted granted Critical
Publication of KR100206534B1 publication Critical patent/KR100206534B1/en

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    • H—ELECTRICITY
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    • H01L23/495—Lead-frames or other flat leads
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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Battery Mounting, Suspending (AREA)
  • Semiconductor Memories (AREA)
  • Connection Of Batteries Or Terminals (AREA)

Abstract

본 발명의 집적 회로 패키지는 주전력의 공급이 중단될 경우에 데이타를 보전하기 위해 휘발성 메모리 칩과 백업 배터리를 캡슐화한다. 상기 패키지는 비전도성 재료의 본체내에 캡슐화된 핑거 리이드 조립체를 포함하고 동일 평면상의 베이스 지지 핑거 리이드는 접속 영역을 가로지른다. 상기 배터리의 한 단자는 베이스 지지 핑거 리이드에 용접되고, 집적 회로 칩은 배터리 전도성 에폭시 층에 의해 다른 배터리 단자에 직접 접착된다. 상기 집적 회로 칩, 배터리 및 베이스 지지 핑거 리이드의 스태크된 조립체는 중앙 영역내에 배치되어, 금 상호 접속 와이어를 포함한 상기 스태크된 조립체가 패키지 성형체내에 완전히 캡슐화된다.The integrated circuit package of the present invention encapsulates a volatile memory chip and a backup battery in order to preserve data when main power supply is interrupted. The package includes a finger lead assembly encapsulated within a body of non-conductive material and coplanar base support finger leads traverse the connection area. One terminal of the battery is welded to the base support finger lead, and the integrated circuit chip is directly bonded to the other battery terminal by a battery conductive epoxy layer. The stacked assembly of the integrated circuit chip, battery, and base support finger lead is disposed in a central region such that the stacked assembly, including the gold interconnect wire, is fully encapsulated in a package molded body.

Description

제로 전력 IC 모듈Zero Power IC Module

제1도는 본 발명의 제1실시예에 따라 백업 배터리의 음극 단자상에 집적회로칩이 장착되어 있는 리이드 프레임 조립체의 평면도.1 is a plan view of a lead frame assembly in which an integrated circuit chip is mounted on a negative terminal of a backup battery according to a first embodiment of the present invention.

제2도는 단일 모울딩 패키지내의 반도체 집적회로와 리이드 프레임의 부분파단 측면도.2 is a partially broken side view of a semiconductor integrated circuit and lead frame in a single molding package.

제3도는 제2도의 집적회로, 백업 배터리 및 핑거 리이드 조립체의 부분 파단 평면도.3 is a partially broken plan view of the integrated circuit, backup battery and finger lead assembly of FIG.

제4도는 백업 배터리의 양극 단자상에 집적회로 칩이 장착되어 있는 리이드 프레임 조립체의 평면도.4 is a plan view of a lead frame assembly in which an integrated circuit chip is mounted on a positive terminal of a backup battery.

제5도는 단일 모울딩 패키지내에 캡슐된 제4도의 리이드 프레임 조립체, 백업 배터리 및 집적회로 칩의 부분 파단 측면도.FIG. 5 is a partially broken side view of the lead frame assembly, backup battery and integrated circuit chip of FIG. 4 encapsulated in a single molding package.

제6도는 제5도의 집적회로 패키지의 부분 파단 평면도.6 is a partially broken plan view of the integrated circuit package of FIG.

제7도는 본 발명의 다른 실시예에 따라 리이드 프레임 조립체상에 장착된 반도체 칩과 백업 배터리의 평면도.7 is a plan view of a semiconductor chip and backup battery mounted on a lead frame assembly in accordance with another embodiment of the present invention.

제8도는 제7도의 핑거 리이드 조립체상에 장착되어 단일의 모울딩 패키지내에 캡슐화된 백업 배터리, 세라믹 기판 및 집적회로 칩을 갖는 집적회로 패키지의 부분 파단 측면도.FIG. 8 is a partially broken side view of an integrated circuit package having a backup battery, a ceramic substrate and an integrated circuit chip mounted on the finger lead assembly of FIG. 7 encapsulated within a single molding package.

제9도는 제8도의 집적회로 칩, 세라믹 기판, 백업 배터리 및 변형된 핑거 리이드 조립체의 부분 파단 확대 평면도.9 is an enlarged, partially broken plan view of the integrated circuit chip, ceramic substrate, backup battery, and modified finger lead assembly of FIG.

제10도는 제8도의 단일 모울딩 회로 패키지 일부분의 확대 단면도.FIG. 10 is an enlarged cross sectional view of a portion of the single molding circuit package of FIG.

제11도는 배터리와 집적회로가 직선형 리이드 프레임의 동일평면 베이스판 핑거 리이드위에 장착되어 단일의 모울딩 패키지내에 캡슐화되어 있는 반도체 집적회로의 부분 판단 측면도.FIG. 11 is a side view of a partial determination of a semiconductor integrated circuit in which a battery and an integrated circuit are encapsulated in a single molding package mounted on a coplanar base plate finger lead of a linear lead frame.

제12도는 제11도의 집적회로, 백업 배터리 및 핑거 리이드 조립체의 부분 파단 평면도.12 is a partially broken plan view of the integrated circuit, backup battery and finger lead assembly of FIG.

제13도는 배터리의 음극단자가 동일평면형 베이스판 핑거 리이드에 장착되고 집적회로 칩이 배터리의 음극 단자상에 장착되어 있는, 제11도와 비슷한 반도체 집적회로의 부분 파단 측면도.FIG. 13 is a partially broken side view of a semiconductor integrated circuit similar to FIG. 11, in which the negative terminal of the battery is mounted on the coplanar base plate finger lead and the integrated circuit chip is mounted on the negative terminal of the battery.

제14도는 제13도의 집적회로, 백업 배터리 및 핑거 리이드 조립체의 평면도.14 is a plan view of the integrated circuit, backup battery and finger lead assembly of FIG.

제15도는 J-리이드들이 접착 기판상에 납땜되어 있는 표면 장착식 듀얼-인-라인(dual-in-line) 집적회로 칩의 측면도.FIG. 15 is a side view of a surface mount dual-in-line integrated circuit chip having J-leads soldered onto an adhesive substrate. FIG.

제16도는 제15도에 도시된 표면 장착식 듀얼-인-라인 칩 패키지의 정면도.FIG. 16 is a front view of the surface mount dual-in-line chip package shown in FIG.

제17도는 제15도의 선 17-17을 따라 절단한 단면도.FIG. 17 is a cross-sectional view taken along the line 17-17 of FIG. 15. FIG.

제18도는 제15도의 선 18-18을 따라 절단한 단면도.18 is a cross-sectional view taken along the line 18-18 of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10, 40, 60, 80 : 반도체 칩 패키지 12 : 집적회로 칩10, 40, 60, 80: semiconductor chip package 12: integrated circuit chip

14 : 입력/출력 노드 16 : 커넥터 핀14 input / output node 16 connector pin

18 : 핑거 리이드 20 : 리이드 프레임 조립체18: finger lead 20: lead frame assembly

22 : 접속 영역 28 : 베이스 지지 핑거 리이드22: connection area 28: base support finger lead

30 : 비전도성 성형체 32 : 백업 배터리30: non-conductive molded body 32: backup battery

34 :와이어 52 : 세라믹 결합 기판34: wire 52: ceramic bonding substrate

82 : J-리이드 90 : 열반사 금속층82: J-lead 90: heat reflection metal layer

본 발명은 일반적으로 반도체 소자들이 패키지에 관한 것으로, 특히 주 전원이 끊어졌을때 메모리 데이터를 보전하기 위한 백업 배터리와 메모리 칩같은 반도체 집적회로를 캡슐화하는 집적회로 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to packages, and more particularly to integrated circuit packages that encapsulate semiconductor integrated circuits such as backup batteries and memory chips for preserving memory data when main power is lost.

반도체 집적회로 칩들의 통상의 전자회로 패키지들은 칩 소자를 감싸 밀봉하기에 적합하면서도, 열을 소산시키고, 구조적으로 지지하며, 소자의 리이드를 외부 핀 커낵터들에 전기적으로 접촉시키고 또한 패키지내의 다른 소자들을 서로 전기적으로 접속시킨다. 이런 패키지들은 단층 또는 다층의 부전도체로 형성될 수 있는바, 그중 한층에 반도체 칩이 매립된다. 유연한 금속 리이드들은 칩을 둘러싸는 상호 접속 영역으로부터 가장자리의 접속핀들까지 뻗어서 상위 전자회로의 인쇄회로판 소켓에 소자의 입력/출력 단자들을 연결한다.Conventional electronics packages of semiconductor integrated circuit chips are suitable for enclosing and sealing chip devices, while dissipating heat, structurally supporting them, electrically contacting the lead of the device with external pin connectors and also allowing other devices in the package to be sealed. Electrically connected to each other. Such packages may be formed of single or multiple negative conductors, in which a semiconductor chip is embedded. The flexible metal leads extend from the interconnection area surrounding the chip to the edge connecting pins and connect the device's input / output terminals to the printed circuit board sockets of the upper electronic circuit.

집적회로 패키지내에 캡슐화된 IC 칩상에서 수행되는 중요한 집적회로 제품으로는 전력 소모가 적고 메모리의 셀 밀도가 높은 특징을 갖는 정적 등속도 호출 기억장치(SRAM)같은 휘발성 반도체 메모리가 있다. 휘발성 메모리 셀을 갖는 이런 집적 메모리 회로들내의 유효한 논리 신호들의 발생 및 데이터의 유지는 전원 전압을 일정한 범위내에 유지하는가에 일부 좌우된다. 일반적인 집적회로 메모리 소지들에서, 집적회로들은 인가되는 외부 전원 전압을 감지하여 그 전압이 동작에 신뢰성을 줄만큼 충분한가를 결정한다. 전압이 저 전압이면 이 저 전압 조건에 응답하여 동작칩들이 비선택되고 대기 조건에 유지되는 제어 신호들을 발생시킨다. 이것은 저 전압 조건이 수정될때까지 판독/기록 동작들을 각각 억제하는 참 칩 선택신호(CS)와 그 보상 칩 선택 신호(CS)에 의해 일반적으로 행해진다.Important integrated circuit products performed on IC chips encapsulated in integrated circuit packages include volatile semiconductor memories, such as static constant speed call memory (SRAM), which are characterized by low power consumption and high memory cell density. The generation of valid logic signals and the retention of data in these integrated memory circuits having volatile memory cells depend in part on maintaining the supply voltage within a certain range. In typical integrated circuit memory holdings, integrated circuits sense the external power supply voltage applied and determine if the voltage is sufficient to provide reliability for operation. If the voltage is low, the operating chips generate control signals that are unselected and maintained in the standby condition in response to this low voltage condition. This is generally done by a true chip select signal CS and its compensation chip select signal CS, which respectively inhibit read / write operations until the low voltage condition is corrected.

메모리 칩이 선택하지 않은 상태에 있는 동안 휘발성 메모리 셀내의 축적 커패시터들의 전하 레벨들을 유지하여 기억된 데이터를 유지할 필요가 있다. 그렇게 하지 않으면, 프로그램과 데이터를 포함해 메모리 셀에 기억된 정보는 주 전력을 제거했을때 사라질 것이다. 상기 전력의 손실이 메모리 회로에 손상을 가져오지 않는다 할지라도, 기억된 정보의 손실은 프로세싱(processing)이 재설정되기 전에 메모리에 프로그램과 데이터를 다시 모드할 것을 요한다.While the memory chip is in the unselected state, it is necessary to maintain the stored data by maintaining the charge levels of the accumulation capacitors in the volatile memory cell. Otherwise, information stored in memory cells, including programs and data, will be lost when the main power is removed. Although the loss of power does not cause damage to the memory circuit, the loss of stored information requires reprogramming the program and data into memory before processing is reset.

메모리 반도체 회로상에 핀 단자를 추가하여 데이터 손실 문제를 해결하고자 하였는바, 그 추가 단자에 원격 전원으로부터 백업 전력이 공급되어 메모리 셀내에 데이터를 보전한다. 그러나 대부분의 집적회로 메모리들의 핀 패턴은 현재 표준화되어 있는바 ; 그 결과, 원격 백업 전원 전용의 다른 핀을 추가하면 표준 핀 패턴과 어울리지 않게 되어 기존의 회로들을 다시 설계해야 하는 문제가 발생할 것이다.In order to solve the data loss problem by adding a pin terminal on the memory semiconductor circuit, backup power is supplied from the remote power supply to the additional terminal to preserve data in the memory cell. However, the pin pattern of most integrated circuit memories is currently standardized; As a result, adding another pin dedicated to the remote backup power supply will not match the standard pin pattern, which will require redesigning existing circuits.

따라서, 소켓 면적과 표준 핀 형태에 영향을 주지 않으며, 주 전원이 손실되어도 기억된 데이터가 보존되는, 메모리 칩과 배터리를 캡슐화하는 반도체 메모리 패키지가 필요하게 되었다.Thus, there is a need for a semiconductor memory package that encapsulates a memory chip and a battery that does not affect socket area and standard pin shape, and that stored data is preserved even when main power is lost.

패키지된 칩의 원가와 크기의 상당한 부분은 패키지 제작에 들어가고, 신뢰성 있는 전기적 접속을 제공하는 외에 2가지 중요한 설계 기준은 원가 효율과 공간 효율이다. 따라서, 집적회로 칩과 백업 배터리를 안전하게 지지하는 개량된 소자 패키지에 대한 필요성이 존재하는바, 상기 패키지에는 표준 인쇄 회로판 소켓들과 적절하게 플러그 접속되도록 형성된 핀 커넥터들이 마련되어 있고, 백업 배터리를 지지하는데 필요한 패키지 공간은 최소화된다.A significant portion of the cost and size of packaged chips goes into package fabrication, and besides providing reliable electrical connectivity, two important design criteria are cost efficiency and space efficiency. Accordingly, there is a need for an improved device package that securely supports integrated circuit chips and backup batteries, which are provided with pin connectors configured to properly plug into standard printed circuit board sockets and support the backup battery. Required package space is minimized.

집적회로 메모리 소자용의 몇몇 패키지들은 2-부분의 패키지 구조중 반쪽 구간내에 모울드된 배터리를 포함한다. 이런 구조에서, 리이드 프레임의 베이스판에 칩을 장하하고 I/O패드들과 각각의 내부 리이드를 사이에 와이어들을 접착한다. 모울드를 가열한 다음 가열된 모울드 공동안으로 모울딩 수지를 주입한다. 그결과 한쪽의 모울드된 반 구간안에 수지에 의해 리이드 프레임과 IC 칩이 캡슐화된다,Some packages for integrated circuit memory devices include batteries molded in half of the two-part package structure. In this structure, the chip is loaded on the base plate of the lead frame and the wires are bonded between the I / O pads and the respective inner leads. The mold is heated and then the molding resin is injected into the heated mold cavity. As a result, the lead frame and the IC chip are encapsulated by the resin in one molded half section.

제2의 반쪽 구간안에는 소형 배터리와, 결정같은 별개의 성분들을 장착한다. 제2의 선택된 반쪽 구간에는 제1의 모울드된 반쪽 구간의 리이드 프레임의 핑거 리이드들과 접촉하도록 정밀하게 위치된 케넥터 핀들이 있다. 이중 구간 배열은대량 생산에 적용하기에 적합하였다. 그러나. 제2의 반쪽 구간에 의해 높이가 더 높이지기 때문에 임계 공간 생산품에 적용하도록 설정된최대 높이 한계를 초과하는 패키지가 생산된다.Inside the second half section is a small battery and separate components such as crystals. In the second selected half section there are connector pins precisely positioned to contact the finger leads of the lead frame of the first molded half section. The dual section arrangement was suitable for applications in mass production. But. Since the height is made higher by the second half section, a package is produced that exceeds the maximum height limit set for application to critical space products.

따라서, 반도체 회로소자, 리이드 프레임 조립체 및 백업 배터리가 비전도성 재료의 단일 성형체안에 캡슐화되는 개량된 소자 패키지에 대한 필요성이 존재하는바, 그 패키지의 높이는 백업 배터리가 들어있지 않은 통상의 소자 패키지의 높이보다 크지 않다.Accordingly, there is a need for an improved device package in which the semiconductor circuitry, lead frame assembly, and backup battery are encapsulated in a single molded body of nonconductive material, where the height of the package is the height of a conventional device package that does not contain a backup battery. Not greater than

본 발명은 백업 배터리를 포함해 집적회로 소자를 캡슐화하는 개량된 패키지를 제공하는, 백업 배터리의 단자들중 하나에 집적회로 소자를 장착함으로써 그리고 리이드 프레임 조립체의 베이스판 핑거 리이드에 나머지 배터리 단자를 장착함으로써 상기 백업 배터리의 제한요소들을 극복한다. 이런 배열에서, 배터리는 전력 리이드의 베이스판 지지부 위에 스토크되고, 그 배터리위에 집적회로가 스토크된다. 바람직한 실시예에서, 베이스판 핑거 리이드는 나머지 핑거 리이드들과 동일 평면상에 있고, 핑거 리이드 상호 접속 영역을 가로지르는 베이스 지지부를 포함한다. 집적회로 가판은 전도성 접착제층에 의해 배터리 단자에 접착된다. 백업 배터리와 집적회로는 소켓 면적이나 핀 형태를 바꾸지 않고도 패키지의 성형체내에 완전히 밀봉된다. 이런 동일 평면형에서는, 패키지의 두께는 약간 증기하지만 와이어 접착상의 문제점은 피하게 된다.The present invention provides an improved package for encapsulating integrated circuit devices, including a backup battery, by mounting the integrated circuit device to one of the terminals of the backup battery and mounting the remaining battery terminals to the base plate finger lead of the lead frame assembly. Thereby overcoming the limitations of the backup battery. In this arrangement, the battery is stoked over the base plate support of the power lead, and the integrated circuit is stoked on the battery. In a preferred embodiment, the baseplate finger lead is coplanar with the remaining finger leads and includes a base support across the finger lead interconnect area. The integrated circuit board is bonded to the battery terminals by a conductive adhesive layer. The backup battery and integrated circuit are completely sealed in the molded body of the package without changing the socket area or pin shape. In this coplanar type, the thickness of the package is slightly steamy but the problem of wire adhesion is avoided.

다른 실시예에서, 백업 배터리의 한 단자를 베이스판 핑거 리이드상에 장착하고 나머지 배터리 단자에 세라믹 기판을 장착한다. 비전도성 에폭시층으로 세라믹 기판위에 집적회로 기판을 접착하고, 연결 도체에 의해 하부의 백업 배터리 단자에 전기적 접촉이 이루어진다. 세라믹 기판의 표면을 고도로 연마해 매끄럽게 다듬질하여, 거칠고 불규칙한 단자면을 가질 수도 있는 백업 배터리의 양극 또는 음극 단자에 전기적인 접촉을 하기 위해 크기가 다른 집적회로 칩들을 지지한다.In another embodiment, one terminal of a backup battery is mounted on the base plate finger lead and a ceramic substrate is mounted on the other battery terminal. The non-conductive epoxy layer adheres the integrated circuit board onto the ceramic substrate and makes electrical contact to the underlying backup battery terminals by the connecting conductors. The surface of the ceramic substrate is highly polished and smoothed to support different sized integrated circuit chips for electrical contact to the positive or negative terminals of the backup battery, which may have rough and irregular terminal surfaces.

표면 장착의 경우, 백업 배터리는 밀봉되고, 재유동 납땜(reflow soldering)을 하는 동안 열반사 금속층에 의해 열손상으로부터 보호된다.In the case of surface mount, the backup battery is sealed and protected from thermal damage by a layer of heat reflective metal during reflow soldering.

이하 첨부 도면들을 참조하여 본 발명을 자세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

이하 동일한 부분들은 명세서와 도면 전반을 통하여 제각기 동일한 참고번호로 표시하였다. 본 발명은 N형 실리콘 반도체 칩에 모노리틱 CMOS/LSI 기술로 장착되는 정적 등속도 호출 기억장치(SRAM)와 함께 설명된다. 그러나, 본 발명의 패키지 조립체는 별개의 소자뿐 아니라 집적 소자용 교환가능한 백업 배터리 전원을 캡슐화하고 제공하는데 이용될 수도 있지만, 입력/출력 노드가 여러개인 휘발성 메모리 집적회로에 특별히 사용될 수도 있음은 물론이다. 따라서, 최광의로 보아 본 발명은 별개의 회로요소 세분된 회로요소 및 집적 회로요소를 포함해(이들에 한정되지 않음) 백업 배터리를 필요로하는 1개 이상의 회로소자들과, 분리된 소자와 집적 소지의 하이브리드 집합체들을 수용하는 모울딩 가능한 어떤 패키지에도 합체될 수 있다.Hereinafter, the same parts are denoted by the same reference numerals throughout the specification and drawings. The present invention is described with a static constant speed call memory (SRAM) mounted on an N-type silicon semiconductor chip with monolithic CMOS / LSI technology. However, the package assembly of the present invention may be used to encapsulate and provide replaceable backup battery power for integrated devices as well as discrete devices, but may also be used specifically for volatile memory integrated circuits with multiple input / output nodes. . Thus, in the broadest sense, the invention incorporates one or more circuit elements, including, but not limited to, separate circuit elements, subdivided circuit elements, and integrated circuit elements, which require a backup battery; It can be incorporated into any moldable package that accommodates your own hybrid assemblies.

제1, 2도에는 본 발명을 구현하는 반도체 칩 패키지(10)의 일례가 도시되어 있다. 패키지(10)는 입력/출력 노드를 (14)을 갖는 집적회로 칩(12)을 지지하고 캡슐화한다. IC 칩(12)은 예컨대 낮은 전력 소모와 높은 메모리 셀 밀도를 특징으로 하면서 상보형 금속 산화 반도체 기술에 의해 구현되는 2Kx8 정적 등속도 호출 기억장치이다.1 and 2 illustrate an example of a semiconductor chip package 10 implementing the present invention. Package 10 supports and encapsulates integrated circuit chip 12 with input / output nodes 14. IC chip 12 is a 2Kx8 static constant velocity call memory implemented by complementary metal oxide semiconductor technology, for example, characterized by low power consumption and high memory cell density.

예로든 패키지(10)는 그 종연부를 따라 24개의 외부 커넥터 핀들이 600mil의 간격으로 평행 2열로 배치되어 있는 듀얼-인-라인 형태로 되어 있다. 집적회로 칩(12)의 입력/출력 노드들(14)은 제1도에 도시된 것 처럼 리이드 프레임 조립체(20)의 전도성 핑거 리이드(18)에 의해 소정의 접속핀들(16)에 전기 접속된다.The example package 10 is in a dual-in-line configuration in which 24 external connector pins are arranged in two parallel rows at 600 mil intervals along the edge thereof. Input / output nodes 14 of integrated circuit chip 12 are electrically connected to predetermined connecting pins 16 by conductive finger leads 18 of lead frame assembly 20 as shown in FIG. .

제1, 2도를 참조하면, 내부 리이드들(18)은 중앙 상호 접속 영역(22)에 대해 방사상으로 이격되어 있고 커넥터 핀들(16)과 일체이다. 리이드 프레림 조립체(20)의 연결 부분(20L)은 제조중에 궁극적으로 잘려나가, 내부 리이드들(18)이 제각기 각각의 커낵터 핀(16)에 전기적으로 연결된다. 모울딩을 한뒤, 리이드 프레임 조립체(20)의 외주변에서 이송 사이드 레일 스트립들(24, 26) 역시 최종 제조 단계의 절단 및 성형 작업중에 잘려나간다.Referring to FIGS. 1 and 2, the inner leads 18 are radially spaced relative to the central interconnect area 22 and are integral with the connector pins 16. The connecting portion 20L of the lead praim assembly 20 is ultimately cut off during manufacture, so that the inner leads 18 are electrically connected to respective connector pins 16, respectively. After molding, the transport side rail strips 24, 26 at the outer periphery of the lead frame assembly 20 are also cut off during the cutting and forming operations of the final manufacturing step.

전도성 핑거 리이드(18)의 내단부들은 상호 접속 영역(22)둘레에 대칭으로 이격되어 있다. 전도성 핑거 리이드(18)의 내단부들은 비교적 폭이 좁고, 상호 접속 영역(22)으로부터 방사상으로 뻗어나가면서 점점 폭이 넓어진다. 리이드 프레임 조립체(20)의 중앙 베이스 지지 핑거 리이드(28)는 집적회로 패키지(10)의 종축선(Z)과 일치되게 뻗는다. 바람직한 실시예의 한 특징에 따르면, 베이스 지지 리이드(28)는 중앙에서 절단된뒤, 제2도에 도시된 것 처럼 리이드 프레임 조립체(20) 평면에 대해 오프셋되게 성형되어, 분리된 핑거 리이드 연결 바아 부분들(28A,28B)을 만든다. 분리된 연결 바아 부분들(28A,28B)은 핑거들(18)에 대해 수직 간격(A)만큼 오프셋된다.The inner ends of the conductive finger leads 18 are symmetrically spaced around the interconnect area 22. The inner ends of the conductive finger leads 18 are relatively narrow and gradually wider as they extend radially from the interconnect area 22. The central base support finger lead 28 of the lead frame assembly 20 extends coincident with the longitudinal axis Z of the integrated circuit package 10. According to one feature of the preferred embodiment, the base support lead 28 is cut centrally and then shaped to be offset relative to the lead frame assembly 20 plane as shown in FIG. Make the fields 28A and 28B. The separate connecting bar portions 28A, 28B are offset by the vertical gap A with respect to the fingers 18.

외부 커넥터 핀들(16)과 내부 핑거 리이드들(18)은 모울딩 중에 처음에는 동일 평면상에 있다. 모울딩이 끝난 후, 절단 및 성형 작업중에 케넥터 핀(16)을 패키지의 종측면을 따라 90°구부린다.The outer connector pins 16 and the inner finger leads 18 are initially coplanar during molding. After the molding is finished, the connector pin 16 is bent 90 ° along the longitudinal side of the package during cutting and forming operations.

반도체 칩 패키지(10)는 상위전자 장치의 인쇄 회로판 또는 다른 몇몇 반도체 패키지에 반도체 칩(12)의 입력/출력 들을 전기적으로 접속하는 표준 외부 핀패턴을 제공한다. 칩 패키지(10)에는 폴리에테르이미드나 에폭시 수지같은 중합체의 비전도성 재료의 성형체(30)가 있다. 본 배열에서, 리이드 프레임 조립체(20), 반도체 칩(12) 및 백업 배터리(32)는 성형체(30)내에 매립되어 캡슐화 된다.The semiconductor chip package 10 provides a standard external pin pattern for electrically connecting the inputs / outputs of the semiconductor chip 12 to a printed circuit board or some other semiconductor package of the upper electronic device. The chip package 10 includes a molded body 30 of a nonconductive material made of a polymer such as polyetherimide or epoxy resin. In this arrangement, the lead frame assembly 20, the semiconductor chip 12 and the backup battery 32 are embedded in the molded body 30 and encapsulated.

백업 배터리(32)는 기밀 봉지되어, 이송 모울딩 공정의 높은 온도 조건에 노출되었을때 전해질이 증발되지 않게 하는 것이 바람직하다. 그외에, 배터리(32)는 단락 회로의 전류 흐름에 응답하여 고 저항값까지 상승하는 비-선형 내부 임피던스를 갖는 것이 바람직하다. 이것은 리이드 프레임이 절단될때까지 백업 배터리(32)가 조립 및 이송 모울딩 중에 프레임에 의해 단락되기 때문에 필요하다.The backup battery 32 is preferably hermetically sealed to prevent the electrolyte from evaporating when exposed to the high temperature conditions of the transfer molding process. In addition, the battery 32 preferably has a non-linear internal impedance that rises to a high resistance value in response to current flow in the short circuit. This is necessary because the backup battery 32 is shorted by the frame during assembly and transfer molding until the lead frame is cut.

몇몇 경우에는, 백업 배터리(32)가 기밀 봉지되고 단락 보호부를 갖는외에, 조립 및 절단이 완료된 후 배터리의 충전 준위가 정격 전압까지 복귀되도록 재충전 가능한 것이 바람직하다.In some cases, in addition to the airtight sealing of the backup battery 32 and the short circuit protection, it is preferable to recharge the battery so that the charging level of the battery returns to the rated voltage after assembly and cutting are completed.

일 실시예에서, 배터리(32)는 직경이 12.5㎜이며, 3.2V의 직류 셀이다. 배터리(32)는 와이어 접착 및 이욧 모울딩중에 고온에 노출되기 때문에 필히 고온용이어야 한다. 그렇지 않으면 배터리내의 전해질이 증발되어 배터리 전하가 손실될 것이다. 적당한 배터리(32)로는 Rayovac Corporation에서 Part No, BR 1225 UHT로 시판중인 리튬-카본 모노플로라이드 셀이 있다. 이런 Rauovac 셀은 DC 3.2 V 및 35mAh로 정격되어 있고 저장수명은 70℃에서 10년이며 3-5분동안 225℃의 고온상태에서 고장없이 견딜 수 있기 때문에 본 이송 모울딩 공정에 특히 적당하다. 배터리(32)의 양극 단자(32P)와 음극 단자(32N)는 환형의 유전체 절연층(32Q)에 의해 서로에 대해 절연된다.In one embodiment, the battery 32 is 12.5 mm in diameter and is a 3.2 V DC cell. The battery 32 must be high temperature because it is exposed to high temperatures during wire bonding and splice molding. Otherwise the electrolyte in the battery will evaporate and the battery charge will be lost. Suitable batteries 32 include lithium-carbon monofluoride cells sold by Rayovac Corporation as Part No, BR 1225 UHT. These Rauovac cells are rated at 3.2 V DC and 35 mAh and have a shelf life of 10 years at 70 ° C and can withstand failures at high temperatures of 225 ° C for 3-5 minutes, making them particularly suitable for this transfer molding process. The positive terminal 32P and the negative terminal 32N of the battery 32 are insulated from each other by the annular dielectric insulating layer 32Q.

반도체 칩(12)은 Amicon CT-5047-2 같이 은이 충전된 에폭시 접착제의 전도성 칩착에 의해 배터리의 음극 단자(32N)에 접착되어 전기적으로 접속된다. 입력/출력 노드들(14)은 직경이 1.3mil인 미세한 금 와이어(34)에 의해 전도성 핑거 리이드들(18)중 소정의 것에 전기적으로 접속된다. 전도성 핑거 리이드들(18)과 I/O노드들(14)에 금 와이어(34)를 접착하는 것은 통상의 열음파 보올 접착 기술로 하는 것이 바람직하다.The semiconductor chip 12 is adhered to and electrically connected to the negative terminal 32N of the battery by the conductive chip adhesion of an epoxy adhesive filled with silver such as Amicon CT-5047-2. The input / output nodes 14 are electrically connected to any of the conductive finger leads 18 by a fine gold wire 34 having a diameter of 1.3 mils. Bonding the gold wire 34 to the conductive finger leads 18 and the I / O nodes 14 is preferably by conventional thermoacoustic adhesive bonding techniques.

백업 배터리(32)의 양극 단자(32P)는 캡슐화되기 전에 저항 용접이나 납땜에 의해 연결 바아 부분들(28A,28B)에 전기적으로 접속된다. 제2도에서 보다시피, 연결 바아 부분들(28A,28B)은 양쪽 다 양극(32P)에 접촉된 채 기다란 간격을 중심으로 분리되어 있다. 연결 바아 부분들(28A,28B)사이의 기다란 간격은 필수적인 것이 아니고 베이스 지지 핑거 리이드(28)를 잘단한뒤; 바아 부분들(28A,28B)을 성형한 부수적인 결과이다.The positive terminal 32P of the backup battery 32 is electrically connected to the connecting bar portions 28A and 28B by resistance welding or soldering before encapsulation. As shown in FIG. 2, the connecting bar portions 28A and 28B are separated about an elongated gap while both are in contact with the anode 32P. Elongated spacing between connecting bar portions 28A, 28B is not necessary and after cutting the base support finger lead 28; This is a minor result of shaping the bar portions 28A, 28B.

연결 바이 부분들(28A,28B)의 수직 오프셋(A)때문에 백업 배터리(32)와 집적회로 칩(12)을 접속 영역(22)의 상하좌우 중심에 위치시킬 수 있다. 더우기, 이런 배열이기 때문에, 핑거 리이드 조립체, 백업 배터리, 칩 및 금 와이어(34)를 성형체(30)안에 완전히 캡슐화할 수 있다. 그러나, 리이드 프레임 조립체(20)를 충분한 연성을 갖도록 선택할 수 있어서 연결 바아 부분들(28A,28B)을 리이드(18)와 베이스 지지 핑거 리이드(28)에 대해 수직으로 오프셋되는 연속 핑거 리이드 스트립으로 일체로 성형할 수 있음을 알아야 한다.Because of the vertical offset A of the connection via portions 28A and 28B, the backup battery 32 and the integrated circuit chip 12 can be positioned at the top, bottom, left and right centers of the connection area 22. Moreover, because of this arrangement, the finger lead assembly, backup battery, chip and gold wire 34 can be fully encapsulated in the molded body 30. However, the lead frame assembly 20 can be selected to have sufficient ductility so that the connecting bar portions 28A, 28B are integrated into a continuous finger lead strip that is vertically offset relative to the lead 18 and the base support finger lead 28. It should be noted that it can be molded into.

배터리(32)를 연결 바아 부분들(28A,28B)에 전기적으로 부착한 뒤에, 집적회로 칩(12)을 뱉터리의 음극 단자(32N)에 접착한다. 이어서 미세한 금 와이어들(34)의 양단을 I/O 노드들(14)과 각각의 리이드들(18)에 연결한다. 양극 베이스판 핑거 리이드(28)와 칩(12)의 양극 백업 전압 노드(14P) 사이에 금 와이어(34P)를 접착한다. 음극 백업 전압 노드(14N)는 금 와이어(34N)를 통해 배터리의 음극 단자(32N)에 전기적으로 접속한다.After electrically attaching the battery 32 to the connection bar portions 28A, 28B, the integrated circuit chip 12 is adhered to the negative terminal 32N of the spit battery. Both ends of the fine gold wires 34 are then connected to the I / O nodes 14 and the respective leads 18. A gold wire 34P is adhered between the anode base plate finger lead 28 and the anode backup voltage node 14P of the chip 12. The negative backup voltage node 14N is electrically connected to the negative terminal 32N of the battery through the gold wire 34N.

그뒤 리이드 프레임 조립체(20)를 다공동 분할 모울딩내에 위치시킨다. 모울드 공동을 이송 모울딩 기계내에서 밀폐하고, 폴리페놀렌 술파이드 같은 비전도성 캡슐화 재료를 미세한 탄환 모양으로 노즐을 통해 주입한다. 이런 주입이 일어나는 압력을 정밀 조정하여 금 와이어 접착을 훼손하지 않게 한다. 적당한 압력과 온도에서, 탄환들을 녹인 다음 모울드내의 채널안으로 흘려서 리이드 프레임 조립체(20)의 주변 공동들을 채워, 리이드 프레임 조립체(20), 백업 배터리(32), IC 칩(12) 및 금 와이어(34)를 완전히 캡슐화한다. 이어서 열과 압력을 가하여 수지를 모울드내에서 경화한 다음 오븐에서 더 경화한다.The lead frame assembly 20 is then placed in the cavity split molding. The mold cavity is sealed in a transfer molding machine and a non-conductive encapsulating material such as polyphenolene sulfide is injected through the nozzle into a fine bullet shape. The pressure at which this injection occurs is precisely adjusted so that the gold wire bonds are not compromised. At an appropriate pressure and temperature, the bullets are melted and flowed into channels in the mold to fill the surrounding cavities of the lead frame assembly 20, leading to the lead frame assembly 20, the backup battery 32, the IC chip 12, and the gold wire 34 ) Is fully encapsulated. The resin is then cured in the mold by applying heat and pressure and then further in an oven.

이상의 이송 모울드 공정의 결과로서, 비전도성 재료로 된 기다란 장방형의 성형체(30)의 형대로 패키지(10)가 생산된다. 모울드에서 제거한 뒤, 리이드 프레임 조립체(29)의 인접 핀들(16) 사이의 연결 부분(20L)을 잘라내어 그 핀들과 전도성 핑거 리이드들을 서로 절연시킨다. 그외에, 이송 사이드 레일들(24,26)도 모울드 조립체에서 잘리 분리한다.As a result of the transfer mold process, the package 10 is produced in the form of an elongate rectangular shaped body 30 made of a non-conductive material. After removal from the mold, the connecting portion 20L between adjacent pins 16 of the lead frame assembly 29 is cut out to insulate the pins and the conductive finger leads from each other. In addition, the conveying side rails 24 and 26 are also cut off from the mold assembly.

리이드 프레임 조립체(20)의 재료는 주석-도금 니켈이나 철 합금같은 통상의 금속 합금 또는 CDA 194같은 주석-도금 구리 합금으로 하는 것이 바람직하다.The material of the lead frame assembly 20 is preferably a conventional metal alloy such as tin-plated nickel or an iron alloy or a tin-plated copper alloy such as CDA 194.

주지하는 바와 같이, 조립중에 커넥터 핀들과 내부 전도성 리이드들은 바람직하게 연속 금속 스트립으로부터 찍어낸 연결 부분들(20L)과 사이드 이송 레일들(24, 26)에 의해 구조적으로 서로 연결된다. 이런 연결 부분들은 조작용으로 커넥터 핀들에 붙어있을 뿐이고 최종 사용전에 절단된다.As will be appreciated, during assembly the connector pins and the inner conductive leads are structurally connected to each other by connecting portions 20L and side conveying rails 24 and 26 which are preferably stamped from a continuous metal strip. These connections are only attached to the connector pins for manipulation and are cut before final use.

외부 핀들(16)중 소정의 것은 통상 직류 +5.0 V 인 전압Vcc를 공급하는 주전원 노드에 연결되기에 적합하고, 마찬가지로 다른 외부 커넥터 핀은 호스트 전자 장치의 접지 노드에 연결되어 접지-기준 GND를 제공하기에 적합함을 알 수 있다.Certain of the external pins 16 are suitable for connection to a mains node supplying a voltage Vcc, which is typically +5.0 V direct current, likewise other external connector pins are connected to the ground node of the host electronic device to provide a ground-referenced GND. It can be seen that it is suitable for the following.

나머지 핀들은 참 칩 선택 신호(CS), 보상 칩 선택 신호, 집적회로를 출입하는 데이터를 동시에 계수하는 신호(CLK) 및 상기 호스트 전자회로에 의해 생기는 각종의 다른 I/O 신호들용으로 사용된다. 비교기와 스위칭 회로(도시 안됨)는 상위 전자회로의 주 전원으로부터의 전압(Vcc)와 백업 배터리(32)의 전압을 비교한 다음 가장 높게 검출된 전압을 집적회로칩(12)에 자동적으로 공급한다.The remaining pins are true chip select signal (CS), compensation chip select signal The signal CLK, which simultaneously counts data entering and leaving the integrated circuit, and various other I / O signals generated by the host electronic circuit. The comparator and the switching circuit (not shown) compare the voltage from the main power supply of the upper electronic circuit with the voltage of the backup battery 32 and then automatically supply the highest detected voltage to the integrated circuit chip 12. .

제4, 5, 6도를 참조하여 본 발명의 다른 실시예에 따르면, 반도체 칩 패키니(40)는 집적회로 칩(12)과 백업 배터리(32)를 지지하여 캡슐화하고, 집적회로칩(12)은 백업 배터리(32)의 양극단자면(32P)에 장착된다. 제6도에서 보다시피, 베이스 지지 핑거 리이드 (28)와 배터리의 음극 전압 노드(14N) 사이에 금 와이어(34N)를 전기적으로 접속하고 칩(12)의 양극 백업 전압 노드(14P)와 배터리의 양극 단자면(32P)사이에 금 와이어(34P)를 접착한다. 백업 배터리의 음극 단자(32N)를 저항 용접으로 오프셋 연결 바아 부분들 (28A,28B)에 전기적으로 연결한다. 배터리(32)를 반대로 하는 이외에, 칩 패키지(40)는 근본적으로 제1 - 3도에 도시된 패키지(10)와 동일하다.According to another embodiment of the present invention with reference to FIGS. 4, 5, and 6, the semiconductor chip package 40 supports and encapsulates the integrated circuit chip 12 and the backup battery 32, and the integrated circuit chip 12. ) Is mounted on the positive terminal surface 32P of the backup battery 32. As shown in FIG. 6, the gold wire 34N is electrically connected between the base support finger lead 28 and the negative voltage node 14N of the battery, and the positive backup voltage node 14P of the chip 12 and the battery. The gold wire 34P is bonded between the positive terminal surface 32P. The negative terminal 32N of the backup battery is electrically connected to the offset connection bar portions 28A, 28B by resistance welding. In addition to reversing the battery 32, the chip package 40 is essentially the same as the package 10 shown in FIGS.

집적회로(12)는 Amicdodn CT-5047-2같이 은이 충전된 에폭시 접착제의 침착처럼 전도성 접착제에 의해 배터리 양극 단자(32P)에 전기적으로 접착된다. 수직 오프셋(A)때문에, 백업 배터리(32)와 집적회로 칩(12)의 스토크된 조합체가 접속영역(22)내에서 상하좌우로 중심이 맞쳐진다. 이런 배열에 따르면, 핑거 리이드 조립체, 백업 배터리, 칩 및 금 와이어들이 성형체(30)내에 완전히 캡슐화된다. 따라서, 배터리(32)가 제2도의 배터리 방향과 반대인 점에서만 칩 패키지(40)가 칩 패키지(10)와 다르고 패키지의 기본 높이는 동일함을 알 수 있다.The integrated circuit 12 is electrically bonded to the battery positive terminal 32P by a conductive adhesive, such as the deposition of a silver filled epoxy adhesive such as Amicdodn CT-5047-2. Because of the vertical offset A, the stoked combination of the backup battery 32 and the integrated circuit chip 12 is centered up, down, left and right in the connection region 22. According to this arrangement, the finger lead assembly, backup battery, chip and gold wire are fully encapsulated in the molded body 30. Therefore, it can be seen that the chip package 40 is different from the chip package 10 and the basic height of the package is the same only in that the battery 32 is opposite to the battery direction of FIG.

제7-10도에 의한 본 발명의 또 다른 실시예에 따르면 백업 배터리(32)가 저항 용접에 의해 연결 바아 부분들(28A,28B)에 전기적으로 접착되고 집적회로 칩(12)이 세라믹 결합 기판(52)에 의해 배터리 음극 단자(32N)에 기계적으로 장착된 반도체 칩 패키지(50)가 제공된다. 이런 배열에서, 집적회로 칩(12)은 전도성 에폭시 접착제의 침착에 의해 세라믹 결합 기판(52)에 부착된다. 세라믹 결합 기판(52)은 비전도성 에폭시 접착제 층에 의해 배터리 음극 단자(32N)에 접착된다. 제10도에 도시된 것처럼, 칩(12)상의 음극 전력 노드(14N)는 연결 도체(34V)를 거쳐 배터리 음극 단자(32N)에 전기적으로 연결된다. 연결 도체(34V)는 결합 기판(52)을 관통하는 구멍(52A)을 통해 뻗는다.According to another embodiment of the present invention according to FIGS. 7-10, the backup battery 32 is electrically bonded to the connecting bar portions 28A and 28B by resistance welding and the integrated circuit chip 12 is ceramic bonded substrate. A semiconductor chip package 50 mechanically mounted to the battery negative terminal 32N is provided by 52. In this arrangement, the integrated circuit chip 12 is attached to the ceramic bonded substrate 52 by the deposition of a conductive epoxy adhesive. The ceramic bonded substrate 52 is bonded to the battery negative terminal 32N by a nonconductive epoxy adhesive layer. As shown in FIG. 10, the negative power node 14N on the chip 12 is electrically connected to the battery negative terminal 32N via a connecting conductor 34V. The connecting conductor 34V extends through a hole 52A penetrating the coupling substrate 52.

세라믹 결합 기판(52)의 목적은 집적회로 칩(12)에 안정되고 균일한 지지면을 제공하는데 있다. 통상, 배터리의 단자면들(32P,32N)은 거칠고 불균일하며, 그 결과 배터리 표면에 일정하게 접촉하기가 어렵다. 집적회로 칩과 지지면 사이의 접촉을 원활하고 크게 하는 것은 반도체 칩에 생기는 기계적 응력의 영향을 피하는데 필요한바, 이런 응력은 LSI 회로망을 손상시킬 수도 있다. 그외에, 세라믹 기판(52)의 접착 면적은 크기가 다른 IC 칩들을 기계적으로 결합하기에 충분히 커야 한다. 예컨대, 결합면적이 배터리 음극 단자(32N)의 표면적보다 큰 집적회로 칩을 결합하는 것이 바람직할 수 있다. 따라서, 집적회로 칩(12)과 배터리 음극 단자(32) 사이에 세라믹 기판(52)을 끼우는 점에서 칩 패키지(50)가 칩 패키지(10)와 다름을 알 수 있다. 배터리, 세라믹 기판, 및 칩(12)의 총스태크된 높이는 성형체(30)내에 완전히 캡슐화될 만큼 충분히 작다.The purpose of the ceramic bonded substrate 52 is to provide a stable and uniform support surface for the integrated circuit chip 12. Typically, the terminal faces 32P and 32N of the battery are rough and uneven, and as a result, it is difficult to constantly contact the battery surface. Smooth and large contact between the integrated circuit chip and the support surface is necessary to avoid the effects of mechanical stress on the semiconductor chip, which may damage the LSI network. In addition, the adhesive area of the ceramic substrate 52 should be large enough to mechanically couple IC chips of different sizes. For example, it may be desirable to join an integrated circuit chip having a coupling area larger than the surface area of the battery negative terminal 32N. Accordingly, it can be seen that the chip package 50 is different from the chip package 10 in that the ceramic substrate 52 is sandwiched between the integrated circuit chip 12 and the battery negative terminal 32. The total stacked height of the battery, ceramic substrate, and chip 12 is small enough to be fully encapsulated within the molded body 30.

제11, 12도에 따르면, 반도체 칩 패키지 (60)는 백업 배터리(32)의 양극 단자(32P)를 베이스판 핑거 리이드(62)의 베이스판 지지부(62A)상에 장착한 채 집적회로 칩(32)을 지지하고 캡슐화한다. 베이스판 지지 핑거 리이드(62)와 지지부(62A)는 핑거 리이드(18)와 동일 평면상에 있고 접속 영역(22)을 가로지른다. 이들을 이렇게 동일 평면 형태로 하는 잇점의 제2, 5도에 도시된 오프셋 리이드 프레임 조립체와 비교하여 열음파 와이어 접착을 비교적 쉽게 할 수 있는데 있다.11 and 12, the semiconductor chip package 60 includes an integrated circuit chip with the positive terminal 32P of the backup battery 32 mounted on the base plate support portion 62A of the base plate finger lead 62. 32) Support and encapsulate. The base plate support finger lead 62 and the support portion 62A are coplanar with the finger lead 18 and cross the connection region 22. Compared to the offset lead frame assemblies shown in Figs. 2 and 5 of the advantage of having these coplanar shapes, hot sonic wire bonding can be made relatively easy.

직선의 동일평면형 베이스판 핑거 리이드(62)의 사용상의 제한은 약간 더 두툼하게 캡슐화된 패키지(30)를 생산한다는데 있다. 그 외에는 반도체 칩 패키지(60)를 제2도에 도시된 칩 패키지와 동일하게 구성한다.A limitation on the use of a straight coplanar base plate finger lead 62 lies in producing a slightly thicker encapsulated package 30. Otherwise, the semiconductor chip package 60 is configured similarly to the chip package shown in FIG.

제13, 14도에 도시된 것은 또 다른 장착 배열인바, 밴터리(32)의 음극 단자(32N)를 직선의 동일평면형 베이스판 핑거 리이드(62)의 베이스판 지지부(62A)상에 장착한다. 칩 패키지(70)의 구조는 제11도에 도시된 칩 패키지(60)의 구조와 동일하지만, 제13도의 배터리(32)는 제11도의 배터리(32)에 비해 반대로 되어 있다.13 and 14, which is another mounting arrangement, the negative terminal 32N of the battery 32 is mounted on the base plate support portion 62A of the straight coplanar base plate finger lead 62. As shown in FIG. The structure of the chip package 70 is the same as that of the chip package 60 shown in FIG. 11, but the battery 32 of FIG. 13 is reversed from that of the battery 32 of FIG.

제15-18도에는 또 다른 실시예로서 표면 장착식 듀얼-인-라인 모울드 패키지(80)가 도시되어 있다. 이 배열에서, 배터리(32)는 오프셋 베이스판 핑거 리이드 부분들(28A,28B)위에 장착된다. 제18도의 단면도에는 핑거 리이드 부분(28B)만이 도시되어 있지만, 배터리(32)는 제2도에 도시된 것과 같은 방식으로 핑거 리이드 부분들 둘디에 장착됨은 물론이다. 금 와이어들(34)은 제3도에 도시된 것과 같은식으로 해당 핑거 리이드(18)에 열음파 접착된다. 표면 장착 조립체 (80)에서, 바람직하게 자립 지재형이어서 일단(82A)이 성형체(30) 밑으로 휘어져 포켓(84)안으로 들어가는 외부 J-리이드들(82)과 일체로 전도성 핑거 리이드들(18)을 성형한다. J-리이드(82)에는 또한 땜납 부분(86)과 접촉하는 둥근 부분(82B)이 있다.15-18 illustrate a surface mount dual-in-line mold package 80 as another embodiment. In this arrangement, the battery 32 is mounted on the offset base plate finger lead portions 28A, 28B. Although only the finger lead portion 28B is shown in the cross-sectional view of FIG. 18, the battery 32 is of course mounted to the finger lead portions in the same manner as shown in FIG. The gold wires 34 are thermoacoustically bonded to the corresponding finger leads 18 as shown in FIG. In the surface mount assembly 80, the conductive finger leads 18 integrally with the outer J-leads 82, which are preferably self-supporting, so that one end 82A is bent under the molding 30 and into the pocket 84. Mold. J-lead 82 also has rounded portion 82B in contact with solder portion 86.

땜납 부분(86)은 절연 기판(88)의 표면에 접착된다. 기판(88)은 G-30 폴리아미드처럼 유리 천이온도(T )가 높고 Kevlar 에폭시 또는 Kevlar 폴리아미드 섬유처럼 층상 유연성이 양호한 것이 바람직하다.The solder portion 86 is adhered to the surface of the insulating substrate 88. The substrate 88 preferably has a high glass transition temperature T like G-30 polyamide and good layer flexibility like Kevlar epoxy or Kevlar polyamide fibers.

땜납 부분들(86)은 J-리이드들(82)의 굴곡 부분들(82B)에 의해 면 접촉하도록 기판(88)위에 평행하고 이격된 패턴으로 신중히 정열된다. J-리이드들(82) 각각은 땜납으로 미리 도금된다. 그뒤 이중파 재유동 납땜 등에 의해 배치(batch) 납땜 공정에서 각각의 J- 리이드/땜납 부분에 땜납 이음부를 형성한다. 재유동 납땜 공정중에, 표면 장착 패키지(80)를 땜납욕으로부터의 복사열에 노출시키는바, 이런 땜납욕은 SN63-Pb36 땜납의 공융점인 183.9℃(363℉) 근처에 있을 수 있다. J-리이드와 핑거 리이드를 통한 열전도에 의해 또 땜납욕으로부터의 열복사에 의해 중합체 패키지 성형체(30)로 열이 전달된다. 그 결과, 성형체(30)와 배터리(32)는 재유동 공정중에 고온으로 되기 쉽다.The solder portions 86 are carefully aligned in a parallel and spaced pattern on the substrate 88 such that they are in surface contact by the bent portions 82B of the J-leads 82. Each of the J-leads 82 is preplated with solder. Solder joints are then formed in each J-lead / solder portion in a batch soldering process, such as by double wave reflow soldering. During the reflow soldering process, the surface mount package 80 is exposed to radiant heat from the solder bath, which may be near 183.9 ° C. (363 ° F.), the eutectic point of the SN63-Pb36 solder. Heat is transferred to the polymer package molded body 30 by heat conduction through the J-lead and finger lead and by heat radiation from the solder bath. As a result, the molded body 30 and the battery 32 tend to become hot during the reflow process.

표면 장착식의 중요한 특징에 따르면, 땜남욕으로부터의 복사열은 알루미늄, 구리 또는 니켈 등의 열반사 금속층(90)에 의해 성형체(30)로부터 반사된다.According to an important feature of the surface mount type, radiant heat from the solder bath is reflected from the formed body 30 by the heat reflective metal layer 90 such as aluminum, copper or nickel.

금속층(90)은 패키지 성형체(30)의 밑면(30A)에 접착되는 연미된 알루미늄 박판이나 호일이 바람직하다. 그렇지 않으면, 금속층(90)은 Bausch ＆ Lomb Incorporated에 의해 생산되는 90-8TM반사제 같이 유기 접착 재료와 반사금속 입자들을 혼합한 것을 얇게 코팅한 것이다.The metal layer 90 is preferably a soft aluminum sheet or foil adhered to the bottom surface 30A of the package molded body 30. Otherwise, the metal layer 90 is a thin coating of a mixture of organic adhesive material and reflective metal particles, such as the 90-8 TM reflector produced by Bausch & Lomb Incorporated.

Claims (14)

전자회로 소자에 전력을 공급하는 소자 패키지에 있어서: 비전도성 재료의 본체와; 상기 비전도성 재료의 본체내에 캡슐화되고, 핑거 리이드들중 하나는 전력 리이드를 형성하는 다수의 전도성 핑거 리이드들을 포함하는 핑거 리이드 조립체와 ; 양극 전력 단자와 음극 전력 단자를 가지며, 상기 단자들중의 하나는 상기 전력 리이드상에 장착되는 배터리와 ; 상기 비전도성 재료의 본체내에 캡슐화되어 상기 다른 배터리 전력 단자상에 장착회는 전자회로들로 구성됨을 특징으로 하는 소자 패키지.A device package for powering an electronic circuit device, comprising: a body of non-conductive material; A finger lead assembly encapsulated within the body of the non-conductive material, one of the finger leads including a plurality of conductive finger leads forming a power lead; A battery having a positive power terminal and a negative power terminal, one of the terminals mounted on the power lead; And an electronic circuit encapsulated in a body of said non-conductive material and mounted on said other battery power terminal. 제1항에 있어서, 상기 전도성 핑거 리이드들과 상기 전력 리이드가 서로 거의 동일 평면상에 있음을 특징으로 하는 소자 패키지.The device package of claim 1, wherein the conductive finger leads and the power lead are substantially coplanar with each other. 제1항에 있어서, 상기 전력 리이드에는 핑거 리이드 상호 접속 영역내에 배치된 베이스 지지부가 있고 상기 배터리 단자들중 하나는 상기 베이스 지지부에 장착되어 전기적으로 연결됨을 특징으로 하는 소자 패키지.The device package of claim 1, wherein the power lead has a base support disposed in a finger lead interconnect area and one of the battery terminals is mounted and electrically connected to the base support. 제1항에 있어서, 상기 전자회로 소자는 반도체 칩상에서 수행되는 집적회로이고 ; 상기 칩은 상기 나머지 배터리 단자에 스태크된 관계로 기계적으로 장착되어 전기적으로 연결되며 ; 상기 집적회로는 다수의 입력/출력 노도들과 상기 입력/출력 노드들을 상기 전도성 핑거 리이드들에 연결하는 다수의 와이어 도체들과, 상기 칩이 장착된 배터리 단자와 상기 전력 리이드 각각에 상기 와이어 도체들에 의해 전기적으로 연결되는 양극 및 음극 전력 노드들을 갖는 것을 특징으로하는 소자 패키지.The electronic device of claim 1, wherein the electronic circuit element is an integrated circuit performed on a semiconductor chip; The chip is mechanically mounted and electrically connected in a stacked relationship to the remaining battery terminals; The integrated circuit includes a plurality of wire conductors connecting a plurality of input / output furnaces and the input / output nodes to the conductive finger leads, a battery terminal on which the chip is mounted, and the wire conductors on each of the power leads. And an anode and a cathode power nodes electrically connected by the device package. 제1항에 있어서, 상기 배터리에는 양극 접속 단자와 음극 접속 단자가 있고, 상기 음극 접속 단자는 상기 전력 리이드에 장착되어 전기적으로 연결됨을 특징으로 하는 소자 패키지.The device package of claim 1, wherein the battery has a positive connection terminal and a negative connection terminal, and the negative connection terminal is mounted on the power lead and electrically connected thereto. 제1항에 있어서, 상기 배터리에는 양극 접속 단자와 음극 접속 단자가 있고, 상기 양극 접속 단자는 상기 전력 리이드에 장착되어 전기적으로 연결됨을 특징으로 하는 소자 패키지.The device package of claim 1, wherein the battery includes a positive connection terminal and a negative connection terminal, and the positive connection terminal is mounted on the power lead and electrically connected thereto. 제1항에 있어서, 상기 소자 패키지는 상기 회로 소자와 상기 다른 배터리 전력 단자 사이에 삽입된 비-전도성 결합 기판을 포함한 특징으로하는 소자 패키지.2. The device package of claim 1, wherein the device package comprises a non-conductive coupled substrate inserted between the circuit device and the other battery power terminal. 제7항에 있어서, 상기 결합 기판에는 연결 구멍이 뚫려있고; 상기 전자회로 소자는 반도체 칩상에서 수행되는 집적회로이며; 상기 칩은 상기 결합 기판위에 스태크된 관계로 장착되고; 상기 집적회로 소자는 다수의 입력/출력 노드들과 상기 입력/출력 노드들을 상기 전도성 핑거 리이드들에 연결하는 다수의 와이어 도체들과, 상기 결합 기판이 장착되는 밴터리 단자와 상기 오프셋 전력 리이드 각각에 상기 와이어 도체에 의해 전기적으로 연결되는 양극 및 음극 전력 노드들을 가지며; 상기 와이어 도체들중 하나는 상기 집적회로 소자로부터 상기 연결 구멍을 통해 상기 결합 기판이 장착된 배터리 단자까지 연장됨을 특징으로 하는 소자 패키지.The method of claim 7, wherein the bonding substrate is bored with a connection hole; The electronic circuit element is an integrated circuit performed on a semiconductor chip; The chip is mounted on the bonded substrate in a stacked relationship; The integrated circuit device includes a plurality of input / output nodes and a plurality of wire conductors connecting the input / output nodes to the conductive finger leads, a terminal terminal on which the coupling substrate is mounted, and an offset power lead, respectively. Having positive and negative power nodes electrically connected by the wire conductor; One of the wire conductors extends from the integrated circuit element through the connection hole to a battery terminal on which the bonding substrate is mounted. 제1항에 있어서, 상기 배터리는 기밀 봉착됨을 특징으로 하는 소지 패키지.The package of claim 1, wherein the battery is hermetically sealed. 제1항에 있어서, 상기 배터리의 내부 저항은 단락 회로의 전류 흐름에 응답하여 비선형으로 증가함을 특징으로 하는 소자 패키지.The device package of claim 1, wherein the internal resistance of the battery increases nonlinearly in response to current flow in the short circuit. 제1항에 있어서, 상기 배터리가 재충전 가능함을 특징으로 하는 소자 패키지.The device package of claim 1, wherein the battery is rechargeable. 제1항에 있어서, 상기 소자 패키지는 표면 장착에 적합하고, 상기 비전도성 본체의 표면 장착측의 외면에 부착된 열 반사성 금속층을 포함함을 특징으로 하는 소자 패키지.2. The device package of claim 1, wherein the device package includes a heat reflective metal layer suitable for surface mounting and attached to an outer surface of the surface mounting side of the nonconductive body. 비전도성 재료의 본체내에 캡슐화된 다수의 입력/출력 노드들, 상기 비전도성 재료의 본체에 장착되어 본체 외부로 돌출하는 다수의 커넥터 리이드들, 및 상기 비전도성 재료의 본체내에 캡슐화되어 상기 입력/출력 노드들을 상기 커넥터 리이드들에 전기적으로 연결하는 다수의 전도성 핑거 리이드로 이루어지는 핑거 리이드 조립체를 포함하는 회로 소자를 갖는 형태의 전자회로 패키지에 있어서 : 다수의 상기 전도성 핑거 리이드들에는 상호 접속 영역에 대하여 이격되어 있는 내단부들이 있고; 상기 전도성 핑거 리이드들중의 하나는 전력 리이드를 형성하고 상기 상호접속 영역을 가로지르는 베이스 지지부를 가지며; 배터리에는 양극 및 음극 전력 단자들이 있으며, 상기 전력 단자들중의 하나는 상기 전력 리이드의 기판 지지부에 장착되어 전기적으로 연결되며, 상기 회로 소자는 다른 배터리 전력 단지에 장착됨을 특징으로 하는 전자회로 패키지.A plurality of input / output nodes encapsulated within the body of non-conductive material, a plurality of connector leads mounted on the body of the non-conductive material and protruding out of the body, and encapsulated within the body of the non-conductive material to the input / output An electronic circuit package having a circuit element comprising a finger lead assembly consisting of a plurality of conductive finger leads electrically connecting nodes to the connector leads, wherein the plurality of conductive finger leads are spaced apart from an interconnection area. There are internal ends; One of the conductive finger leads forms a power lead and has a base support across the interconnect area; The battery has positive and negative power terminals, one of the power terminals mounted and electrically connected to the substrate support of the power lead, and the circuit element mounted to the other battery power complex. 전자 회로 소자에 전력을 공급하는 배터리와 전자 회로 소자를 패키지하는 방법에 있어서; 핑거 리이드 조립체의 핑거 리이드상에 배터리의 전력 단자를 장착하는 단계와; 상기 배터리의 다른 전력 단자에 상기 전자회로를 장착하는 단계와; 상기 전자 회로 소자, 배터리, 및 전력 리이드의 상기 스태크된 조립체를 비전도성 재료의 본체내에 캡슐화하는 단계들로 구성됨을 특징으로 하는 패키지 방법.A method of packaging an electronic circuit element with a battery that supplies power to the electronic circuit element; Mounting a power terminal of the battery on the finger lead of the finger lead assembly; Mounting the electronic circuit at the other power terminal of the battery; Encapsulating the stacked assembly of the electronic circuit element, battery, and power lead in a body of non-conductive material.
KR1019910009439A 1990-06-06 1991-06-05 Zero power ic module KR100206534B1 (en)

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EP0460802B1 (en) 1997-02-12
EP0460802A3 (en) 1993-03-17
US5008776A (en) 1991-04-16
KR920001691A (en) 1992-01-30
EP0460802A2 (en) 1991-12-11
JPH04273159A (en) 1992-09-29
DE69124641D1 (en) 1997-03-27
DE69124641T2 (en) 1997-05-28

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