KR100206190B1 - Voltage level shift circuit - Google Patents

Abstract

The present invention relates to a voltage level shift circuit that minimizes a current path between a boosted power supply voltage and a ground voltage in a section in which a power supply voltage level is shifted and in which a gate terminal inputs a signal of a predetermined level from the outside A first P-type MOS transistor having a source terminal receiving a power supply voltage from the outside; A first N-type MOS transistor having a gate terminal receiving a signal of a predetermined level applied from the outside, and a source terminal connected to a ground voltage; A second P-type MOS transistor connected in series between the first P-type MOS transistor and the first N-type MOS transistor; A third P-type MOS transistor having a gate terminal connected to a first node connected between the second P-type MOS transistor and the first N-type MOS transistor, and a source terminal receiving a boosted power supply voltage from the outside; A second N-type MOS transistor having a gate terminal connected to the gate terminal of the third P-type MOS transistor, a source terminal connected to the ground voltage, and a drain terminal connected to a drain terminal of the third P-type MOS transistor; A power supply voltage output terminal connected to a drain terminal of the third P-type MOS transistor; A gate terminal is connected to a power supply voltage output terminal, a drain terminal is connected to a first node connected between the second P-type MOS transistor and the first N-type MOS transistor, and a source terminal is connected to the 4 P-type MOS transistor; And an inverter having an input terminal connected to the power supply voltage output terminal and an output terminal connected to the gate terminal of the second P-type MOSFET. With such an apparatus, the current path between the step-up power supply voltage and the ground voltage can be minimized in a section in which the power supply voltage level is shifted, and the number of transistors constituting the voltage level shift circuit can be reduced, have.

Description

A voltage level shift circuit < RTI ID = 0.0 >

The present invention relates to a voltage level shift circuit, and more particularly, to a voltage level shift circuit that minimizes a current path between a boosted supply voltage and a ground voltage in a section in which a power supply voltage level is shifted.

FIG. 1 schematically shows the configuration of a conventional voltage level shift circuit.

1, in a conventional voltage level shift circuit, a bulk terminal is connected to an output terminal of a first inverter 105 which receives and outputs a signal of a predetermined level from the outside, and a source terminal is connected to a ground voltage Vss A gate terminal is connected to an output terminal of a second inverter 106 to which an input terminal is connected to the gate terminal of the first N-type MOSFET 103 and a ground terminal A source terminal connected to the drain terminal of the first N-type MOSFET 103 and a drain terminal connected to the source terminal of the first N-type MOSFET 103, The first P-type MOSFET 101 and the second P-type MOSFET 101 are connected to each other. The source terminal of the first P-type MOSFET 101 is connected to the drain terminal of the second N-type MOSFET 104, A second P-type MOS transistor 102 having a gate terminal connected to a first node N1 to which the drain terminals of the first P-type and first N-type MOS transistors 101 and 103 are mutually connected, 2 input terminal is connected to a second node N2 to which the drain terminals of the P-type MOS transistor 102 and the drain terminal of the second N-type MOS transistor 104 are mutually connected, And a third inverter 107 for outputting a power supply voltage corresponding to a signal of a predetermined level. Here, the gate terminal of the first P-type MOS transistor 101 is connected to the second node N2, and the bulk terminal of the first and second P-type MOS transistors 101 and 102 is connected to the boosted power supply voltage .

Hereinafter, the operation of the voltage level shift circuit having the above-described configuration with reference to Fig. 2 will be described.

First, when driving the power supply voltage output level to a high level, when a high level signal Vcc is applied to the signal input terminal 108 from the outside, the first N-type MOSFET 103 is turned off the second N-type MOS transistor 104 is turned on and the second node N2 is discharged to the ground voltage level Vss.

Thus, the first P-type MOS transistor 101 connected to the gate terminal of the second node N2 is turned on, and the first N-type MOS transistor 103, which has already been turned off, the first node N1 whose path is blocked is charged up to the boosted power supply voltage Vpp level.

As the voltage level of the first node N1 rises to a high level, the second p-type MOS transistor 102 connected to the gate terminal of the first node N1 is turned off, The power supply voltage path (Vpp path) is cut off.

Therefore, the second node N2 discharged at the ground voltage (Vss) level is not disturbed by the step-up power supply voltage Vpp, and the output out1 from the third inverter 107 is from the outside And is output as the boosted power supply voltage Vpp level higher than the applied power supply voltage Vcc level.

Next, when driving the power supply voltage output level to a low level, when a low level signal (0V) is applied to the signal input terminal 108 from the outside, the first N-type MOSFET 103 is turned on 1 node N1 is discharged to the ground voltage (Vss) level.

Accordingly, when the second P-type MOSFET 102 connected to the first node N1 is turned on, the ground voltage path Vss path is blocked by the second N-type MOSFET 104 that has already been turned off The second node N2 is charged up to the boosted power supply voltage Vpp level.

As the voltage level of the second node N2 rises to a high level, the first p-type MOS transistor 101 connected to the gate terminal of the second node N2 is turned off, The power supply voltage path (Vpp path) is cut off.

Therefore, the first node N1 discharged at the ground voltage (Vss) level is not disturbed by the step-up power supply voltage Vpp, and the output out1 from the third inverter 107 becomes the step- And 0V is output by the second node N2 char- acted up to the level (Vpp).

However, according to the above-described conventional voltage level shift circuit, when the signal applied to the signal input terminal 108 transitions from the low level to the high level, the second N-typemos transistor 104 is turned on and the second P- When the signal applied to the section A and the signal input terminal 108 until the transistor 102 is completely turned off transitions from a high level to a low level, the first N-type MOSFET 103 is turned on There arises a problem that a current path is formed between the step-up power supply voltage Vpp and the ground voltage Vss in the section B until the P-type MOS transistor 102 is completely turned off.

(purpose)

It is therefore an object of the present invention to provide a voltage level shift circuit capable of minimizing a current path between a boosted power supply voltage and a ground voltage in a section where a power supply voltage level is shifted .

1 is a circuit diagram showing a configuration of a conventional voltage level shift circuit;

Fig. 2 is an operational timing diagram of the voltage level shift circuit of Fig. 1; Fig.

3 is a circuit diagram showing a configuration of a voltage level shift circuit according to an embodiment of the present invention;

4 is an operational timing diagram of the voltage level shift circuit of Fig.

DESCRIPTION OF REFERENCE NUMERALS

201, 202, 203, 204: P-type MOS transistor

205, 206: N-type MOS transistor 207: Inverter

208: External signal input terminal 209: Output terminal

(Configuration)

According to an aspect of the present invention, there is provided a voltage level shift circuit including a gate terminal receiving a signal of a predetermined level from the outside, a source terminal receiving a power supply voltage from the outside, A transistor; A first N-type MOS transistor having a gate terminal receiving a signal of a predetermined level applied from the outside, and a source terminal connected to a ground voltage; A second P-type MOS transistor connected in series between the first P-type MOS transistor and the first N-type MOS transistor; A third P-type MOS transistor having a gate terminal connected to a first node connected between the second P-type MOS transistor and the first N-type MOS transistor, and a source terminal receiving a boosted power supply voltage from the outside; A second N-type MOS transistor having a gate terminal connected to the gate terminal of the third P-type MOS transistor, a source terminal connected to the ground voltage, and a drain terminal connected to a drain terminal of the third P-type MOS transistor; A power supply voltage output terminal connected to a drain terminal of the third P-type MOS transistor; A gate terminal is connected to a power supply voltage output terminal, a drain terminal is connected to a first node connected between the second P-type MOS transistor and the first N-type MOS transistor, and a source terminal is connected to the 4 P-type MOS transistor; And an inverter having an input terminal connected to the power supply voltage output terminal and an output terminal connected to the gate terminal of the second P-type MOSFET.

In a preferred embodiment of the device, the bulk terminals of the first, second, third, and fourth P-type MOS transistors are supplied with a step-up power supply voltage from the outside.

(Action)

With such an apparatus, the current path between the step-up power supply voltage and the ground voltage can be minimized in a section in which the power supply voltage level is shifted, and the number of transistors constituting the voltage level shift circuit can be reduced, have.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 3 and 4.

In FIGS. 3 and 4, the same reference numerals are used for components that perform the same functions as those of the voltage level shift circuit shown in FIGS. 1 and 2. FIG.

3 shows a configuration of a voltage level shift circuit according to an embodiment of the present invention.

Referring to FIG. 3, the configuration of the voltage level shift circuit according to the embodiment of the present invention is as follows.

First, the gate terminal of the first P-type MOS transistor 201 and the gate terminal of the first N-type MOS transistor 205 receive a signal of a predetermined level applied from the outside via the signal input terminal 208, 1 The source terminals of the P-type MOS transistor 201 and the first N-type MOS transistor 205 are connected to the power supply voltage Vcc and the ground voltage Vss, respectively. The second p-type MOS transistor 202 is connected in series between the first p-type MOS transistor 201 and the first n-type MOS transistor 205, and the third p-type MOS transistor 203 and the second p- The gate terminal of the N-type MOS transistor 206 is connected to the first node N3 between the second P-type MOS transistor 202 and the first N-type MOS transistor 205. The source terminals of the third P-type MOS transistor 203 and the second N-type MOS transistor 206 are connected to the boosted power supply voltage Vpp and the battery voltage Vss, respectively. Next, the fourth P-type MOS transistor 204 is connected to the power supply voltage output terminal 209 whose gate terminal is connected to the drain terminal of the third P-type MOS transistor 203 and whose drain terminal is connected to the second P- 202 and the first N-type MOS transistor 205. The source terminal is supplied with the boosted power supply voltage Vpp from the outside and the source voltage is applied to the power supply voltage output terminal 209 The output terminal of the inverter 207 to which the input terminal is connected is connected to the gate terminal of the second P-type MOSFET 202. Here, each of the bulk terminals of the first, second, third, and fourth P-type MOS transistors 201, 202, 203, 204 is supplied with the boosted power supply voltage Vpp from the outside. And is connected to the bulk terminal step-up power supply voltage Vpp of the first, second, third and fourth p-type MOS transistors 201, 202, 203 and 204.

Hereinafter, the operation of the voltage level shift circuit having the above-described configuration will be described with reference to FIG.

First, when the voltage output level of the power supply voltage output terminal 209 is output to the high level, when a high level signal Vcc is inputted to the signal input terminal 208 from the outside, the first N-type MOSFET 205 are turned on and the first P-type MOS transistor 201 is turned off so that the first node N3 is driven to the ground voltage level Vss discharge.

Since the first node N3 is at a low level, the second N-type MOSFET 206, which is an input to the gate terminal thereof, is turned off, and the third P-type MOSFET 203 is turned on. The boosted power supply voltage Vpp of the high level applied to the source terminal of the third P-type MOSFET 203 is output to the output terminal 209.

At this time, since the step-up power supply voltage Vpp outputted to the power supply voltage output terminal 209 turns off the fourth P-type MOS transistor 204, the step-up power supply voltage path (Vpp path) to the first node N3 is set to .

While the voltage output level of the power supply voltage output terminal 209 is boosted from the low level to the high level (for example, the Vpp level), the inverter 207 detects the power supply voltage Vcc and supplies it to the second node N4 ) To a low level.

Next, when the voltage output level of the power supply voltage output terminal 209 is output as a low level, when a low level signal (0V) is inputted to the signal input terminal 208 from the outside, the first N-type MOSFET The first P-type MOS transistor 201 is turned on and the first node N3 is charged up to the power supply voltage level Vcc.

Since the first node N3 is at a high level, the second N-type MOSFET 206 is turned on and the third P-type MOSFET 203 is turned off. Therefore, A low-level ground voltage (Vss) applied to the source terminal of the second N-type MOSFET 203 is output to the output terminal 209.

At this time, the ground voltage Vss output to the power supply voltage output terminal 209 is input to the gate terminal of the fourth P-type MOSFET 204 to turn on the fourth P-type MOSFET 204, The power supply voltage level Vcc of the node N3 is charged up to the boosted power supply voltage level Vpp.

Accordingly, the third P-type MOS transistor 203 having the first node N3 as the input of the gate terminal is completely turned off, and the voltage output level of the power supply voltage output terminal 209 is output in the opposite phase The second P-type MOSFET 202 connected to the gate terminal of the inverter 207 is turned off.

Therefore, it is possible to minimize the current path generated between the step-up power supply voltage Vpp and the ground voltage Vss in the sections A and B where the power supply voltage level is shifted, and the number of transistors constituting the voltage level shift circuit The layout area can be minimized.

Claims (2)

A first P-type MOS transistor 201 having a gate terminal receiving a signal of a predetermined level from the outside and a source terminal receiving a power supply voltage Vcc from the outside; A first N-type Moostransistor 205 having a gate terminal receiving a signal of a predetermined level applied from the outside, and a source terminal connected to a ground voltage Vss; A second P-type MOS transistor 202 connected in series between the first P-type MOS transistor 201 and the first N-type MOS transistor 205; A gate terminal is connected to the first node N3 connected between the second P-type MOS transistor 202 and the first N-type MOS transistor 205. When the source terminal is supplied with the step-up power supply voltage Vpp from the outside A third P-type MOS transistor 203; The gate terminal is mutually connected to the gate terminal of the third P-type MOS transistor 203, the source terminal is connected to the ground voltage Vss, and the drain terminal is connected to the drain terminal of the third P- A second N-type MOSFET 306; A power supply voltage output terminal 209 connected to the drain terminal of the third P-type MOS transistor 203; A fourth P-type MOS transistor 204 (hereinafter, referred to as " MOS transistor ") having a gate terminal connected to the power supply voltage output terminal 209, a drain terminal connected to the first node N3, )Wow; And an inverter (207) having an input terminal connected to the power supply voltage output terminal (209) and an output terminal connected to the gate terminal of the second P-type MOSFET (202). The voltage level shifting circuit according to claim 1, wherein the bulk terminals of the first, second, third and fourth p-type MOS transistors (201, 202, 203, 204) are supplied with a step-up power supply voltage from the outside.