KR100205522B1 - Thin film transistor array panel and its fabrication method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array substrate of a liquid crystal display device, comprising: a substrate and at least one formed on the substrate so as to improve the aperture ratio of the thin film transistor array and to be suitable for providing a high brightness and low power consumption liquid crystal display device At least one gate bus line, a data bus line formed to intersect the gate bus line, a thin film transistor having a gate electrode connected to the gate bus line, and a single channel electrode connected to the data bus line, a thin film transistor, a gate bus line and data A color filter formed in an inter-region defined by the bus lines intersecting with each other, and formed on the color filter, and including pixel electrodes connected to other channel electrodes of the thin film transistor through contact holes formed in the color filter. A thin film transistor array substrate.

Description

Thin film transistor array substrate and manufacturing method thereof

1 is a cross-sectional view of a conventional thin film transistor array substrate and a color filter substrate.

2 is a diagram illustrating the structure of a thin film transistor array substrate according to the present invention.

3 and 4 illustrate an embodiment of a method for manufacturing a thin film transistor array substrate according to the present invention.

5 is a view showing another embodiment of a method for manufacturing a thin film transistor array substrate according to the present invention.

* Explanation of symbols for main parts of the drawings

1: lower plate 2: upper plate

10, 20, 30, 40: substrate 11, 31-1, 41-1: gate electrode

12, 32, 42: gate insulating film 13, 33, 43: active layer

14, 44: etch stopper 15, 34-1, 45-1: source electrode

16, 35, 46: drain electrode 17: protective film

18, 38, 49: pixel electrode 21: black matrix

22, 37, 48: color filter 23: common electrode

31-2: gate bus line 34-2, 45-2: data bus line

36, 47: storage capacitor electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array substrate of a liquid crystal display device. The present invention relates to a thin film transistor array substrate and a method for manufacturing a liquid crystal display device having high screen brightness and low power consumption by improving the aperture ratio of the thin film transistor array. It is about.

A conventional thin film transistor liquid crystal display device is a structure in which a liquid crystal is filled between a thin film transistor array substrate (hereinafter referred to as "bottom plate"), a color filter substrate (hereinafter referred to as "top plate"), and two substrates. Have That is, a pixel (PLXEL: Picture Element) based on the pixel electrode connected to the drain electrode of the thin film transistor and the thin film transistor, which are switching elements, is vertically and horizontally arranged, and the gate electrodes of each thin film transistor are connected to each other along one direction. A plurality of gate bus lines and a plurality of data bus lines connecting one channel electrode of each thin film transistor along one direction are formed on the lower plate, and the upper plate corresponds to one of red-green-blue (RGB) corresponding to each pixel. The color filter is formed to have a pigment. A black matrix formed of chromium is formed between each color filter, that is, in an area corresponding to the data bus line, the gate bus line, and the thin film transistor region of the thin film transistor array substrate. A protective film is formed on the surface of the color filter and the black matrix, and a common electrode is formed on the upper part of the substrate to apply an electric field to the liquid crystal corresponding to the pixel electrode.

FIG. 1 is a cross-sectional view illustrating the structure of a lower plate 1 of a thin film transistor liquid crystal display according to the related art and an upper plate 2 corresponding to a liquid crystal interposed therebetween. First, a lower plate 1 includes a substrate. A gate electrode 11 is formed on (10), and there is a gate insulating film 12, which is a transparent insulating material such as a silicon nitride film, on top of which an active layer, which is a semiconductor material such as amorphous silicon, is covered to cover the gate electrode. And an etch stopper 14 such as a silicon nitride film for protecting the active layer 13, and a source electrode 15 formed to partially overlap the active layer 13 and the etch stopper 14 thereon. The drain electrodes 16 are formed separately from each other, and a protective film 17 having contact holes formed on the drain electrode 16 region is disposed over the entire surface, and a pixel electrode 18 connected to the drain electrode is formed thereon. With transparent conductive material Formed.

In the upper plate 2, a black matrix 21 is formed on the substrate 20 with an opaque material to correspond to the thin film transistor, the gate bus line, and the data bus line formed on the lower plate 1, and the black matrix 21 is formed on the upper plate 2. The color filter 22 is formed to partially overlap the edge of the substrate, and the common electrode 23 is formed on the entire surface of the substrate using a transparent conductive material to cover the surface of the black matrix and the color filter 22.

At this time, the black matrix 21 and the color filter 22 are formed so that some regions overlap each other, which is required for the bonding margin and the backlight required in the process of bonding the liquid crystal between the upper plate 2 and the lower plate 1. Considering the margin to prevent the light leakage phenomenon that the light irradiated from the (back light) is diffracted or scattered.

Such a conventional thin film transistor liquid crystal display device has a problem in that the actual aperture ratio is reduced due to the consideration of the bonding margin of the upper and lower plates and the prevention of light leakage phenomenon.

In order to solve the conventional problems, the black matrix is formed on the lower plate so that the misalignment of the black matrix area due to the upper and lower plate bonding is eliminated, and the black matrix can be formed as wide as the margin preventing light leakage. A technology of a thin film transistor liquid crystal display device has been proposed.

Another conventional thin film transistor liquid crystal display is a black matrix made of black resin, which is a non-conductive pigment dispersion type photosensitive resin, on the upper portion of the protective film to cover the gate bus line, data bus line, and thin film transistor of the thin film transistor. A technique for forming a has been proposed.

However, even in the above two improved prior arts, a black matrix must be formed in consideration of a margin for preventing light leakage, and thus there is a limit in increasing the aperture ratio.

Thus, the present invention provides a substrate, at least one gate busline formed on the substrate, a data busline formed to intersect the gate busline, and a gate bus so as to minimize the margin for preventing the adhesion margin and the light leakage phenomenon. A thin film transistor having a gate electrode connected to the line and a single channel electrode connected to the data bus line, a color filter formed in an interregion where the thin film transistor and the gate bus line and the data bus line are defined to cross each other, and formed on the color filter. The thin film transistor array substrate includes a pixel electrode connected to another channel electrode of the thin film transistor by releasing contact holes formed in the color filter.

In addition, the present invention is to form a thin film transistor array substrate of the structure described above, the step of forming a gate electrode and a gate bus line with a conductive material on the substrate, and the insulating material and the insulating material on the gate electrode and the gate bus line and the substrate Stacking silicon in succession and patterning amorphous silicon to form a first insulating layer and an active layer, laminating a metal material on the exposed surfaces of the active layer and the first insulating layer, and then patterning the portion of the active layer Forming a source bus and a drain electrode in contact with each other, a data busline connected to the source electrode and intersecting with the gate busline, and forming a color filter on the exposed entire surface using a non-conductive dye or pigment. And forming a drain electrode contact hole exposing a part of the drain electrode on the color filter. After stacking the contact hole, the inner and the color filter a transparent conductive material on the top, a thin film transistor array substrate manufacturing method comprising the steps of: forming a pixel electrode pattern by etching.

The present invention provides a method of forming a gate electrode and a gate bus line using a conductive material on a substrate, and sequentially stacking an insulating material and amorphous silicon on the gate electrode and the gate bus line and the substrate, and patterning the amorphous silicon. Forming an insulating layer and an active layer, depositing a silicon nitride film on an exposed surface of the first insulating layer and the active layer to form an etch stopper, and a metal material on the exposed surfaces of the active layer, the etch stopper and the first insulating layer After stacking, patterning, forming a source electrode and a drain electrode in contact with each of the active layer and the portion of the etch stopper, and a data busline connected to the source electrode and intersecting the gate busline, the exposed entire surface Using a color filter using a non-conductive dye or pigment above, and exposing a portion of the drain electrode to the color filter Is a thin film transistor array substrate manufacturing method comprising and, after stacking the drain electrode contact hole inside and the color filter a transparent conductive material on the top, forming a pixel electrode by pattern etching to form a drain electrode hole contact hole.

2 is a view illustrating an embodiment of a thin film transistor array substrate, that is, a lower plate according to the present invention. FIG. 2A is a plan view centering on one pixel, and FIG. 2B is an AA cutting line. Fig. 2 is a cross-sectional view showing the cross-sectional structure of the storage capacitor region using the BB cutting line.

First, as shown in FIG. 2A, in the lower plate according to the present invention, a plurality of gate electrodes 31-1 and gate bus lines 31-2 connected to each other are formed on the substrate 30, and the gate electrodes are formed. An active layer 33 covering the gate electrode portion of the (31-1) / gate bus line 31-2 is formed via the gate insulating film. The source electrode 34-1 / data bus line 34-2 partially overlaps the active layer 33, and the drain electrode 35 is formed to partially overlap the active layer 33. In addition, a color filter 37 partially overlapping the source electrodes 34-1 / data bus lines 34-2 between two neighboring source electrodes 34-1 / data bus lines 34-2 is provided. Formed. In addition, the pixel electrode 38 connected to the drain electrode 35 through the contact hole T _D (T _S ) formed in the color filter 37 is a source electrode 34-1 / data bus line 34-2. ) And the gate electrode 31-1 / gate bus line 31-2.

On the other hand, the storage capacitor electrode 36 is formed on the adjacent gate electrode 31-1 / gate bus line 31-2 via a gate insulating film (not shown), and contacts the color filter covering the same. There is a storage capacity configured to be connected to the pixel electrode 38 by forming a hole (storage capacitor electrode contact hole) Ts.

Looking at the cross-sectional structure of each area of the lower plate, as shown in (b) of FIG. 2, the gate electrode 31-1 is formed on the substrate 30 with a metal such as chromium or aluminum, and the gate electrode thereon. A gate insulating film 32, which is a silicon nitride film or a silicon oxide film, is formed to cover 31-1. The active layer 33 is formed of amorphous silicon so that the gate electrode 31-1 overlaps with the gate insulating layer 32 interposed therebetween, and the source electrode 34-1 is located on one side of the active layer 33. The drain electrodes 35 are formed on the other side, separated from each other in the region where the 31-1 overlap. In this case, a gate bus line (not shown) is connected to the gate electrode 31-1, and the source electrode 34-1 is a data bus line (not shown) where the gate bus lines (not shown) cross each other. Is connected with).

On the other hand, the gate of the region where the source electrode 34-1, the drain electrode 35 and the upper portion of the active layer 33 above the gate electrode of the thin film transistor having such a structure and the gate bus line and the data bus line cross each other and are defined. The color filter 37 is formed to cover the upper portion of the insulating film. In this case, a drain electrode contact hole T _D is formed in the drain electrode 35 region, and a pixel electrode 38 using a transparent conductive material connected to the drain electrode is formed on the color filter 37. .

As shown in FIG. 2C, the storage capacitor region includes a gate bus line 31-2 formed of a metal material on the substrate 30, a gate insulating film 32 and a gate bus line 31-covering the upper portion thereof. There is a storage capacitor electrode 36 formed to overlap with 2). The storage capacitor is formed by using the gate bus line 31-2 as the first electrode and the storage capacitor electrode 36 as the second electrode. The color filter 37 is formed on the storage capacitor electrode 36, and the pixel electrode 38 is formed on the color filter 37. The pixel electrode 38 is connected to the storage capacitor electrode 36 through a storage capacitive contact hole Ts formed on the color filter to expose the storage capacitor electrode 36.

In addition, the thin film transistor array substrate of the present invention may have a protective film (not shown) of the same pattern under the color filter 38.

FIG. 3 is a process cross-sectional view illustrating each step of manufacturing the thin film transistor array substrate of the present invention centered on the thin film transistor region, and FIG. 4 is a step of manufacturing the thin film transistor array substrate of the present invention centered on the storage capacitance region. An example process cross section is shown.

First, as shown in FIGS. 3A and 4A, metal materials such as crumb, aluminum, and aluminum alloy are laminated on the substrate 30 using a sputtering device, and then pattern-etched to form a gate electrode 31. -1) to form. In this case, although not shown in the drawing, when the gate electrode 31-1 is formed of aluminum, an aluminum alloy, or the like, anodization film may be formed on the surface thereof.

Next, as shown in FIGS. 3B and 4B, silicon oxide films (silicon nitride films or silicon oxide films / silicon nitride films) and amorphous silicon are covered by the chemical vapor deposition method so as to cover the gate electrode 31-1. After successive lamination, the amorphous silicon is patterned to form the active layer 33 on the gate insulating film 32, which is a silicon oxide film, to cover the gate electrode 31-1. On the other hand, when an insulating film such as an oxide film and an amorphous silicon are sequentially stacked, an amorphous silicon (n ⁺ a ^- Si) doped with an impurity is laminated on the upper part, and then patterned in the same manner as the amorphous silicon to form an impurity on the active layer 33. This doped amorphous silicon layer (not shown) can be formed.

Next, as shown in FIGS. 3C and 4C, metal materials such as chromium and aluminum are laminated on the exposed surfaces of the active layer 33 and the gate insulating layer 32 using sputtering equipment. And a pattern etched source electrode 34-1 overlapping a portion of the upper portion of the active layer 33 of the thin film transistor region, and a drain overlapping a portion of the upper portion of the active layer 33 corresponding to the source electrode 34-1. An electrode 35, a data bus line 34-2 extending from the source electrode 34-1, and a storage capacitor electrode 36 overlapping a portion of the gate bus line 31-2 are formed. In addition, when an amorphous silicon layer (not shown) doped with impurities is formed on the active layer 33 formed of amorphous silicon, the source electrode 34-1 and the drain electrode 35 are each amorphous silicon doped with impurities. Formed to overlap with the layer (not shown), and patterned an amorphous silicon layer (not shown) doped with impurities using the source electrode 34-1 and the drain electrode 35 as a mask to form an active layer 33 to a source electrode. (34-1) An ohmic contact layer (not shown) can be provided between the active layer 33 and the drain electrode 35.

Next, as shown in FIGS. 3D and 4D, the active layer exposed from the source electrode 34-1, the source electrode 34-1, and the drain electrode 35 using color resists. A color filter 37 is formed so as to cover the 33, the exposed gate insulating layer 32, the storage capacitor electrode 36, and the data bus line 34-2. At this time, the color filter 37 has a predetermined pattern when viewed as a whole of the thin film transistor array substrate. In this pattern process, the color resist is removed from the upper portion of the drain electrode 36 and the upper portion of the storage capacitor electrode 36. A drain electrode contact hole T _D and a storage capacitor electrode contact hole Ts are formed on the 37.

Next, as shown in FIGS. 3E and 4E, a transparent conductive material such as ITO is formed in the drain electrode contact hole T _D , the storage capacitor electrode contact hole Ts, and the color filter 37. After the material is properly cmd using the sputtering equipment, the pixel electrode 38 is formed by pattern etching to partially overlap the data bus line 34-2 and the gate bus line 31-2.

FIG. 5 illustrates a thin film transistor having a structure in which an etch stopper 44 is formed of a silicon nitride film or the like on an active layer when a thin film transistor, which is a switching element for a pixel, is formed in an active layer. For example, the manufacturing method is illustrated.

First, in FIG. 5A and FIG. 5B, the gate electrode 41-1 is formed on the substrate 40 as shown in FIG. 4A and FIG. 4B, and the gate After the gate insulating film 42 is formed to cover the upper portion of the electrode 41-1, the active layer 43 is formed to cover the gate electrode 41-1.

Next, as shown in FIG. 5C, an etch stop 44 is formed on the active layer 43 overlapping the gate electrode 41-1. The etch stopper 44 laminates a silicon nitride film by a low pressure chemical vapor deposition (LPCVD) method, an atmospheric pressure chemical vapor deposition (APCVD) method, a plasma chemical vapor deposition (PECVD) method, etc. The silicon nitride film is etched away to remain. The reason why the etch stopper 44 is formed is to prevent damage to the active layer of the channel region caused by the etchant in a subsequent process, and in particular, an ohmic contact layer (n ⁺ a ^- Si) doped with impurities on the active layer. (Not shown), the etching selectivity is small between the amorphous silicon constituting the active layer and the amorphous silicon doped with the impurity constituting the ohmic contact layer, so that the ohmic contact layer on the channel region is removed using a source electrode and a drain electrode as a mask. In this case, it is difficult to determine the etch endpoint, thereby solving the problem of damaging the active layer of the channel region.

Next, as shown in (d) of FIG. 5, the source electrode 45-1 and the drain electrode 46 are formed to partially overlap the etch stopper 44, respectively, and as shown in (e) of FIG. 5, the source electrode A color filter 48 is formed on the exposed surface of the upper portion 45-1 and the drain electrode 46 and the data bus line (not shown), and on the color filter 48 so that the drain electrode 46 is exposed. contact holes (T _D) of a top, and then, as in the fifth degree (f), the contact hole (T _D), the drain electrode 46 color filter 48, a pixel electrode 49 connected to the contact and through the formation Form. The process method shown in (d) to (f) of FIG. 5 is the same as the process method shown in (c) to (e) of FIG. 3 except for the positional relationship according to the formation of the etch stopper. Therefore, explanation is omitted.

In another method of manufacturing a thin film transistor array substrate of the present invention, a protective film is formed of a silicon oxide film or a silicon nitride film before forming a color filter, and a color resist is applied thereon, and then the protective film and the color filter are formed in the same pattern. Can be.

The thin film transistor array substrate of the present invention described above is generally formed by combining the color filters formed on the top plate, that is, formed on the thin film transistor array substrate, and does not require a separate black matrix, and requires a thin film transistor, a gate bus line, and a data bus. Since the line is used as a black matrix, the aperture ratio can be improved to 80%, and in terms of the overall upper and lower plates, the black matrix is not formed and the lower protective film pattern process is performed together with the protective film during the color filter forming process. Since it is not formed, the number of masks and the number of steps can be shortened. In addition, even when the pixel electrode is extended to the upper portion of the data bus line, no capacitor is formed between the data bus line and the pixel electrode. This is because a silicon nitride film or a silicon oxide film is interposed between the two metal layers as a protective film. The effect obtained by interposing a color resist having?) Is usually about 2000 GPa, but the color filter is formed at a thickness of 1 to 2 mu m, so that the capacitance reduction effect is greater. Therefore, the capacitor generated between the data bus line and the pixel electrode can be ignored, so that a vertical crosstalk problem due to signal interference between the data bus line and the pixel electrode does not occur.

Claims (15)

A substrate, at least one gate busline formed on the substrate, a data busline formed to intersect the gate busline, a gate electrode connected to the gate busline, and one channel electrode connected to the data busline. A thin film transistor, a color filter formed in an area in which the thin film transistor, the gate bus line and the data bus line are defined to cross each other, and a thin film transistor formed on the color filter, the thin film transistor being formed on the color filter. A thin film transistor array substrate comprising a pixel electrode connected to another channel electrode of a transistor. The thin film transistor array substrate of claim 1, wherein the color filter partially overlaps the data bus line between two neighboring data bus lines. The thin film transistor array substrate of claim 1, further comprising a protective layer having the same pattern as the color filter under the color filter. 1. A method of manufacturing a thin film transistor array substrate, the method comprising: 1) forming a gate electrode and a gate busline on a substrate with a conductive material, and 2) continuously insulating insulating material and amorphous silicon on the gate electrode and gate busline and the substrate. Stacking and patterning the amorphous silicon to form a first insulating layer and an active layer, and 3) laminating a metal material on the exposed surface of the active layer and the first insulating layer, and then patterning the active layer. Forming a source electrode and a drain electrode in contact with a portion, respectively, and a data busline connected to the source electrode to intersect the gate busline, and 4) using a non-conductive dye or pigment on the exposed entire surface; Forming a color filter, and 5) forming a drain electrode contact hole exposing a portion of the drain electrode on the color filter. Comprising the steps of: sex, 6) a thin film transistor array substrate manufacturing method comprising the steps of: after stacking the drain electrode contact hole and the inner transparent conductive material on top of the color filter, the pattern etched to form the pixel electrode. 5. The method of claim 4, wherein in step 3), the gate insulating layer is interposed to form a storage capacitor electrode overlapping a portion of the gate bus line, and in step 5), the storage capacitor is formed on the color filter. And simultaneously forming a storage capacitor electrode contact hole for exposing the electrode, and in the 6) system, when the transparent conductive material is stacked, the pixel electrode is connected to the storage capacitor electrode through the storage capacitor electrode contact hole. A method of manufacturing a thin film transistor array substrate, characterized in that an additional capacitance is formed. The method of claim 4, wherein after the step 3), a transparent insulating material is laminated on the exposed entire surface of the source electrode, the drain electrode, and the data bus line to form a passivation layer. And patterning the same as in the step 5), wherein the drain electrode contact hole is formed to be the same as the color filter. 5. The color filter of claim 4, wherein in the 4) system, the color filter is formed to partially overlap the data bus line connected to the source electrode, and to partially overlap the neighboring data bus line, and to completely overlap the gator bus line. The thin film transistor array substrate manufacturing method characterized in that it forms a. The gate bus line and the neighboring gate bus line of claim 4, wherein the gate bus line and the neighboring gate bus line are formed to partially overlap the data bus line connected to the source electrode and partially overlap with the neighboring data bus line. And forming the color filter so as to partially overlap with the thin film transistor array substrate. The method of claim 4, wherein the pixel electrode is formed to expose a part of the color filter in the 6) system. 1. A method of manufacturing a thin film transistor array substrate, the method comprising: 1) forming a gate electrode and a gate busline on a substrate with a conductive material; Stacking and patterning the amorphous silicon to form a first insulating layer and an active layer, and 3) forming an etch stopper by increasing a silicon nitride film on an exposed surface of the first insulating layer and the active layer; 4) a source material and a drain electrode which are in contact with the active layer and a part of the etch stopper, respectively, by laminating a metal material on the exposed surfaces of the active layer, the etch stopper and the first insulating layer, and Forming a data busline connected to a source electrode and intersecting the gate busline; 5) non-conductive on the exposed entire surface; Forming a color filter by using a dye or a pigment; and 6) forming a drain electrode contact hole exposing a part of the drain electrode in the color filter; 7) inside the drain electrode contact hole and the color; After laminating a transparent conductive material on top of the filter, pattern etching to form a pixel electrode comprising the step of forming a pixel electrode. 11. The method of claim 10, wherein in step 4), the gate insulating layer is interposed to form a storage capacitor electrode overlapping a portion of the gate bus line, and in step 6), the storage capacitor is formed on the color filter. Simultaneously forming a storage capacitor electrode contact hole exposing the electrode, and in step 7), when the transparent conductive material is stacked, the pixel electrode is connected to the storage capacitor electrode through the storage capacitor electrode contact hole. A method of manufacturing a thin film transistor array substrate, characterized in that an additional capacitance is formed. The method of claim 10, wherein after the step 4), a transparent insulating material is laminated on the exposed entire surface of the source electrode, the drain electrode and the data bus line to form a passivation layer, and in the step 5), the color filter And patterning the same as in the step 6), wherein the drain electrode contact hole is formed to be the same as the color filter. The color filter of claim 10, wherein in step 5), the color filter is formed to partially overlap the data bus line connected to the source electrode, partially overlaps with a neighboring data bus line, and completely overlaps the gate bus line. The thin film transistor array substrate manufacturing method characterized in that it forms a. The gate bus line and the neighboring gate bus line of claim 10, wherein in step 5), the gate bus line and the neighboring gate bus line are partially overlapped with the data bus line connected to the source electrode and partially overlap with the neighboring data bus line. And forming the color filter so as to partially overlap with the thin film transistor array substrate. The method of claim 10, wherein in step 7), the pixel electrode is formed to expose a part of the color filter.