KR100204585B1 - Ifft/fft block and timing synchronous method applicable to ofdm/cdma - Google Patents

Abstract

The present invention relates to an IFFT / FFT block and a timing synchronization method which can be applied to an OFDM / CDMA scheme. The present invention relates to an order of FFT block input values, that is, block synchronization and sample by using an output value of an FFT block and a next correlation block. By selecting the timing synchronization, it is possible to obtain fast and accurate synchronization without wasting bandwidth.

Description

IFFT / FFT Block and Timing Synchronization Method Applicable to OFDM / CDMA

The present invention relates to a block and timing synchronization method. In particular, the present invention relates to an IFFT / FFT block and timing synchronization method that can be applied to an OFDM / CDMA method that can be used in an OFMD-CDMA modem that is newly emerging as a method for mobile multimedia. It is about.

In general, future communication services will be in the form of wireless multimedia services that allow users to access various services while enjoying freedom of movement. The communication system to provide these services must be able to accommodate variable and high speed data and have the ability to effectively share resources such as frequencies, databases, devices for computation and storage. In addition, the technology to reduce the size and power consumption of the terminal and the technology to cope with the ever-changing channel environment is a problem to be solved. Direct-Sequence Spread Spectrum Code Division Multiple Access (DSS-CDMA) method, which has been proven to be feasible in mobile voice communications, transforms a narrowband flat fading environment into a wideband frequency selective environment. By placing a (RAKE) receiver, ICI (Inter Chip Interference) can be reduced. However, this process increases the complexity and power consumption of the receiver. Orthogonal frequency division multiplexing (hereinafter referred to as OPDM), which has proven its superior performance in current broadcasting systems, has a serial-to-parallel changer to lengthen a symbol longer than a delay spread so that ISI (Inter Symbol Interference (hereinafter referred to as ISI) can be reduced, but it is difficult to expect frequency diversity because each symbol uses a narrow band frequency using one carrier.

Therefore, the present invention uses the output values of the FFT block and the correlation block of the next stage, in which the order of the FFT block input values, i.e., the IFFT / It is an object of the present invention to provide an FFT block and a timing synchronization method.

The IFFT / FFT block synchronization method, which can be applied to the OFDM / CDMA scheme according to the present invention for realizing the above object, selects any one of samples over-sampled through an A / D converter at the receiving end and serial / parallel. Passing to a transform and sample selector, converting from the step to N parallel signals in the serial / parallel conversion and sample selector and performing an operation through an N-point FFT block; Multiplying the output signal of a point by a PN code or Walsh code, such as a transmitting end, respectively, and summing these values through an adder; comparing the result value generated by the summing from the step with a specific boundary value If the value is smaller than the control signal, the control signal is sent to the serial / parallel conversion and the sample selector. The column transform and sample selector rotates the output N point values by one step and outputs the same, and performs the above process until the result value is at least N times higher than a specific value, and the result value from the step. When more than this specific value is more than N times, the rotation stop signal is passed to the serial / parallel conversion and the sample selector, and the serial / parallel conversion and the sample selector stop the rotation according to this signal.

The IFFT / FFT timing synchronization method which can be applied to the OFDM / CDMA scheme according to the present invention for realizing the above object comprises the steps of: initiating inverse FFT / FFT block synchronization at the receiving end; and timing synchronization control signal from the synchronization control block from the step. Is passed to the serial / parallel conversion and sample selector, and when the timing synchronization control signal is turned on, one sample is selected in order from the oversampled signals received from the A / D converter, and the timing synchronization control signal If is off, the step of fixing the currently selected sample index.

1 is a block diagram illustrating an IFFT / FFT block and a timing synchronization method applicable to an OFDM / CDMA scheme according to the present invention.

* Explanation of symbols for main parts of the drawings

1: multiplier 2: N-point IFFT block

3: parallel / serial converter and low pass filter

4: D / A Converter 5: A / D Converter

6: Serial / Parallel Conversion and Sample Selector 7: N Point FFT Block

8: Adder 9: Synchronous Control Block

Hereinafter, an IFFT / FFT block and a timing synchronization method that can be applied to an OFDM / CDMA scheme according to the present invention will be described in detail with reference to the accompanying drawings.

OFDM systems require robust channel coding and frequency interleaving techniques. Multi-Carrier (CDMA) is a multi-system that takes advantage of ISI strong OFDM and the frequency diversity effect of DS-CDMA. A block diagram of this OFDM-CDMA scheme is shown in the figure. As can be seen in the figure, the block comprises an N-point IFFT block (2), a parallel / serial conversion and a low pass filter (3), a D / A converter (4), an A / D converter (5), a series / parallel It consists of a transform and sample selector 6, an N-point FFT block 7, an adder 8, a synchronous controller 9, and the like. The input signal at node A is a signal mapped to BPSK or QPSK, which is then copied to N points and multiplied by a specific PN code or Walsh code to N point IFFT block 2. Become input. The N-point IFFT block 2 receives an input of N points, performs an IFFT operation, and again outputs an operation result value of N points. These N point signals are converted into a serial signal by outputting the N point parallel signals through the parallel / serial conversion and the low pass filter 3.

The output serial signal is converted by the D / A converter 4 and then input to the receiver through a channel. The serial signal input to the receiver is converted through an A / D converter 5 and then converted into a parallel signal through a serial / parallel conversion and a sample selector 6, and the parallel signal is transferred to an N-point FFT block 7. Is entered. The N-point FFT block 7 receives an input of N points, performs an FFT operation, and outputs an N-point operation result signal. Each of the output signals is multiplied by the same PN code or Walsh as the transmitting end, and outputs by adding the value of N points through the adder 8.

In order to recover the signal of the node A at the node F, the synchronization and the timing synchronization of the inverse FFT / FFT block must exactly match. Therefore, it is important to quickly and accurately match the synchronization and timing synchronization of the inverse FFT / FFT block. Here, the synchronization of the inverse FFT / FFT block indicates that the order of the output values of the N points of the IFFT blocks of the transmitting end and the order of the FFT input values of the fisheries end match. In other words, matching the order of the nodes B and the order of the nodes E is called synchronization of the inverse FFT / FFT block. Timing synchronization means that a band-limited serial signal that has passed through a channel is oversampled by a receiver A / D converter 5 at a specific value, and selects an optimal sample from the oversampled samples. To match the phase of the PN or Walsh code between the transmitting and receiving ends.

The method of synchronizing the inverse FFT / FFT block is as follows.

Any one of the oversampled samples is selected by the receiving A / D converter 5 and passed to the serial / parallel conversion and sample selector 6. For example, if the oversampling coefficient is 8, eight oversamplings are performed per symbol. One of these eight samples is randomly selected and passed to the serial / parallel conversion and sample selector 6. The serial / parallel conversion and sample selector 6 convert the signal to N points in parallel and then perform the operation through the N point FFT block 7. After performing the FFT operation, the N point output signal is multiplied by the PN code or Walsh code, respectively, such as the transmitting end, and these values are added through the adder 8. In other words, it is called a correlation operation or a correlation operation. The numerical result of the correlation operation is compared with a specific boundary value, and when the result value is smaller than the boundary value, a control signal is sent to the serial / parallel conversion and the sample selector 6. If the control signal is (On), the serial / parallel conversion and sample selector 6 rotate the output N point values by one step and output the result. In other words, when N is 4, that is, if the transceiver performs four inverse FFT / FFT, the receiver / serial / parallel conversion and the sample selector 6 output four values in parallel. If the four indices are (a) (b) (c) (d), the indices of each branch initially output from the serial / parallel conversion and the sample selector 6 are (a) (b) (c) ( d). That is, the order of the output signal of the serial / parallel conversion and the sample selector 6 is (a) (b) (c) (d). If the signal to rotate from the synchronous control block 9 is received, the serial / parallel conversion and the sample selector 6 rotate and output the output order. In other words, the initial order is output from (a) (b) (c) (d) to (b) (c) (d) (a). This process is performed until the value at node F is at least N times higher than the specified value. If the value at node F is greater than or equal to N times, the rotation stop signal is passed to the serial / parallel conversion and sample selector 6, and the serial / parallel conversion and sample selector 6 rotates. Stop according to this signal.

The reason for this process is that the signal at node A cannot be recovered at node F if the order at node B and the order at node E do not match exactly. In other words, if the order at node E is exactly the same as the order at the transmitting end, the correlation value at node F is 64 if there is no channel and noise and the processing gain is 64 (= N), and the order is not correct. This is because the autocorrelation value is output when the PN code and Walsh code are not synchronized.

If the value at node F is above a certain value, the order at node E is fixed so that the synchronization of the initial inverse FFT / FFT block is correct.

This process is expressed by the following formula 1,

[Equation 1]

The specific value of Equation 1 is a value considering channel characteristics and various environments and can be obtained through repeated simulation in a channel environment.

Where a _m (K) is the signal value at node F and n and γ are specific values.

Next, an algorithm for synchronizing timing will be described.

The receiver then synchronizes the reverse FFT / FFT block and then proceeds to timing synchronization. In the synchronization control block 9, the algorithm for matching the node E value to the inverse FFT / FFT block synchronization determines whether or not the value is greater than an arbitrary value δ set to a value larger than the specific value γ used. Is passed to the serial / parallel conversion and sample selector (6). The operation of the serial / parallel conversion and sample selector 6, which has received the timing synchronization control signal, is as follows. That is, when the timing synchronization control signal is On, one sample is selected according to the order among the eight oversampled signals transferred from the A / D converter 5. Assuming that the indices of the eight oversampled samples are (a) (b) (c) (d) (e) (f) (g) (h), if any sample (a) was selected at the beginning of synchronization, the current If the received timing synchronization control signal is On, the sample having the sample index (b) is selected. If the timing synchronization control signal is Off, the currently selected sample index is fixed.

This process is represented by the following formula 2, the logical expression.

[Equation 2]

In Equation 2, a _m (K) is a signal value at node F and δ is any specific value that is larger than γ value.

Through the above-described process, the synchronization and timing synchronization of the inverse FFT / FFT block can be continuously matched.

As described above, according to the present invention, the output values of the FFT block and the correlation block of the next stage are used to quickly and accurately synchronize the order of the FFT block input values, that is, block synchronization and sample selection to synchronize timing. There is an effect that can be obtained.

Claims (2)

In the IFFT / FFT block synchronization method applicable to the OFDM / CDMA scheme, selecting any one of the oversampled samples through the A / D converter of the receiver and passing it to the serial / parallel / conversion and sample selector And converting from the above step into a parallel signal of N points in the serial / parallel conversion and a sample selector, and then performing an operation through an N point FFT block. Multiplying each of the PN code or Walsh code and then adding these values through an adder, and comparing the result value generated by the addition from the step with a specific boundary value, if the result value is smaller than the boundary value, Sending a control signal to the conversion and sample selector; and if the control signal is on from the step, the serial / parallel conversion and sample selector are output. Outputting the values of N points by one step, and performing this process from the step until the result value is at least N times higher than a specific value, and when the result value is higher than the specific value from the step N times In case of abnormality, IFFT / FFT can be applied to the OFDM / CDMA scheme, which includes rotating stop signal to serial / parallel conversion and sample selector and serial / parallel conversion and sample selector to stop rotation according to this signal. Block and timing synchronization method. In the IFFT / FFT timing synchronization method which can be applied to the OFDM / CDMA scheme, the inverse FFT / FFT block synchronization is performed at the receiving end, and the timing synchronization control signal is converted from the synchronization control block to the serial / parallel conversion and sample selector. If the timing synchronization control signal is turned on, and if the timing synchronization control signal is on, one sample is selected according to the order of the oversampled signals received from the A / D converter, and if the timing synchronization control signal is off, the currently selected sample index is fixed. IFFT / FFT timing synchronization method that can be applied to the OFDM / CDMA method, characterized in that consisting of.