KR100200708B1 - Circuit for driving memory cells semiconductor memory device - Google Patents

Abstract

The present invention relates to a memory cell driving circuit of a semiconductor memory device. The present invention provides a semiconductor memory device having a plurality of word line drivers for driving word lines connected to memory cells of a semiconductor memory device, a row decoder for selecting the word line drivers, and word driver decoders for controlling the word line drivers, respectively. In the memory cell driving circuit of the present invention, by connecting the respective ground terminals of the word driver decoders to a power ground line, the ground lines contain a resistance component to block noise flowing into the ground lines, thereby damaging data stored in the memory cell. It can prevent the reception, thereby improving the reliability of the semiconductor memory device.

Description

Memory cell driving circuit of semiconductor memory device

The present invention relates to a memory cell driving circuit of a semiconductor memory device, and more particularly, to a memory cell driving circuit of a semiconductor memory device capable of blocking noise through a ground terminal.

In general, memory cells of a semiconductor memory device are designed to match the recording density of a product. For example, in the case of 16 MB memory unit and the second ²⁴ memory cells, the memory cell ²²⁶ for the 64 MB memory unit. In this way, the user inputs the necessary information into the numerous memory cells. It will print out the information already stored. Among many memory cells, a user inputs and outputs information to a specific memory cell. At this time, in order to select a specific memory cell among a large number of memory cells, a unique address of the specific memory cell must be designated. The addressing signal is applied to a decoding circuit, which is a circuit which is externally input and combined by a control element and then generates one or a plurality of memory cell selection signals. The decoding circuit is divided into a column decoder and a row decoder. Only the row decoder will be described herein. The row decoder is used to control the wordline driver, and the wordline driver is used to drive the access transistor of the memory cell.

When a specific memory cell is selected by the row decoding circuit, the data of the memory cell is read out or the external data is stored in the memory cell. Noise is generated through the ground terminal during the operation of such a circuit, and seriously affects the reliability of the semiconductor memory device.

1 is a circuit diagram of memory cells and memory cell driving circuits of a conventional semiconductor memory device. The circuit shown in FIG. 1 includes row decoders 11 and 13 for outputting a row line selection signal for selecting one or a plurality of row lines of a memory cell array when a row address is input. Word line drivers 15, 17, 19, and 21 for boosting the row line selection signal to allow sufficient driving of the access transistors 23 and 25 of the memory cell; Word Driver Decoders 27 and 29 that control the drivers 15, 17, 19 and 21.

The word drive decoders 27 and 29 are connected to the word line drivers 15, 17, 19 and 21 through the PX0 and PX1 lines, respectively. Word lines WL11 and WL12 are connected to the output terminal. The ground lines of the word drive decoders 27 and 29 are connected to a power ground line while being connected to each other.

An operation of the circuit of FIG. 1 will be described. When the row decoder 11 is selected by the address signal, a high level voltage is applied to the input terminals of the two word line drivers 15 and 17 through the NWE1 line, which is the main word line. At this time, the word drive decoder 27 is selected and the PX0 line is at a logic high level to activate the word line driver 15. Then, the access transistor 23 of the memory cell 31 connected to the word line WL11 is turned on to output the data stored in the memory cell 31 or the data is transferred to the memory cell 31. Is entered. After the predetermined time has elapsed, when the input / output of the data for the memory cell 31 is completed, the circuits currently operating in order to proceed with the operation of the other memory cell 33 should be returned to their original state.

Therefore, the PX0 line of the word driver decoder 27, which was at the logic high level, changes to the logic low level through the ground line G through MN0 which is turned on by the change of the node N2. At this time, since the PX0 and PX1 lines are connected to a plurality of word line drivers and have a very large load, they act like capacitors that accumulate charge. Given the amount of charge that increases with higher voltage, if the PX0 line with a high voltage of logic high level drops to a logic low level and its charges are discharged through G in a short time, G is momentarily logic low level by the charges. At higher voltage levels. The instantaneous voltage level generated at this time is called noise.

The word driver decoder 29 sharing G adjacent to the word driver decoder 27 is subjected to the influence of the noise generated from the word driver decoder 27 as it is. That is, the noise is transmitted to the PX1 line through MN1, which was on to keep the PX1 line at a logic low level. Noise carried on the PX1 line is carried to WL12 through MN2 turned on of the word line driver 17 operating at a logic high level. Then, the access transistor 25 of the memory cell 33, which has nothing to do with its current operation, is momentarily turned on in a state in which a small current can flow, but is stored in the capacitor 26 of the memory cell 33. Charge is lost. If this operation is repeated, the information previously stored in the memory cell 33 cannot be used properly. The smaller the level of the noise, the smaller the influence of adjacent memory cells.

As described above, according to the conventional semiconductor memory device, noise through the ground line damages data stored in the memory cell of the memory cell driving circuit connected to the copper ground line. In extreme cases, data stored in a memory cell may be lost.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a memory cell driving circuit of a semiconductor memory device capable of blocking noise through a ground line.

1 is a partial circuit diagram of memory cells and memory cell driving circuits of a conventional semiconductor memory device.

2 is a partial circuit diagram of memory cells and memory cell driving circuits of a semiconductor memory device according to the present invention;

The present invention to achieve the above object,

A memory cell of a semiconductor memory device having a plurality of word line drivers for driving word lines connected to memory cells of a semiconductor memory device, a row decoder for selecting the word line drivers, and word driver decoders for controlling the word line drivers, respectively. In the driving circuit, there is provided a memory cell driving circuit of a semiconductor memory device for connecting each ground terminal of the word driver decoders to a power ground line.

According to the present invention, noise through the ground line is cut off to protect the memory cell from the noise.

Hereinafter, the present invention will be described in detail through examples.

2 is a partial circuit diagram of memory cells and memory cell driving circuits of a semiconductor memory device according to the present invention. The circuit shown in FIG. 2 includes row decoders 111 and 113 for outputting a row line selection signal for selecting one or a plurality of row lines of a memory cell array when a row address is input, and boosting the row line selection signal to memory. Word Line Drivers 115, 117, 119, and 121 to allow the access transistors 123 and 125 of the cell to fully drive, and Word Driver Decoders that control the word line drivers 115, 117, 119, and 121. 127,129). The word drive decoders 127 and 129 are connected to the word line drivers 115, 117, 119 and 121 through the PX0 and PX1 lines, respectively, and the word lines WL11 'and WL12' are connected to the output terminals of the word line drivers 115, 117, 119 and 121, respectively. have.

One word drive decoder 127 includes a NAND gate 151 having an address signal as an input, a PMOS transistor 153 and an NMOS transistor 155 having respective gates connected to an output terminal of the NAND gate 151. have. The source of the PMOS transistor 153 is connected to a power supply, and the drain of the PMOS transistor 153 is connected to the drain of the NMOS transistor 155. The source of the NMOS transistor 155 is grounded through the G2 line and the drain is connected to the PX0 line.

Since the G2 line is connected to the power ground line affected by the ground source through the long line, it may be regarded as a kind of resistance connected between the word drive decoder 127 and the power ground line.

The word line driver 115 includes a first NMOS transistor 157 having a drain connected to NWE1 and a gate connected to a power supply, and a second NMOS transistor connected to a source of the first NMOS transistor 157 and a drain connected to a power supply. 159, a third NMOS transistor 161 having a gate connected to the drain of the second NMOS transistor 159, and a drain connected to the drain of the first NMOS transistor 157, a source of the second NMOS transistor 159, and a third NMOS transistor 159. A drain is connected to the source of the source 161, a gate is connected to the output terminal of the NAND gate 151, and the source includes a fourth NMOS transistor 163 grounded through a G3 line which is a ground line. A word line WL11 'is connected to the drain of the fourth NMOS transistor 163.

An operation state of the circuit of FIG. 2 will be described. When the row decoder 111 is selected by the address signal, a high level voltage is applied to the input terminals of the two word line drivers 115 and 117 through the NWE1 line. At this time, the word drive decoder 127 is selected by the address signal and the PX0 line is at a logic high level, thereby activating the word line driver 115. That is, the voltage applied to NWE1 turns on the second NMOS transistor 159 through the first NMOS transistor 157. At the same time, the output of the NAND gate 151 becomes the logic low level by the address signal, which turns on the PMOS transistor 153, thereby causing the PX0 line to rise from the logic low level to the logic high level.

Accordingly, the third NMOS transistor 161 is turned on and the voltage of the PX0 line is applied to the word line WL11 'to activate the memory cell 131 to output data stored in the memory cell 131 or to the memory cell 131. Enter.

After the predetermined time passes, the NAND gate 151 of the word drive decoder 127 outputs a logic high level voltage by an address signal. Then, the NMOS transistor 155 of the word drive decoder 127 When turned on, the PX0 line is electrically connected to the G2 line, transitioning from a logic high level to a logic low level. That is, the PX0 line is at zero potential.

However, since the G2 and G3 lines act as a kind of resistance, some of the charges accumulated in the PX0 line pass through the G2 line, and some of the charges are lost by the power ground line. Therefore, when the charge accumulated in the PX0 line is discharged through the G2 line, the noise caused by the ground line is blocked by not affecting other elements connected to the power ground line.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

As described above, according to the present invention, by connecting the word driver decoders to the power ground line affected by the ground source, the noise through the ground line is prevented from damaging the data stored in the memory cell of the memory cell driving circuit connected to the copper ground line. Thus, the reliability of the semiconductor memory device can be improved.

Claims (1)

A memory cell of a semiconductor memory device having a plurality of word line drivers for driving word lines connected to memory cells of a semiconductor memory device, a row decoder for selecting the word line drivers, and word driver decoders for controlling the word line drivers, respectively. In the driving circuit, And connecting respective ground terminals of the word driver decoders to a power ground line, respectively.