KR100200348B1 - Test circuit of sram - Google Patents

Abstract

The present invention relates to a test circuit of a static random access memory for testing the normal presence of cells of the static random access memory.

A plurality of static random access memories consisting of a first PMOS transistor MP1, a first N-MOS transistor MN1, a second P-MOS transistor MP2, and a second N-MOS transistor MN2 for writing or reading data. Static random access memory 100 having cells and a test signal generator 200 for testing the presence or absence of the static random access memory cells described above.

Description

Static random access memory test circuit

1 is a block diagram of N × M bits of static random access memory.

2 is a cell of normal random access memory.

3 shows a cell 1 of a random access memory in which a failure occurs.

4 is a cell of a random access memory in which a failure occurs.

5 is one embodiment of a static random access memory test circuit of the present invention.

6 is another embodiment of the static random access memory test circuit of the present invention.

7 is another embodiment of the static random access memory test circuit of the present invention.

8 is a static random access memory test signal generation circuit of the present invention.

9 is a timing diagram of a static random access memory test circuit of the present invention with cell 1 of a random access memory in which a failure has occurred.

The present invention relates to a test circuit of a static random access memory, and more particularly to a test circuit of a static random access memory for testing the normal presence of cells of the static random access memory.

1 is a block diagram of an N × M bit static random access memory, wherein the static random access memory is a second inverted first pre-charge signal PCB1 and first precharge signal PCB1. The precharge signal PCBB1, the third precharge signal PCB2, the fourth precharge signal PCB2 inverting the third precharge signal PCB2, the control dress signals ADR_XN: 1 and the second address. It is composed of cells of a plurality of random access memories that receive signals ADR_YM: 1 and output a first bit and a first bit bar.

FIG. 2 is a cell of a normal random access memory. The cell 10 of the random access memory includes first and second pass transistors PA1 and PA2, a first PMOS transistor MP1, and a first N-MOS transistor MN1. Composed of a first inverter (I1) consisting of a second inverter (I2) consisting of a first inverter (I1), a second PMOS transistor (MP2) and a second N-MOS transistor (MN2), the first, second pass transistors (PA1, PA2) ) Is commonly connected to the first address signal ADR_X, the first drain / source of the first pass transistor PA1 is connected to the second bit, and the first pass signal of the second pass transistor PA2 is The first drain / source is connected to the second bit bar, and the second drain / source of the first pass transistor PA1 is connected to the input of the first inverter I1 and the output of the second inverter I2. The second drain / source of the second pass transistor PA2 is connected to the input of the second inverter I2 and the output of the first inverter I1.

The write, data preservation and read operations of the cell 10 of the random access memory are as follows.

In order to write the data having the high logic value in the cell 10 of the random access memory, the high logic value is input to the first address ADR_X to turn on the first and second pass transistors PA1 and PA2. When a high logic value is input to 2 bits and a low logic value to a second bit bar, the first node A, which is an output of the first inverter I1, has a low logic value and a second inverter ( The second node B, which is an output of I2), has a high logic value, and a low logic value may be input to the first address ADR_X. Since the data written in the cell 10 of the random access memory by the first and second inverters I1 and I2 are latched continuously, the recorded data is preserved. In order to perform the read operation, a low logic value is input to the third precharge signal PCB2 and the fourth precharge signal PCBB2 of FIG. 1 to pull up the second bit and the second bit bar. Pull-up state and input the high address of the first address ADR_X, the voltage charged in the parasitic capacitor connected to the second bit bar is the first N-MOS transistor of the first inverter I1. The voltage of the first node A cannot be completely discharged to the ground voltage Vss according to the ratio of the transistors of the second pass transistor PA2 and the first N-MOS transistor MN1. Although the voltage is slightly higher than the ground voltage Vss, the voltage of the first node A is adjusted by adjusting the transistor sizes of the second PMOS transistor MP2 and the second NMOS transistor MN2 of the second inverter I2. Even though the voltage is slightly higher than the ground voltage Vss, the voltage of the second node B has a high logic value so that the second inverter has a high logic value. By adjusting the logic threshold voltage of (I2), the voltage charged in the parasitic capacitor connected to the second bit bar is completely discharged to the ground voltage (Vss) so that the second bit removes the high logic value during reading. Two bit bars output low logic values, respectively.

3 is a cell 1 of a random access memory in which a failure occurs, and cell 1 (20) of a bad random access memory is a second PMOS transistor of the second inverter I2 of the cell 10 of the normal random access memory in FIG. (MP2) is bad, and FIG. 4 is cell 2 of the random access memory in which the failure occurs, and cell 2 (30) of the bad random access memory is the first inverter I1 of the cell 10 of the normal random access memory in FIG. This is the case where the first PMOS transistor MP1 of Nm is defective.

The failure of the cell of the random access memory is caused by a defective contact or a bad manufacturing of the gate channel in the integrated circuit manufacturing process.

The write, data integrity and read operations of the cell 1 20 of the bad random access memory of FIG. 3 are as follows.

The write operation for writing the data having the high logic value in the cell 1 20 of the bad random access memory is the same as that of the cell 10 of the normal random access memory of FIG. 2, and the read operation is performed in the second PMOS. Although the transistor MP2 is not defective and does not operate, the voltage of the first node A does not completely discharge to the ground voltage Vss and the ground voltage similarly to the operation of the cell 10 of the normal random access memory of FIG. 2. Since the second NMOS transistor MN2 is turned on because the voltage slightly higher than Vss, the current flowing through the first NMOS transistor MN1 is considerably larger than the current flowing through the second NMOS transistor MN2. The voltage of the node A is discharged to the first NMOS transistor MN1 so that the voltage of the first node A becomes the ground voltage Vss, and the second NMOS transistor MN2 is turned off to read the second bit. (bit) is the high logic value, and the second bit bar is the low logic value. Since the respective outputs are performed, it is not possible to determine whether or not the cell 1 20 of the bad random access memory is defective during reading.

The second node having the high logic value written at the time of writing cannot be latched because the second PMOS transistor MP2 is defective at the time of data preservation of the cell 1 (20) of the bad random access memory. (B) has a low logic value after a predetermined time due to the leakage current, and the first node A has a high logic value by the first inverter I1, so that the data of the cell 1 (20) of the bad random access memory is bad. Has different data from the data recorded at the time of recording.

Therefore, in order to test a random random memory cell having a bad random access memory cell as shown in FIG. 3 or FIG. 4 among a plurality of random access memory cells of the conventional static random access memory, it is impossible to test whether or not there is a defect during writing and reading. Data integrity caused by leakage current during maintenance can be tested to determine whether or not the random access memory cell is defective. However, in the conventional case, in order to test whether the random access memory cell is defective, a sufficient time must be waited until the data of the defective random access memory cell has data different from the data written at the time of writing due to leakage current. It takes a long time to test for defects.

An object of the present invention is to provide a test circuit of a static random access memory that can test the presence or absence of defects in a random access memory cell in a short time to reduce the integrated circuit manufacturing cost.

In order to achieve the above objects, the test circuit of the static random access memory of the present invention is composed of a first PMOS transistor, a first N-MOS transistor, a second P-MOS transistor, and a second N-MOS transistor for writing or reading data. It has a plurality of static random access memory cells, and has a first bit bar having an inverted signal of the first bit and the first bit as an input or an output, for reading the first bit and the first bit bar respectively. Receiving a first and second precharge signal for pulling up, and having a second bit bar having an inverted signal of the second bit and an input or output of each of the static random access memory cells; A static random access memory for receiving third and fourth precharge signals for pulling up the second bit bar and the second bit bar for reading, and a low time constant for a predetermined time. When the first charge signal and the first bit bar are received and the first and second PMOS transistors are defective, the first test signal and the presence or absence of the same test as the precharge signal are tested. A second test signal having a low logic value is always output to the second test signal, and when the first PMOS transistor or the second & MOS transistor is defective, the second test signal equal to the precharge signal is always low A first test signal having a logic value is output, wherein the first test signal is connected to a first precharge signal or a third precharge signal of the static random access memory, and the second test signal is a static random access memory. And a test signal generating means connected to the second precharge signal or the fourth precharge signal.

Hereinafter, a test circuit of a static random access memory of the present invention will be described in detail with reference to the accompanying drawings.

5 is an embodiment of a test circuit of the static random access memory of the present invention. The test circuit of the static random access memory of the present invention includes a first PMOS transistor (MP1) and a first & MOS transistor that write or read data. (MN1), the static random access memory 100 having a plurality of static random access memory cells composed of (MN1), the second PMOS transistor (MP2) and the second N-MOS transistor (MN2) and the defects of the static random access memory cells It consists of a test signal generation circuit 200 for testing the presence.

The static random access memory 100 has the same configuration as in FIG. 1 and has a first bit bar having an inverted signal of the first bit BIT and the first bit, which is an input or output of the static random access memory 100. BITB) and receive first and second precharge signals PCB1 and PCBB1 for respectively pulling up the first bit and the first bit bar BITB for reading. A second bit bar having an input or an output second bit and an inverted signal of the second bit for each of the static random access memory cells of the second bit. And third and fourth precharge signals PCB2 and PCBB2 for pulling up the second bit bar and the second bit bar for reading.

The test signal generation circuit 200 includes a precharge signal PC having a low logic value for a predetermined time, a first bit and a first bit bar to test whether the static random access memory cells are defective. When the first and MOS transistors MN1 and the second PMOS transistor MP2 are defective by receiving the BITB), the first test signal PCL and the presence or absence of the same test as the precharge signal PC are tested. A second test signal PCR having a low logic value is always output to the same, and when the first PMOS transistor MP1 or the second N-MOS transistor MN2 is defective, the same as the precharge signal PC. The first test signal PCL having a low logic value is always output when the second test signal PCR and the defect test are performed, and the first test signal PCL is the first of the static random access memory 100. The second frame is connected in common to the precharge signal PCB1 and the third precharge signal PCB2. Bit signal (PCR) is commonly connected to the second pre-charge signal (PCBB1) and the fourth pre-charge signal (PCBB2) of static random access memory (100).

FIG. 6 is another embodiment of a test circuit of the static random access memory of the present invention, wherein the static random access memory 100 has the same configuration as that of FIG. 1, and includes the first bit (i.e., an input or an output of the static random access memory 100). BIT) and a first bit bar (BITB) having an inverted signal of the first bit, wherein the first bit bar (BITB) and the first bit bar (BITB) are respectively pulled up for reading. 1, receiving the second precharge signals PCB1 and PCBB1 and having a second bit which is an input or an output for each of the static random access memory cells and an inverted signal of the second bit. Third and fourth precharge signals PCB2 and PCBB2 having a second bit bar for pulling up the second bit and the second bit bar for reading; Receive.

The test signal generation circuit 200 includes a precharge signal PC having a low logic value for a predetermined time, a first bit and a first bit bar to test whether the static random access memory cells are defective. When the first and MOS transistors MN1 and the second PMOS transistor MP2 are defective by receiving the BITB), the first test signal PCL and the presence or absence of the same test as the precharge signal PC are tested. A second test signal PCR having a low logic value is always output to the precharge signal PC when the first PMOS transistor MP1 or the second N-MOS transistor MN2 is defective. The first test signal PCL having the low logic value is always output when the same second test signal PCR and the defect test are performed, and the first test signal PCL is generated by the static random access memory 100. One precharge signal PCB1 is connected, and the second test signal PCR has a static random access. The second precharge signal PCBB1 of the memory 100 is connected, and the third precharge signal PCB2 and the fourth precharge signal PCBB2 are commonly connected to the precharge signal PC. .

7 is another embodiment of a test circuit of the static random access memory of the present invention, in which the static random access memory 100 has the same configuration as that of FIG. 1 and includes a first bit that is an input or output of the static random access memory 100. (BIT) and a first bit bar (BITB) having an inverted signal of the first bit, for pulling up the first bit (BIT) and the first bit bar (BITB) for reading, respectively. Receives the first and second precharge signals PCB1 and PCBB1, and outputs a second bit that is an input or an output and an inverted signal of the second bit, for each of the static random access memory cells. Third and fourth precharge signals (PCB2 and PCBB2) having a second bit bar having a second bit bar for pulling up the second bit and the second bit bar for reading, respectively; Receive

The test signal generation circuit 200 includes a precharge signal PC having a low logic value for a predetermined time, a first bit and a first bit bar to test whether the static random access memory cells are defective. When the first and MOS transistors MN1 and the second PMOS transistor MP2 are defective by receiving the BITB), the first test signal PCL and the presence or absence of the same test as the precharge signal PC are tested. A second test signal PCR having a low logic value is always output to the precharge signal PC when the first PMOS transistor MP1 or the second N-MOS transistor MN2 is defective. The first test signal PCL having the low logic value is always output when the same second test signal PCR and the defect test are performed, and the first test signal PCL is generated by the static random access memory 100. 3 is connected to the precharge signal PCB2, and the second test signal PCR is a static random access The fourth precharge signal PCBB2 of the memory 100 is connected, and the first precharge signal PCB1 and the second precharge signal PCBB1 are commonly connected to the precharge signal PC. .

8 is a test signal generation circuit of the static random access memory of the present invention, wherein the test signal generation circuit 200 includes a first negative logical means NAND1 having three inputs and a second negative logical means having two inputs ( NAND2), the first input of the first negative logical means (NAND1) is connected to the precharge signal PC, and the second input is connected to the output of the second negative logical means (NAND2). A first input of the two negative logical means NAND1 is connected to the first bit BIT, and a second input of the second negative logical means is connected to the output of the first negative logical means NAND1. A first latch means 210, a third negative logical means (NAND3) having three inputs, and a fourth negative logical means (NAND4) having two inputs, the first of the third negative logical means (NAND2) The input is connected to the precharge signal PC, the second input is connected to the output of the first negative logical means NAND1, and the third input is connected to the output of the fourth negative logical means NAND4. The first input of the fourth negative logical means NAND4 is connected to the first bit bar BITB, and the second input and the first negative logical means NAND1 of the fourth negative logical means NAND4 are connected to each other. The third input of the AND is logically multiplied by the output of the second latch means 220, the precharge signal PC and the first latch means 210 connected to the output of the third negative logical means NAND3, and the first test signal ( Second logical multiplication means AND2 for outputting the second test signal PCR by ANDing the output of the first logical multiplication means AND1 and the precharge signal PC and the second latch means 220 for outputting the PCL. And a test signal (TEST) indicating whether the test circuit of the static random access memory is defective or not, and logically combining the output of the test signal (TEST) and the first latching means (210) to perform the first logical multiplication means. The first logical sum means OR1 connected to one input of AND1 and the output of the test signal TEST and the second latch means 220 are connected to one input of the second logical multiplication means AND2. The second logical sum unit OR2 may be further provided.

The operation of the test circuit of the static random access memory of the present invention according to the above configuration will be described in detail.

In the case of a plurality of static random access memory cells of the static random access memory of FIG. 1 having cells of random access memory having a failure as shown in FIG. 3 or FIG. A high or low logical value is input to the first bit bar BITB, and the first bit bar BITB inputs inverted data of the first bit BIT to write a high or low logical value to the plurality of static random access memory cells. For example, when the second PMOS transistor MP2 of the second inverter I2 is defective or the first N-MOS transistor MN1 of the first inverter I1 is defective as illustrated in FIG. 3, the first bit BIT Input the high logic value to the first bit bar (BITB) and the low logic value to the first node (A) by the first address and the second address. On the contrary, when the first PMOS transistor MP1 of the first inverter I1 is defective or the second N-MOS transistor MN2 of the second inverter I2 is defective as shown in FIG. The low logic value is input to the bit BIT and the high logic value is input to the first bit bar BITB, and the high logic value is input to the first node A by the first address and the second address. Record the low logic value in.

FIG. 9 is a timing diagram of the static random access memory test circuit of the present invention having the cell 1 of the random access memory in which the failure of FIG. 3 occurs, in order to test the presence or absence of a plurality of static random access memory cells in the first node A. FIG. The low logic value is written to the second node B and the high logic value is recorded.

As shown in FIG. 9, the precharge signal PC, which is an input of the test signal generation circuit 200, has a low logic value at time t1 and a high logic value at time t2. The second address ADR_Y of the static random access memory inputs a high logic value and the first address ADR_X inputs the same signal as the precharge signal PC.

The test signal generation circuit 200 of the static random access memory of FIG. 8 receives the precharge signal PC, the first bit BIT, the first bit bar BITB, and the test signal TEST. Since the test signal TEST has a high logic value at time t1 when the signal PC has a low logic value, the first and second logical sum means OR1 and OR2 output high logic values. Since the first and second test signals PCL and PCR, which are outputs of the two logical means AND1 and AND2, become the same as the precharge signal PC, they have a low logic value. In the exemplary embodiment of the static random access memory test circuit of FIG. 5, the first test signal PCL is common to the first and third precharge signals PCB1 and PCB2 of the static random access memory 100. Since the second test signal PCR is connected to the second and fourth precharge signals PCBB1 and PCBB2 of the static random access memory 100 in common, the first address signal ADR_X is low at time t1. Since the first and second pass transistors PA1 and PA2 of the static random access memory cell are turned off because of the logic value, the first bit, the first bit bar, the second bit, and the second bit. The bitbars all have a high logic value, and the second node B, which is the output of the first node A and the second inverter I2, which is the output of the first inverter I1 of the static random access memory cell. Have high and low logic values, respectively, data written at the time of writing.

When the precharge signal PC and the first address ADR_X have a high logic value, the first and second pass transistors PA1 and PA2 of the cell of the random access memory where the failure of FIG. (BIT) and the second bit have the same high logic value as the second node (B), and the first bit bar (BITB) and the second bit bar (bitb) have the same row as the first node (A). Has a logical value.

Since the fourth negative logic unit NAND4 of the test signal generation circuit 200 has the high logic value by the first bit bar BITB having the low logic value, the output of the second latch circuit 220 is It changes from a high logic value to a low logic value and the output of the first latch circuit 210 has the same high logic value as the previous state. When the test signal TEST is activated, that is, has a low logic value, the second test signal PCR has a low logic value by the output of the second latch circuit 220 having a low logic value and the first test signal PCL. Has a high logic value.

Since the first and third precharge signals PCB1 and PCB2 of the static random access memory 100 have a high logic value, the second and fourth precharge signals PCBB1 and PCBB2 have a low logic value. The voltage of the first node A of the cell 1 of the random access memory in which the failure of FIG. 3 is generated depends on the size of the transistors of the first N-MOS transistor MN1 of the second pass transistor PA2 and the first inverter I1. When the voltage rises from the ground voltage Vss to a constant voltage and the voltage rises above the threshold voltage of the second N-MOS transistor MN2 of the second inverter I2, the second N-MOS transistor MN2 is turned on to be the first voltage. Since the voltage of the two nodes B is discharged through the second NMOS transistor MN2, the second node B is changed from a high logic value to a low logic value, thereby causing the first PMOS of the first inverter I1. The transistor MP1 is turned on so that the first node A has a high logic value and the input or input of the cell 1 of the random access memory in which the defect occurs. The second bit, the second bitbar, the output, the first bit and the first bitbar, the input or output of the random access memory, are inverted data of the data written at the time of writing. Will have

Therefore, in order to test the failure of the conventional static random access memory, it is necessary to wait until the second node B is discharged by the leakage current and changed to a different state from the recorded data during the data preservation time. (B) is discharged in a short time by the second N-MOS transistor MN2, so that the test time can be significantly shortened.

The operation is the same even when the static random access memory 100 has the cell 2 of the random access memory in which the failure of FIG. 4 occurs, but the failure has occurred only to write the data to the static random access memory cells before testing for the failure. Inverted data which is different from when the random access memory cell 1 is tested for defects is recorded.

The operation of the embodiments of the static random access memory test circuit of the present invention of FIG. 6 or 7 is the same as that of FIG. That is, the first test signal PCL, which is the output of the test signal generation circuit 200, may be connected to any one of the first or third precharge signals PCB1 and PCB2 of the static random access memory 100. Similarly, the second test signal PCR may be connected to any one of the second or fourth precharge signals PCBB1 and PCBB2 of the static random access memory 100.

Claims (5)

An input or output of a static random access memory having a plurality of static random access memory cells consisting of a first PMOS transistor, a first N-MOS transistor, a second P-MOS transistor, and a second N-MOS transistor for writing or reading data. A first bit bar having a first bit and an inverted signal of the first bit, and receiving first and second precharge signals for respectively pulling up the first bit and the first bit bar for reading; And a second bit bar having an inverted signal of the second bit and the second bit as an input or an output for each of the static random access memory cells, when reading the second bit and the second bit bar, respectively. In the test circuit of the static random access memory for receiving the third and fourth precharge signal for pulling up for the test to test the presence of the static random access memory cells defective Receiving a precharge signal having a low logic value for a predetermined time, the first bit and the first bit bar, and when the first and second picotransistors are defective, a first equal to the precharge signal; A second test signal having a low logic value is always output at the time of a test signal and a defect test, and a second test signal equal to the precharge signal when the first PMOS transistor or the second & MOS transistor is defective. A first test signal having a low logic value is always output during a defect test, wherein the first test signal is connected to the first precharge signal or the third precharge signal of the static random access memory, and the second test signal is output. The test signal includes a test signal generating means connected to the second precharge signal or the fourth precharge signal of the static random access memory. A. The test circuit of claim 1, wherein the test circuit of the static random access memory receives a precharge signal having a low logic value for a predetermined time, the first bit and the first bar, and receives the first and MOS transistors or the second pin. When the MOS transistor is defective, a first test signal identical to the precharge signal and a second test signal having a low logic value at the time of a defect test are always output, and the first PMOS transistor or the second & MOS transistor is outputted. Outputs a second test signal identical to the precharge signal when the defect is present and a first test signal having a low logic value at the time of a defect test; The first test signal is connected to the first precharge signal, the second test signal is connected to the second precharge signal, and the third and fourth precharge signals are the precharge signal. And a test signal generating means connected in common with the test circuit of the static random access memory. 2. The apparatus of claim 1, wherein the test signal generating means comprises a first negative logical means having three inputs and a second negative logical means having two inputs, wherein the first input of the first negative logical means comprises: Is connected to the precharge signal, a second input is connected to the output of the second negative logical means, a first input of the second negative logical means is connected to the first bit, The second input of the second negative logical means comprises: first latch means connected to the output of the first negative logical means; A third negative logical means having three inputs and a fourth negative logical means having two inputs, wherein the first input of the third negative logical means is connected to the precharge signal, and a second input Is connected to the output of the fourth negative logical means, the third input is connected to the output of the first negative logical means, and the first input of the fourth negative logical means is the first input. A second latch means connected to the bit bar, the second input of the fourth negative logical means and the third input of the first negative logical means being connected to the output of the third negative logical means; First logical multiplication means for outputting a first test signal by ANDing the precharge signal and the output of the first latch means; And second logical multiplication means for outputting a second test signal by ANDing the precharge signal and the output of the second latch means. The method of claim 3, wherein the test signal generating means receives a test signal for testing whether the static random access memory cells are defective or not and logically combines the test signal and the output of the first latch means. First logical sum means connected to one input of the first logical multiplication means; And second logical sum means connected to one input of the second logical multiplication means by logically combining the test signal and the output of the second latch means. The test circuit of claim 1, wherein the test circuit of the static random access memory receives a precharge signal having a low logic value for a predetermined time, the first bit and the first bit bar, and the first and second transistors or the second pin. When the MOS transistor is defective, a first test signal identical to the precharge signal and a second test signal having a low logic value at the time of a defect test are always output, and the first PMOS transistor or the second & MOS transistor is outputted. Outputs a second test signal identical to the precharge signal when the defect is present and a first test signal having a low logic value at the time of a defect test; The first test signal is connected to the third precharge signal, the second test signal is connected to the fourth precharge signal, and the first and second precharge signals are the precharge signal. A test circuit for a static random access memory, characterized in that connected in common to.