KR100200077B1 - Non-volatile semiconductor memory device and fabrication method of the same - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory device for securing a process margin for misalignment and a manufacturing method thereof, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of securing a process margin for misalignment A nonvolatile semiconductor memory device and a method of manufacturing the same. According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device for securing a process margin for misalignment, including a front surface of a plurality of bit line active regions separated by a plurality of device isolation oxide films, And a metal wiring formed through the bit line contact formed on the conductive layer.

Description

Nonvolatile semiconductor memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device for ensuring margins against misalignment and a manufacturing method thereof.

Electrically Erasable and Programmable Nonvolatile Semiconductor Memory Devices For example, the cell structure of a flash EEPROM is largely classified into a NOR type and a NAND type. The NOR type structure is disadvantageous in terms of high integration, , The NAND type structure is advantageous in high integration, but has a drawback in that the cell current is small and the speed is increased. 1, the string includes a first select transistor ST1, a second select transistor ST2 connected to a common source line to which the source is grounded, a source of the first select transistor ST1 And a plurality of floating gate type memory transistors M1Mn in which channels are connected in series between the drain of the second selection transistor ST2 and the drain of the second selection transistor ST2.

FIG. 2 is a view showing a layout of a nonvolatile semiconductor memory device implemented according to the prior art, and FIG. 3 is a process sectional view of the layout shown in FIG. 2 in various directions. 3A is a sectional view of the layout shown in FIG. 2 cut in the direction A to A ', FIG. 3B is a sectional view of the process cut in the direction B to B', and FIG. Fig.

2 and 3, impurity regions 302 and 307 doped with a high-concentration circular-shaped impurity in a semiconductor substrate or a well 301 are formed in channel regions 308 on the main surface of the semiconductor substrate 301, As shown in Fig. The impurity region 302 is a connection region connected to the bit line BL2 made of a metal such as aluminum through the connection opening CT and serves as a drain region of the first selection transistor ST1. The impurity regions 303 and 306 act as common source-drain regions of two adjacent transistors among the transistors ST1, M1Mn and ST2. On the channel regions of the first and second selection transistors ST1 and ST2, gate films of a solid solution metal silicide material such as tungsten silicide are formed through a gate insulating film.

Floating gates 311 of polycrystalline silicon material are formed on the channel regions of the memory transistors M1Mn through the gate insulating film 310, respectively. On the floating gates, control gates of the solid solution metal silicide material are formed through an interlayer insulating film, for example, an ONO insulating film. The gates of the first and second selection transistors ST1 and ST2 and the control gates of the memory transistors M1Mn are connected to the first and second selection lines SSL and GSL and the word lines WL1WLn, respectively.

On the other hand, as the sizes of the memory transistors, that is, the memory cells, are reduced, the dimension of each layer is reduced, and the resolution is increased according to the increase in equipment. However, it is difficult to secure a process margin. In addition, there is no difficulty in forming a fine pattern because there is no step coverage of a silicon substrate. However, in order to reduce a cell size by a sub-micron process, reduction of a contact size and ensuring a process margin It becomes important.

An object of the present invention is to provide a nonvolatile semiconductor memory device capable of securing a process margin for misalignment and a manufacturing method thereof.

It is another object of the present invention to provide a nonvolatile semiconductor memory device capable of improving the reliability of a chip and a method of manufacturing the same.

1 is an equivalent circuit diagram of a general NAND type nonvolatile semiconductor memory device.

2 is a layout of a NAND-type nonvolatile semiconductor memory device implemented according to a conventional technique.

3 is a process sectional view of the layout shown in Fig. 2 cut in various directions. Fig.

4 is a layout of a NAND-type nonvolatile semiconductor memory device implemented according to an embodiment of the present invention.

5 is a process sectional view of the layout shown in Fig. 4 cut in various directions. Fig.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

It should be noted that the same components and parts of the drawings denote the same reference numerals as far as possible.

FIG. 4A is an equivalent circuit diagram of a nonvolatile semiconductor memory device constructed according to an embodiment of the present invention, FIG. 5A is a sectional view of the layout shown in FIG. Sectional view taken along line B-B 'in FIG.

4 and FIG. 5, portions similar to those described in the related art will be omitted or briefly described, and the bit line contact, which is the core of the present invention, will be mainly described.

In the process of forming the device, a circular well and a well are formed on a semiconductor substrate 301, an active region is formed on a predetermined substrate 301, a gate oxide film is formed, A tunnel oxide film is formed by removing the mask layer PR by forming a polysilicon layer on the first gate electrode by wet etching, A bit line contact formation region is etched through a predetermined dry etching and wet etching using a poly gate separation mask in the direction of the word line, and a predetermined contact hole is formed in the bit line contact formation region Type impurity is implanted to form the high concentration impurity region 501, and then the mask layer is removed. Then, the first gate conductor 502 is further deposited to be a bit line contact The rest of the area on the semiconductor substrate except for the bit line contact region, and so as to directly contact with the major surface of the semiconductor substrate so that the immersion time 2 minutes and by a conductor of the same. After the above process is performed, ion implantation is performed to make the deposited polysilicon into a conductor, or doped with impurities and then formed through a predetermined photolithography process to form a floating gate. At this time, a first gate conductor is formed to form a pattern with a predetermined distance between the bit line and the bit line so as to surround a portion where the bit line contact is to be formed. By a conventional flash process such as a predetermined oxidation and CVD method, A second gate conductor for forming a word line is formed and a word line is formed through a predetermined photolithography process. At this time, a layout is formed so as to cover a portion where the bit line contact is to be formed. After the etching, As shown in FIG.

A conventional flash process is applied to the structure formed by the above process to perform a predetermined process of depositing an insulating film or oxidizing the word line, forming a portion to be a source / drain through ion implantation, or depositing an insulating material A contact hole is formed through a predetermined photolithography process for connecting the semiconductor substrate 301 and the bit line. At this time, a contact pattern is formed at a portion connected to the silicon and the first gate conductor through a predetermined process, and the insulating film is etched through predetermined dry and wet etching to deposit metal through the contact hole, Thereby completing the above-described manufacturing process.

The present invention relates to the contact structure of the bit line BL in the above process, and the conventional bit line is directly connected to the main surface of the semiconductor substrate 301 with a high melting point metal such as metal or polycide, In order to prevent this, the metal bit line and the semiconductor substrate (or the semiconductor substrate) may be damaged due to misalignment in the formation of the bit line contact, 301 are extended to the element isolation film 309, a process margin for misalignment can be ensured and the characteristics of the element can be improved.

As described above, the present invention has an advantage that a process margin for misalignment that can occur in a bit line contact can be secured. Further, the present invention has an advantage that the reliability of the chip can be improved.

Claims (6)

A nonvolatile semiconductor memory device for securing a process margin for misalignment, A conductive layer including a front surface of a plurality of bit line active regions separated by a plurality of element isolation oxide films and a part of the element isolation oxide film; And a metal line formed through the bit line contact formed on the conductive layer. A nonvolatile semiconductor memory device having a high concentration active regions formed on a semiconductor substrate, a plurality of element isolation oxide films for isolating the active regions, and bit line contacts formed on the activation regions, And a conductive layer formed between the bit line contacts and the activation regions, respectively. ≪ RTI ID = 0.0 > 31. < / RTI > A method of manufacturing a nonvolatile semiconductor memory device, comprising: Forming a device isolation film for isolating an active region formed on a semiconductor substrate or a well; Forming a tunnel oxide film through photolithography after forming a first insulating film on the active region; Forming a first conductive layer on the tunnel oxide layer and forming the first conductive layer over a predetermined region of the isolation layer also on an active region to form a bit line contact; Forming a second insulating layer on the remaining first conductive layer except a first conductive layer in which the bit line contact is formed, and forming a second conductive layer on the second insulating layer; Masking the second conductive layer to form a drain region and a source region which are high concentration impurity regions; Forming a contact on the first conductive layer to form the bit line contact after depositing a third insulating film on the entire surface of the resultant product; And forming a metal layer on the contact. ≪ Desc / Clms Page number 19 > 4. The method of claim 3, further comprising forming a high concentration impurity region on the active region where the bit line contact is formed. 5. The method of claim 4, wherein when the first insulating film is a gate oxide film, the second insulating film is an insulating film having an oxide film, an insulating film, and an oxide film sequentially deposited. 6. The method of claim 5, wherein the second conductive layer is a control gate when the first conductive layer is a floating gate.