KR100199315B1 - Multi-port random access memory - Google Patents

Abstract

The present invention relates to a multi-port RAM (random access memory) that enhances the shadow write test function.

m rows comprising n x n columns of RAM cells, each RAM cell having storage means for storing binary data, wherein each row of RAM cells are commonly coupled to each set of M data paths, where m, n and M are integers A multi-port random access memory, the multi-port random access memory comprising: access means for executing data access to the random access memory cell via the data path; And path selection means for determining a data path such that data access is enabled through the selected data path and data access is disabled through the unselected data path.

Description

Multi-Port Random Access Memory

The present invention relates to a multi-port RAM (random access memory) that enhances the shadow write test function.

RAM having at least one address port and having a memory element (core cell) is known. A 180-MHz 0.8-μm BiCMOS Modular Memory Family of DRAM ane Multoport SRAM, IEEE Journal of Solid-State Circuits, Vol, 28, NO. 3, March 1993, p. The document described at 222, at 227 shows various arrays of RAM memory elements.

For RAM, the problem is to develop a practical and non-forced way of detecting shorts between bit lines from different ports. B. Nadeau-Dostie et al. Serial Interfacing for Embedded-Memory Testing, IEEE Design Test of Computers, April 1990, p. The document described in 52 describes a built-in self test architecture and memory test.

Detection of shorts due to manufacturing defects between bit lines from different ports running parallel to each other over long distances (height of the memory array) is difficult due to the small differential signal swing used in high speed memory port architectures. Short between word lines from different ports is difficult to detect without a specific test algorithm. Such defects are passed through undetected by functional test means or conventional BIST during manufacturing testing, causing intermittent failures in the field. The shadow write method can be used to detect bit line and word line short faults between ports during BIST or functional testing.

It is an object of the present invention to provide an improved multi-port RAM.

According to one aspect of the invention, there are m rows of n rows of RAM cells each having storage means for storing binary data, each row of RAM cells being commonly coupled to each set of M data paths, m, n Multi-port random access memory (RAM) is provided in which, and M are integers. Multi-port RAM determines the data path such that access means for performing data access to the RAM cell via the data path, and data access is enabled over the selected data path and data access is disabled over the non-selected data path. It further includes a path selection means to.

In one example, the access means includes data read means for reading binary data stored in the storage means via the selected data path, wherein the binary data is differential or single-ended binary data. Binary data stored in the storage means is read through the selected data path, and data read through the unselected data path is disabled.

In another example, the access means includes (i) a data write for storing binary data in the storage means via a data path selected in the write mode and (ii) reading binary data stored in the storage means via a data path selected in the read mode; And lead means.

Binary data is differential or single-ended binary data. During the write mode, binary data is stored in the storage means via the selected data path, and data write through the unselected data path is disabled. During read mode, binary data is read from the storage means via the selected data path, and data read through the unselected data path is disabled.

Multi-port RAM port architecture with path selection means (shadow writes) is a practical and non-intrusive for detecting shorts between bit lines and word lines from different read-only, write-only, or read-write ports in multi-port RAM. To provide a way. This is an innovative test enhancement feature.

By application of the shadow light feature, bit line and word line defects between multi-port RAM ports can be detected during manufacturing test by standard single port test algorithms. This allows the integration of BIST for multi-port memory using the available BIST controller developed to test single port memory. The smallest modification to the BIST controller requires enabling the shadow light function and allowing the multi-port memory to be treated as multiple individual single port memories.

Figure 1 is a block diagram of a multi-port RAM.

FIG. 2 is a circuit diagram of an SRAM (Static Random Access Memory) cell included in the RAM shown in FIG.

3 is a detailed view of the latch shown in FIG.

4 is a diagram of a circuit providing shadow light to a memory row access and a bitline clamp.

5 is a block diagram of a three port RAM with one write port and two read ports in accordance with an embodiment of the invention.

6 is a circuit diagram of one embodiment of a RAM cell of a multi-port RAM with column selection means in accordance with the present invention.

7 is a circuit diagram of another embodiment of a RAM cell of a multi-port RAM with column selection means.

8 is a block diagram of a two port SRAM having two read-write ports.

9 is a circuit diagram of a shadow write application of differential binary data by differential lead-write bit lines.

10 is another circuit diagram of a shadow write application of differential binary data by a single-ended read-write bit line.

11 is a block diagram of a two port SRAM having two read-write ports.

12 is a circuit diagram of a shadow write application of single-ended binary data by a single-ended read-write bit line.

13 is a circuit diagram of another shadow light application of single-ended binary data by a single-ended read-write bit line.

14 is a block diagram of a three port SRAM with one write only port and two read only ports.

FIG. 15 is a circuit diagram of a shadow light application for a three port SRAM with one single-ended write-only port and two single-ended read-only ports.

FIG. 16 is a circuit diagram of another shadow light application for a three port SRAM with one single-ended write-only port and two single-ended read-only ports.

Explanation of symbols for main parts of the drawings

110: 5-port SRAM cell array 112: word line

114: bit line 116: lead port row decoder

118 read port control and column decoder 120 address predecoder

124: data output circuit 126: light port control circuit

128: Lightport Row Decoder and Shift Register

130: light port interface circuit 132: light clock line

Best Mode for Carrying Out the Invention Embodiments of the present invention will be described below with reference to the accompanying drawings.

I. 9-port memory

Figure 1 illustrates a multi-port RAM. The nine-port static random access memory (SRAM) is configured as a 384 byte memory storage with one 24 x 128 bit (16 byte) write port and eight 384 x 8 bit lead ports. This is realized as an array of 48 rows by 64 columns core cells. 128-bit writes are interleaved with 64-bits written to each of the two selected rows per write cycle to give a more optimal array aspect ratio.

Five-port RAM was designed with four fully differential read ports and a single-ended pseudo differential light port. Differential lead ports are chosen for improved performance with respect to more compact single-ended architectures. Indirect read-access architecture is used to eliminate the multi-port cell stability problem associated with multiple simultaneous accesses to the cell. The single-ended light schema combined with row interleaving functions as two light bit lines per column. Local bitline reversal schemes are used to provide pseudo differential write performance at the core-cell for equivalent differential write performance.

The multi-port RAM has a five port SRAM cell array 110 with one write port and four read ports. The cell array 110 is connected to the read word line 112 and the read bit line 114. Cell array 110 has RAM cells in m (= 48) rows and n (= 64) columns. The address identifying the RAM cell for data read in cell array 110 is determined by the X and Y address signals provided by read port row recorder 116 and read port control and column decoder 118 respectively. The address data is determined by the address signal appearing on the input bus 120. The address data is included in the address signal appearing on the input bus 120, and the address signal has X and Y address data. The address data is supplied to an address predecoder 122 which provides X and Y address data to the read port row recorder 116 and the read port control and column decoder 118 respectively. The data output circuit 124 is connected to the cell array 110 for data read. The multi-port RAM has a write port control circuit 126, a write port row decoder and shift register 128, and a write port interface circuit 130. The write port row decoder and shift register 128 are connected to the data output circuit 124 via the write clock line 132. The write port row recorder and shift register 128 and the write port interface circuit 130 are connected to the cell array 110 via the write word line 134 and the write bit line 136, respectively. The data write function is executed by the write port control circuit 126, the write port row decoder and the shift register 128, and the write port interface circuit 130.

9-point operation is obtained by time multiplexing four physical lead ports in the core array. Four full-lead accesses in the core array run on these ports in each clock cycle. Read data is retimed and latched on eight output ports to provide to the user on the rising edge of the system clock. All lead port inputs are provided on the 9-port interface at the same ramp clock edge and are internally pipelined for read access. Read operation is controlled by a self-timed clock generator that blocks each read cycle as soon as possible following data access to minimize power consumption. Self-timed operation provides nearly constant power consumption across all processing cases. Fully multiplexed read operation is initiated by one rising edge of the system clock, simplifying high level interfaces and minimizing clock duty-cycle requirements. See the name Multi-Port Random Acess Memory of the invention filed on July 26, 1996 by the same applicant.

Read memory maps are ordered to provide two independent data pages that are switched to short bit toggles. The write port data is physically mapped via the data register arrangement to match the read data map. No thermal decode is required at the light port. Since TSI applications require write addressing sequentially, an embedded write address counter is provided with page synchronization control to detect page switch events.

In addition, the memory is provided with an ultra low power, no power mode by internally gate all interface signals with clocks by a thrust cutoff signal, thereby eliminating any signal transitions in the memory while asserting power cutoff.

To facilitate the scan and BIST design methodology, the memory interface has a built-in scan chin for specific multi-port test modes that do address and data signal plus so-called shadow writing. Scan rows can be independently controlled to support most columns.

The shadow light mode is intended for short port-to-port detection by a combination assertion of test mode control signals [B. Nadeau-Dostie et al entitled Setial Interfacing tor Embedded-Memory Testing, IEEE Design Test if Computers, April 1990, p. 52].

The RAM cells of the multi-port SRAM core array shown in FIG. 2 are indirect data through one single-ended write-only port and gate bitline pull-down transistor with local bitline inversion to impart pseudo differential height access. It consists of four differential lead ports with access.

In the following description, for simplicity and for illustrative purposes only, it is assumed that the referring metal oxide semiconductor field effect transistor (FET MOSFET) and the supply voltage are + Vdd (e.g., 5.0 or 3.3 volts).

The RAM cell shown in FIG. 2 has a 5-port memory element, and has four differential list ports and one write port with indirect data access. The RAM cell has a latch (cell) 210 having two inverters 211 and 212. Each of the inverters 211 and 212 has a complementary metal oxide semiconductor (CMOS) inverter. The input and output terminals of the inverter 211 are connected to the output and input terminals of the inverter 212, respectively.

In Figure 2, all FETs are N-channel FETs. The source of FET 214 is connected to the drain of FET 216 and the source of FET 218 is connected to the drain of FET 220. Similarly, the source of FET 222 is connected to the drain of FET 224 and the source of FET 226 is connected to the drain of FET 228. The source of FFE 230 is connected to the drain of FET 232 and the source of EFT 234 is connected to the drain of FET 236. The source of FET 238 is connected to the drain of FET 240 and the source of FET 242 is connected to the drain of FET 224.

The output terminal of the inverter 211 and the input terminal of the inverter 212 are connected to the drain of the FET 246 and the gates of the FETs 216, 224, 232, and 240. The input terminal of the inverter 211 and the output terminal of the inverter 212 are connected to the drain of the FET 248 and the gate of the FETs 220, 228, 236, and 224, the source of which is the FET Is connected to the drain of 250. The sources of FETs 216, 220, 224, 228, 232, 236, 240, 244, and 250 are connected to ground terminals.

Gates of the FETs 246 and 248 are connected to a line 252 to which the write word line signal wlw is provided. The gate of FET 250 and the source of FET 246 are connected to line 254 where a write signal blw representing data 0 or 1 is provided.

The line 256 provided with the word line read signal wlra is connected to the gates of the FETs 214 and 218. The line 258 provided with the word line read signal wlrb is connected to the gates of the FETs 222 and 226. The line 260 provided with the word line read signal wlrc is connected to the gates of the FETs 230 and 234. Is connected to. A word line read signal wlrd is provided 262, which is connected to the gates of the FETs 238, 242.

The drains of the FETs 218, 226, 234, and 242 are connected to the lines 264, 266, 268, and 270 provided with the read bit line signals blra, blrb, blrc, and blrd. Each is connected. The drains of the FETs 214, 222, 230, and 238 are connected to the lines 272, 274, 276, and 278 provided with the read bit line signals blrna, blrnb, blrnc, and blrnd. Each is connected. Lines 264 and 272, 266 and 274, 268 and 276, 270 and 278 are bit line pairs, and in each pair, the lead bit line signals blra and blrna , blrb and blrnb, blrc and blrnc, blrd and blrnd are provided with differential signals.

3 illustrates in detail the latch 210 of a multi-port RAM core array. The latch 210 is a known RAM memory element having two CMOS inverters. In FIG. 3, the drain of the P-channel FET 280 (load device) and the N-channel (FET 282 (drive device)) defining one CMOS inverter is the P-channel FET 284 (defining another CMOS inverter). Load device) and the gate of the N-channel FET 286 (drive device). Likewise, the drains of the FETs 284 and 286 are connected to the gates of the FETs 280 and 282. And the source of 284 are connected to the voltage terminal of the power supply + Vdd. The sources of the FETs 282 and 286 are connected to the ground terminal, and the drain connection points of the FETs 280 and 282 are connected to the node CN. The drain connection points of FETs 284 and 286 define node C. Nodes CN and C are the data input and output terminals of latch 210.

4 shows a circuit for providing shadow light to memory column access and bit line clamps. This circuit has first to fourth circuits for the first to fourth ports a to d. In the first circuit of column a, the sources of the P-channel FETs 310 and 312 are connected to the power supply terminal 314 of constant voltage + Vdd. The sources of N-channel FETs 316 and 318 are connected to the ground terminal. The drains of FETs 310 and 316 are connected to the drains of P-channel FETs 320. The drains of FETs 312 and 318 are connected to the drains of P channel and 322, respectively. Line pairs 264, 272 provided with lead bit line signals blra and blrna are FETs 320 and 322. Are respectively connected to the drain. The sources of FETs 320 and 322 are connected to bus line pairs 324 and 326, respectively, to which a port data signals dba and dbna are provided. Gates of the FETs 320 and 322 are connected to a column access signal line 328 to which a port column access signal yia is provided. Similarly, in the second circuit in column b, the FETs 330 and 332 are connected to the power supply terminal 314. The sources of FETs 334 and 336 are connected to ground terminals. The drains of FETs 330 and 334 are connected to the drains of FET 338. The drains of FETs 332 and 336 are connected to the drains of FETs 340. Line pairs 266 and 274 provided with the read bit line signals blrb and blrnb are connected to the drains of the FETs 338 and 340, respectively. The sources of FETs 338 and 340 are connected to bus line pairs 342 and 344 where the b port data signals dbb and dbnb are provided. The gates of the FETs 338 and 340 are connected to the column access signal line 346 to which the b-port column access signal yib is supplied. In addition, the third and fourth circuits in the columns c and d are also similar to the first circuit.

In this example, there are two shadow light lines 390 and 392. Gates of FETs 310, 312, 316, and 318 of the first circuit and gates of FETs 350, 352, and 356 of the third circuit are provided by the shadow light a / c signal. Is connected to the shadow light line 390. The gates of FETs 330, 332, 334, and 336 of the second circuit and the gates of FETs 370, 372, 374, and 376 of the fourth circuit have different shadow lights b. / b signal is connected to the shadow light line 392 provided.

Two line pairs 264, 272 and 268, while the test pattern extends over the other two line pairs 266, 274 and 270, 278 to detect a read error, 276 may be driven to ground potential. Similarly, two line pairs 266, 274, and (while the test pattern extends over the other two line pairs 264, 272 and 268, 276 to detect read errors. 270 and 278 can be driven to ground potential. This mode includes bit line clamp devices: FETs 310, 312; 330, 332; 350, 352; By the specific control of 370 and 372, it is realized without an overhead threshold path.

Short detection due to manufacturing defects between bit lines from different ports running parallel to each other over long distances (height of the memory array) is difficult due to the small differential signal swing used in high speed read only memory port architectures. Such defects are passed through undetected during manufacturing testing and are the cause of intermittent defects in the field. The shadow light methodology can be used to detect bit line short faults between ports during BIST or functional testing.

Shadow light for multi-port lead-only architecture detects bit line short faults while driving standard test patterns on two ports while bit lines from other ports are driven to the Vss potential (0 volts) by the shadow light circuitry Used to Since the active bit line precharge level is approximately Vdd potential (3.3 volts), any short between the active bit line and the bit line (0 volts) of the shadow light causes a significant error voltage applied to the bit line, resulting in an invalid lead.

In normal read mode, FETs 310 and 312 limit the voltage swing of the bit line to less than 500 mV. When shadow light mode is enabled, two read port bit line pairs are connected to FETs 316, 318 and FETs 354, 356 (or FETs 334) while driving the other two bit line pairs of the test pattern. ), 336, and FETs 374, 376) are driven to the Vss potential and lead errors are detected. The shadow light a / c signal on the shadow light line 390 and the shadow light b / d signal on the shadow light line 392 select the columns for which the shadow light should be enabled.

In this example, two shadow light control signals are added to the memory control: enabling the shadow light mode and selecting the shadow light a / c and shadow light b / d signals. No other circuit is needed.

Latch 210 stores data 0 or 1. When the word line read signal wlra on line 256 is high, FETs 218 and 214 are gated. For zero data, the FETs 220 and 218 are turned on and the bit lines 264 are pulled down by the FETs 220 and 218, resulting in a low read bit line signal blra. FETs 216 and 214 are off and the lead bit line signal blrna on line 272 becomes high. Thus, data 0 is read.

For one data, the FETs 216 and 214 are turned on and the bit lines 272 are pulled down by the FETs 216 and 214, resulting in a low read bit line signal blran. FETs 220 and 218 are off and the read bit line signal blra on line 264 is high. Thus, data 1 is read.

When the shadow light a / c signal on the shadow light line 390 is low and the shadow light b / d signal on the shadow light line 392 is high, the FETs 334, 336 and the fourth circuit of the second circuit are high. FETs 374 and 376 are turned on, and two read port bit line pairs 266, 274 and 270 and 278 are driven to ground potential through the turned on FET. Thus, the data read through the bit lines 266 and 274 of the port b and the bit lines 270 and 278 of the port d is terminated. At the same time, the FETs 310, 312 of the first circuit and the FETs 350, 352 of the third circuit are turned on and the two read port bit line pairs 264, 272 and 268, 276 is enabled. Thus, while preventing the other bit lines of ports b and d from being tested, a test pattern travels over two bit line pairs 264, 272, 268, and 276 to detect a read error. While the a-port and c-port thermal access signals yia and yic are low, the test patterns traveling through the bitline pairs are connected to bus line pairs 324, 326 via FETs 320, 322, and 358, 360. ) And 362, 364.

Similarly, when the shadow light a / c signal on the shadow light line 390 is high and the shadow light b / d signal of the shadow light line 392 is low, the turned on FETs 316 and 318 and the third circuit of the first circuit are low. FETs 354 and 356 of the circuit, two lead port bit line pairs 264, 272 and 268, 276 are driven to ground potential. The test pattern travels on two bit line pairs 266, 274, 270, and 278 so that read errors are detected. The bus access pairs 342, 344, 382, and 384 are read through the column access signals yib and 378 and 380.

II. Shadow Light Applications of Differential Binary Data by Differential Read-Only Ports

A multi-port RAM according to one embodiment of the invention comprises m rows multiplied by n columns of RAM cells, each RAM cell having storage means for storing differential binary data.

The write and lead bit line signals are fully differential.

II-1.Structure

5 is a block diagram of a three-port RAM with one write only port and two read only ports. The RAM has a core cell array, row decode blocks, column access and data I / O blocks, and address and control blocks. The core cell array is composed of a cell array of m rows times n columns shown in FIG. Each cell has three ports (M = 3 in this example), and each port has a word line and a bit line. Cell access is achieved through the selection of the word line signal generated by the row decode block in accordance with the X address signal and the selection of the bit line pair by the column access block in accordance with the Y address signal.

Memory interfaces for asynchronous RAM implementations with dedicated read only and write only ports typically include an address bus, a memory select input and a data input bus or a data output bus per port. An asynchronous implementation typically has a clock input for each port. In this example, the asynchronous implementation is considered the full interface plus shadow light control interface as shown in FIG. For this case, the address and control block includes a circuit for enabling or disabling memory access, an interface register for all inputs, and a clock buffer, depending on the state of the select input. Non-selection of memory usually involves disabling row and column decode functions and possibly internal clock disabling to help reduce power consumption. Thermal access and data I / O blocks typically have thermal access and decode functions, data input registers, data write drivers, and data output sensing and buffer circuits.

The RAM cell shown in FIG. 6 has a three port memory element, and has one write port and two read ports with direct data access. The RAM cell has a data latch that stores differential binary data. The latch has two inverters 411 and 412 connected to nodes C and CN. The details of the latch are shown in FIG.

Node C of the latch is connected to the sources of N-channel FETs 414, 416, and 418. The drain of the FET 414 is connected to the line 420 to which the write bit line signal blw is provided. The drains of the FETs 416 and 418 are connected to the lines 422 and 424 provided with the a port and b port lead bit line signals bla and blb, respectively.

The node CN of the latch is connected to the drains of the N-channel FETs 426, 428, and 430. The source of FET 426 is connected to line 432 where the write bit line signal blnw is provided. The sources of FETs 428 and 430 are connected to lines 434 and 436 provided with the a port and b port lead bit line signals blna and blnb, respectively. Gates of the FETs 414 and 426 are connected to a line 438 to which the write word line signal wlw is provided. Gates of the FETs 416 and 428 are connected to a line 440 to which a port read word line signal wla is provided. Gates of the FETs 418 and 430 are connected to a line 422 to which the b-port lead word line signal wlb is provided. Lines 420 and 432, lines 422 and 434, and lines 424 and 436 are differential bit line pairs. The write bit line signals blw and blnw, the a port lead bit line signals bla and blna, and the b port lead bit line signals blb and blnb are differential.

Line 422 is connected to the drain of P-channel FET 444, N-channel FET 446, and P-channel FET 448. Line 434 is connected to the drains of P-channel FET 450, N-channel FET 452, and P-channel FET 454. The a-port shadow light enable signal swa is supplied to the gates of the FETs 444, 446, 450, and 452. The a-port column access signal yia is supplied to the gates of the FETs 448 and 454. Line 424 is connected to the drains of P-channel FET 456, N-channel 458, and P-channel FET 460. Line 436 is connected to the drains of P-channel FET 462, N-channel 464, and P-channel FET 466. The b-port shadow light enable signal swb is supplied to the gates of the FETs 456, 458, 462, and 464. The b-port column access signal yib is supplied to the gates of the FETs 460 and 466. The sources of the FETs 444, 450, 456, and 462 are connected to the power supply terminals of the constant voltage + Vdd. The sources of FETs 446, 452, 458, and 464 are connected to ground terminals. Sources of FETs 448, 454, 460, and 466 are connected to respective data bus lines. The a port differential read data signals dba and dbna are provided to the sources of FETs 448 and 454, respectively. The b-port differential read data signals dbb and dbnb are provided to the sources of FETs 460 and 466, respectively. FETs 444, 450, 456, and 462 are bit line clamp devices. FETs 446, 452, 458, and 464 are shadow light drivers. FETs 448, 454, 460, and 466 are thermal access devices. A port lead bit line different from the lines 422 and 434 is connected to the OR circuit 468. The b port lead bit line different from the lines 424 and 436 is connected to the OR circuit 470.

II-2 Behavior

In order to enable shadow light on port a, the port shadow light enable signal swa is set to high. To enable shadow light on port b. The b-port shadow light enable signal swb is set to high. Port a Port b Port Shadow Light Enable The shadow light is disabled when the signals swa and swb are both low (the normal mission mode is enabled). When shadow light on port a is enabled, lines 422 and 434 are driven to ground potential. A and b port bit lead shorts are detected.

Direct read access used in the RAM cell shows that the memory contents due to the write operation on the low read bit line signals bla and blna when the a port read word line signal wla is high while the a port is in the shadow write mode are detected. To avoid this, all a-port read word line signals must remain disabled. This can be accomplished by the non-selection of a port if the memory selection capability per port is available. Otherwise, shadow light control row decoder non-selection must be added to the memory control logic.

Inter-port word line shorts are detected by driving all word line signals on the port low during shadow write. Any word line short between line 440 (a port lead word line signal wla is held low) and line 442 (b port lead word line signal wlb is active) is connected to a port lead word line signal wla. Caused by the contamination of the cell accessed by. (The a port read bit line signals bla and blna are low when the a port read word line signal wla is active due to a short, so it is invalid light). The invalid read in the cell accessed by the b-port read word line signal wlb is caused by a read access delay defect due to the reduced voltage of the b-port read word line signal wlb due to a-port and b-port read word line shorts. At-speed testing, which is achievable or desirable self-timed memory operation, requires delay defect detection that leads to read errors.

If some port interaction is physically impossible, shadow light control may be added to each individual lead port by independent control or group control of each circuit (equivalent to a 9-port TSI SRAM).

Fabrication test application of the shadow light circuit can be accomplished by performing a logical OR of all lead bit line signals controlled by a given shadow light enable signal as shown in FIG. In this case, all of the a-port read bit line signals bla and blna share a common shadow write enable signal swa and are logically ORed by the OR circuit 468. Similarly, all the b-port read bit line signals blb and blnb are logically ORed by the OR circuit 470. In pregnant mode (when shadow light is not enabled), the output of the OR circuit 468 (a port test result signal swaq) is high since the active precharge level on all lead bit lines is high. When the shadow light is enabled, all lead bit line signals are low and the a-port test signal swaq is low. If any of the shadow light drivers (FETs 446 and 452) fail, the lead bit line signal remains high and the a-port test result signal swaq remains high. A complete static implementation of the logic OR results in all bits in the shadow light. Care must be taken to minimize the chance of undetected defects in the circuit implementation as it requires ensuring that the line is low, and such large, complex, and static logic functions are considerably slow. This is acceptable because the test algorithm requires many cycles to complete the time to verify the status of the output (swaq or swbq).

III. Other Shadow Light Applications of Differential Binary Data by Differential Read-Only Ports FIG. 7 illustrates a circuit of another shadow light implementation that has been slightly modified to improve manufacturing test coverage and does not require logic OR function circuitry. In this case, each shadow light control signal is divided into two such that a port shadow light enable signal swa0 and swa1 are given, for example. Full shadow light mode is enabled for port a when the a-port shadow light enable signals swa0 and swa1 are both high. Mission mode is enabled for port a when both the a-port shadow light enable signals swa0 and swa1 are low. Fabrication tests of the FETs 446 and 452 are enabled when either of the a-port shadow light enable signals swa0 and swa1 is high. The bport shadow light and bport shadow light driver are tested in the same way.

The fabrication test algorithm for detecting shadow light defects is as follows.

1) write 1 data in the even row of memory and 0 data in the odd row of memory, with shadow light disabled on each port (the shadow light enable signal on each port is low); When N is the number of memory ports, only 2 x N rows should be written [N x MUX cycles]; 2) enable a port shadow write enable signal swa0 to drive a port lead bit line signal bla low on all memory columns [1 cycle]; 3) enabling the a port read word line signal wla0 (a port word line in row 0); If the shadow light driver device of the a port lead bit line (e.g., the FET 446 of the line 422) is functional, drive each a port lead bit line of the signal bla of each column of the memory to low and state in step 1). Write all cells in row 0 that were initialized to zero in state 1 [1 cycle]; 4) disable the a port shadow write enable signal swa0 and the a port shadow write enable signal swa1 to drive the a port read bit line signal blna low in all memory columns [1 cycle]; 5) enabling the a-port read word line signal wla1 in row 1; If the shadow light driver device of the port lead bit line (e.g., FET 452 of line 434) is functional, writes all cells in row 1 from state 0 initialized in step 1 to state 1 (one cycle). ]; 6) repeat steps 2) to 5) for each port to enable the appropriate shadow light control signal to increase the row accessed in each case [(N-1) x 4 cycles]; 7) terminate the test by reading all memory locations that were accessed in the test; All even row positions have data 0 and the odd row positions have data 1; Any error indicates a fault in the shadow light circuit [n x MUX cycles].

This algorithm requires N x (4 + 2 x MUX) cycles, N is the number of ports, MUX is the column decode multiplex coefficient (MUX = c / d, c is the number of columns, and d is the data word width. )to be. When N is less than 10 and MUX is typically between 1 and 32, the worst case test impact is less than 100 cycles.

For the shadow light function to detect bit line shorts between ports, in the shadow light mode all word lines of the port must be disabled. But. In order for the shadow light manufacturing test shown in FIG. 7 to function, it is necessary to select the word line of the port in the shadow light mode. The simplest implementation of this feature is to have per-port memory selection useful for test controllers (BIST or functional testers) so that all ports except those under test are disabled. The shadow light control circuit is completely independent of the mission mode memory control. In addition, the shadow light control circuit may be used to disable the memory row decoder only when both of the port's shadow light control signals are enabled (e.g., the a-port shadow light enable signals swa0 and swa1 are both aggregated). The new shadow light control provides separate control of the shadow light control signals (a port shadow light enable signals swa0 and swa1) of each port or port group, plus an input for independently enabling the shadow light of each port (or port group). Require.

The main effect of this circuit is to simplify the manufacturing test algorithm as a whole. Due to the application of the shadow light circuit shown in FIG. 7, a very complex and configuration dependent test algorithm is simplified by SMARCH (B. Nadeau-Dostid at al entitled Serial Interfacing for Embedded-Memory Testing, IEEE Design Test of Computers, April 1990, pp. 52-63) or the non-serial MARCH algorithm. Each port is tested independently as if all other ports were independent memory when in shadow light mode. All inter-port bit line and word line faults are detected.

Ⅳ. Shadow Light Application of Differential Binary Data by Differential Read-Write Ports According to another embodiment of the present invention, a multi-port RAM includes m rows multiplied by n columns of RAM cells, and each RAM cell stores differential binary data. A storage means is provided. The write and lead bit line signals are fully differential.

IV-1. rescue

8 is a block diagram of a two-port RAM with two read-write ports. The RAM has a core cell array, row decode blocks, column access and data I / O blocks, and address and control blocks. The core cell array consists of a cell array of m rows multiplied by n columns shown in boxes in FIG. Each cell has two ports (M = 2 in this example), and each port has a word line and a bit line. Column access is achieved through selection of the word line signal generated by the row decode block in accordance with the X address signal and selection of the bit line by the column access block in accordance with the Y address signal.

Memory interfaces for asynchronous RAM implementations with read-write ports typically have an ad bus, memory select input, write enable input, data input bus and data output bus per port. The asynchronous implementation also has a clock input for each port. For this example, the asynchronous implementation is based on the complete interface plus shadow light control interface as shown in FIG. In this case, the address and control blocks are clock buffers, interface registers for all inputs, circuitry for selecting between read and write cycles depending on the state of the write enable input and memory access depending on the state of the select input or A circuit for disabling is usually provided. Non-selection of memory involves disabling row and column decode functions to help reduce power consumption and possibly internal clock disabling. Thermal access and data I / O blocks typically have thermal access and decode functions, data input registers, data write drivers enabled during write cycles, and data output sense and buffer circuitry.

The RAM cell shown in FIG. 9 has two read-write ports with two-port memory elements and direct data access. The RAM cell has a data latch with two inverters 511 and 512. The input of the inverter 511 and the output terminal of the inverter 512 are connected to the node C of the latch. The output of the inverter 511 and the input terminal of the inverter 512 are connected to the node CN of the latch. The details of the latch are shown in FIG.

Node C is connected to the sources of N channel FETs 514 and 516, the drain of which is connected to lines 518 and 520, respectively. The a port and b port bit line signals bla and blb are provided on lines 518 and 520, respectively. Node CN is connected to the drains of N-channel FETs 522 and 524 and its source is connected to lines 526 and 528, respectively. The a port and b port bit line signals blna and blnb are provided on lines 526 and 528, respectively. Lines 518 and 526 and lines 520 and 528 are differential bit line pairs. The a-port bit line signals bla and blna and the b-port bit line signals blb and blnb are differential signal pairs.

Gates of the FETs 514 and 522 are connected to a line 530 to which a port word line signal wla is provided. The gates of FETs 516 and 524 are connected to line 532 where the b-port word line signal wlb is provided.

Line 518 is connected to the drains of P-channel FETs 534 and 536. Line 526 is connected to the drain of P-channel FET 538 and the source of FET 536. The gates of FETs 534, 536, and 538 are supplied to the gates of FETs 542 and 544 with the a-port column access signal yia and the a-port shadow light enable signal swa at its input terminals. Lines 518 and 526 are connected to the drains of N-channel FETs 542 and 544, respectively. The a-port shadow light enable signal swa is supplied to the gates of the FETs 542 and 544. Lines 518 and 526 are connected to transmission gates 546 and 548, respectively, connected to the data bus. The a-port column access signal yia is supplied to positive input terminals of the transmission gates 546 and 548.

Line 520 is connected to the drains of P-channel FETs 550 and 552. Line 528 is connected to the drain of P channel FET 554 and the source of FET 552. The gates of FETs 550, 552, and 554 are connected to OR gate 556 to which the b port column access signal yib and the b port shadow light enable signal swb are supplied to the input terminals. Lines 520 and 528 are connected to the drains of N-channel FETs 558 and 560, respectively. The b-port shadow light enable signal swb is supplied to the gates of the FETs 558 and 560. Lines 520 and 528 are connected to transmission gates 562 and 564 respectively connected to the data bus. . The b-port column access signal yib is connected to the sub-input terminals of the transfer gates 562 and 564. The b-port column access signal yinb is connected to the transfer gates 562 and 564, respectively. The sources of FETs 534, 538, 550, and 554 are connected to power supply terminals of constant voltage + Vdd. The sources of FETs 542, 544, 588, and 560 are connected to ground terminals. FETs 534, 536, 538, 550, 552, and 554 are bit line precharge devices. OR gates 540 and 556 provide precharge disable functionality. FETs 542, 544, 558, and 560 are shadow light driver devices. Transmission gates 546, 548, 562, and 564 are port column access devices.

Port thermal access signals yia / yina and yib / yinb are differential. When the a-port column access signals yia and yina are high and low, respectively, the transmission gates 546 and 548 are turned on so that the a-port data signals dba and dbna pass through the transmission gates 546 and 548, respectively, The data bus is fed into lines 518 and 526 when in write mode and in lines 518 and 516 when in read mode. Similarly, when the b-port column access signals yib and uinb are high and low, respectively, the transfer gates 526 and 564 are turned on, so that when the b-port data signals dbb and dbnb are in write mode, the lines 520 and 528 and when in read mode, are fed to the data bus at lines 520 and 528. The a-port data signals dba and dbnb and the b-port data signals dbb and dbnb are differential.

IV-2. action

To enable shadow light on port a, the port aport shadow light enable signal swa is set to high. To enable shadow light of port b, the port b light shadow enable signal swb is set to high. shadow port is disabled (normal mission mode is enabled) when both a-port and b-port shadow light enable signals swa and swb are low. With shadow light enabled at a fore, precharge is disabled and the a-port bit line signals bla and blna are driven to ground potential so that a bit line short between a and b ports is sensed.

According to the direct access used in the RAM cell, in the shadow write mode, all the word line signals of the port are low bit line signals (e.g., a port when the word line signal (e.g. a port word line signal wla) is high. It should be disabled (keep low) to avoid memory content conflicts due to write operations on the bit line signals bla and blna). This can be achieved by deselecting the ports at the time of shadow write if the memory selection capability per port is available. Otherwise, shadow light control row decoder non-selection must be added to the memory control logic.

Inter-port word line shorts are detected by driving all word line signals at the port low during shadow write. Any word line short between line 530 and line 532 causes fouling of the cell accessed by the a-port word line signal wla (inner shorted when a-port word line signal wla is active) b port bit line signals bla and blna are both low and therefore invalid.) The invalid read from the cell accessed by the b-port word line signal wlb is due to the read access delay defect due to the reduced voltage of the b-port word line signal wlb due to the word line short between the a-port and b-port. Fast testing or self-timed memory operations require the detection of delay defects that introduce read errors.

Shadow light control must be added to each individual lead port as independent control or group control of each circuit (equivalent to a 9-port TSI SRAM) if some port interaction is physically impossible.

The manufacturing test of the shadow light function may be accomplished through the test pattern described with respect to FIG. 7, with a slightly altered implementation or by the logical OR function as in FIG. 6 if FIG. 9 is more closely related to the shadow light function of FIG. 7. Can be. This is explained next (section V).

The performance effect of this implementation is slightly greater than the shadow light implementation described in connection with FIGS. 4, 6, and 7. In this case, the critical path interactions are shadow light drivers (FETs 542, 544, 558 and 560), bit line precharge disable OR function circuits [OR gates 540 and 556]. And precharge devices (FETs 534, 536, 538, 550, 552, and 554).

Ⅴ. Different shadow light applications of differential binary data by differential lead-light ports.

FIG. 10 illustrates a circuit of another shadow light implementation that has been slightly modified to improve manufacturing test coverage. In this case, each shadow light control signal is divided into two to give a port shadow light enable signal swa0 and swa1, for example. Full shadow light mode is enabled on port a when the a-port shadow light enable signals swa0 and swa1 are both high. Pregnancy mode is enabled on port a when both the port shadow light enable signals swa0 and swa1 are low. The fabrication test of FETs 542 and 544 is enabled when either one of the a-port shadow light enable signals swa0 and swa1 is high. The manufacturing test for detecting shadow light defects is the same as described in connection with the implementation shown in FIG.

The main effect of this shadow light implementation is to simplify the manufacturing test algorithm as a whole. By application of the shadow light circuit shown in FIG. 9 or FIG. 10, a very complicated and configuration dependent test algorithm can be replaced with a simple MARCH type algorithm. Each port is tested independently as if it were independent memory when all other ports were in shadow light mode. Thus, all inter-port bit line and word line defects are detected. B. Nadear-Dostie et al Serial Interfacing for Embeded-Memory Testing at pp. The original shadow light concept disclosed in 60-61 discloses a method of using the built-in light capabilities of a lead-light port in shadow light mode for inter-port fault detection. The effects of the new proposal are compressed in three ways: 1) The new shadow light is global, and all bit lines of the port when shadowed are driven to ground, so that the new shadow light passes the test algorithm only once for the port under test. You can do it; The original implementation required both phases of the data driven on the bit line of the shadow light port to detect all port-to-port shorts, and 2) the critical path interaction of the shadow light implementation disables the word line of the port when shadow light. It is much lower than the original implementation, assuming memory per port selection is available. 3) The shadow light implementation is testable, i.e., the logical OR function or shadow light test algorithm allows the shadow light function to be verified.

Ⅵ. Shadow-Light Applications of Single-Ended Binary Data with Single-Ended Lead-Write Bitlines

A multi-port RAM according to another embodiment of the present invention comprises RAM cells of m rows times n columns, each RAM cell having storage means for storing single-ended binary data.

The write and read bit line signals are single-ended.

Figure 11 shows a block diagram of a two port RAM with two read-write ports.

The RAM has a co-cell array, row decode blocks, column access and data I / O blocks, and address and control blocks. The nose cell array consists of a cell array of m rows times n columns shown in the box of FIG. Each cell has two ports (M = 2 in this example) and each port word line and bit line. Cell access is achieved through selection of the word line signal generated by the row decode block in accordance with the X address signal and selection of the bit line by the column access block in accordance with the Y address signal.

Memory interfaces for asynchronous RAM implementations with read-write ports typically have an address bus, memory select input, write enable input, data input bus, and data output bus per port. The asynchronous implementation also has a clock input for each port. For this example, the asynchronous implementation is based on the full interface plus shadow light control interface as shown in FIG. In this case, the address and control blocks enable or disable memory access depending on the clock buffer, the interface registers for all inputs, the circuit that selects between read and write cycles depending on the state of the write enable input, and the state of the select input. The circuit which enables is normally provided. Non-selection of memory involves disabling row and column decode functions to help reduce power consumption and possibly internal clock disabling. The column access and data I / O blocks typically have a column access and decode function data input register, a data write driver and a data output sense and buffer circuit that are enabled during write cycles.

Ⅵ-1. rescue

FIG. 12 shows an implementation of the shadow light circuit used in a conventional two port SRM with a single-ended lead-light port. The illustrated two-port RAM cell is representative of this kind of memory with one NMOS access per port (word line access device connects bit lines directly to nodes C and CN of the latch). The latch has inverters 611 and 612. The details of the latch are shown in FIG.

In FIG. 12, node C is connected to the source of N-channel FET 614 whose drain is connected to line 616. In FIG. The a port bit line signal bla is provided to line 616. The gate of the FET 614 is connected to the line 618 to which the a-port word line signal wla is provided. Node CN is connected to the drain of N-channel FET 620 whose source is connected to line 622. The b-port bit line signal blnb (inverted signal) is provided to line 622. The gate of FET 620 is connected to line 624 where the b-port word line signal wlb is provided. Line 616 is connected to the drain of N-channel FET 626, P-channel FET 628, and N-channel FET 630. The gates of the FETs 628 and 630 are connected to the output terminals of the OR gate 632 to which the a-port shadow light enable signal swa and the b-port column select signal yia are supplied. Line 622 is connected to the drain of N-channel FET 634, P-channel FET 636, and N-channel FET 638. The a-port and b-port shadow light enable signals swa and swb are supplied to the gates of FETs 626 and 634, respectively. Gates of FETs 636 and 638 are connected to the output terminals of OR gate 640 to which the b port shadow light enable signal swb and the b port column select signal yib are supplied. The sources of FETs 630 and 638 are connected to the data bus. The sources of FETs 626 and 634 are connected to ground terminals. Sources of FETs 628 and 636 are connected to precharge line 642. FETs 626 and 634 are shadow light driver devices. FETs 628 and 636 are bit line precharge devices. FETs 630 and 638 are thermal access devices.

Ⅵ-2. action

The normal read or write driver (mission mode read or write) is executed when the shadow write mode is disabled, i.e., when the a-port and b-port shadow light enable signals swa and swb are both low. The read cycle is a bit line signal (e.g., at the precharge voltage potential Vblp as defined by active FETs 628 and 636 since both the a-port shadow light enable signal swa and the a-port column select signal yia are low. , bla) to start the access. The voltage generator for the precharge voltage potential is not shown. The precharge voltage is usually defined as Vdd / 2 to allow cell access without overwriting the cell contents. The cell selection is made by operating the word line signal wla and the column selection signal yia. This disables bit line precharge and allows the cell to drive the bit line hinges high or low. Since the column access device (FET 630 or 638) passes the read data through the data bus to the output, the a port data signal dba or the b port data signal dbb is provided. After the access ends, word line and column access are disabled and bit line precharge is enabled to prepare for the next access. The write cycle is the same as the data being provided to the bit line via the column access device (FET 630 or 638) during cell selection. The cell contents are overwritten by setting the bit line signal (e.g., a port bit line signal bla) high or low while the word line signal (e.g., a port word line signal wla) is active.

The shadow light is enabled for the port by setting the corresponding shadow eye enable signal swa or swb to high. A port bit line signal bla is driven low by the shadow light driver FET 626 gated by the shadow light enabled at port a. A bit line short is detected between the port under test (e.g., port b) and a port (e.g., a port) in which the shadow light mode is enabled. If high data is expected at line 622 (port to be tested) of b port bit line signal blnb and a short is present with respect to a port bit line 616 (port of shadow light) of a port bit line signal bla, The voltage driven by the write driver FET 626 on the a-port bit line 616 becomes an invalid lead on the low-falling line 622.

According to the direct access used in the RAM cell, all the word line signals of the port during shadow write are the low bit lines of the shadow light when the word line signal (e.g. a port word line signal wla) is high (e.g., a port). Should be disabled (keep low) to avoid memory content conflicts due to write operations on line 618 of bit line signal bla. This may be achieved by non-selection of the port of the shadow light if the memory selection capability per port is available as shown in FIG. Otherwise, shadow light control row decoder non-selection must be added to the memory control logic.

Inter-port word line shorts are detected by driving all word line signals wla and wlb at the shadower's fortress low. Any word line short between the line 618 (a port word line signal wla is kept low) and the line 624 (b port word line signal wlb is active) causes a collision of the cell accessed by wla. (Writes zero because the a-port word line signal wla is active and the a-port bit line signal bla is low due to a short). The invalid read in the cell accessed by the b-port word line signal wlb is due to a read access delay defect due to the reduced voltage of the signal wwl due to the short of lines 618 and 624. Fast testing or self-timed memory operation is required to detect delay defects induced by read errors.

If some port interaction is physically impossible, shadow light control must be added to each individual lead port as independent control or group control for each circuit. The selection of the shadow light source potential (the voltage at which the shadow light driver makes the bit line shadow light) need not be grounded as in this case. Any known potential is sufficient to detect the defect. For example, in this example, the Vdd potential applied to the bit line of the shadow light by the shadow light driver is used.

Fabrication test application of the shadow light circuit can be accomplished by observing the data read at the port in the shadow light mode. Since all bit line signals of the port at the time of shadow writing are driven low, the expected data for the data output is all low (when the bit line polarity is the same as the data output polarity as shown in FIG. 12 for the port a).

If the shadow light port data cannot be read, the logic OR test function circuit of all bit lines of the shadow light can be used as shown in FIG. In FIG. 13, the line 616 and the other a port bit line are connected to the OR circuit 650. In FIG. Line 622 and the other b-port bit line are connected to OR circuit 652. The a-port and b-port test result signals are provided by OR circuits 650 and 652, respectively, as described in connection with FIG. do.

The main effect of this shadow light implementation is the overall simplification of the manufacturing test algorithm for testing multi-port memory. By the application of the shadow light circuit shown in FIG. 12, a very complicated and configuration dependent test algorithm can be replaced with a simple MARCH type algorithm. Each port is tested independently as if all other ports were in write mode, as if they were a single port memory. All inter-port bit line and word line defects are detected in addition to the defect types normally detected by the selected algorithm. Only the BIST circuit overhead incurred beyond the standard single-port BIST is added to the port selection circuit, which enables shadow light enable and port non-selection of the port of the shadow light and the shadow light manufacturing test circuit to test the shadow light circuit. It is provided.

3 Port SRAM Shadow Light Applications with One Single-Ended Light-Only Port and Two Single-Ended Read-Only Ports

14 shows a block diagram of a three port RAM with one write only port and two read only ports. The RAM has a core cell array, row decode block, column access and data I / O blocks, and address and control blocks. The core cell array is composed of a cell array of m rows times n columns shown in the box of FIG. Each cell has three ports (M = 3 in this example), where the port is a word line signal (a port read word line signal wla, b port read word line signal wlb or write word line signal wlw) and a bit line signal. (a port lead bit line signal bla, b port lead bit line signal blb or write bit line signal blw). Cell access is achieved through selection of the word line signal generated by the row decode block in accordance with the X address signal and bit line selection by the column access block in accordance with the Y address signal.

Memory interfaces for asynchronous RAM implementations with dedicated read-only and write-only ports have a conventional address bus, memory select input and data input bus or data output bus per port. Asynchronous implementations typically also have a clock input for each port. For this example, the asynchronous implementation is considered a shadow light control interface as shown in the full interface plus FIG. For this case, the address and control block typically includes circuitry for enabling or disabling memory access, interface registers for all inputs, and clock buffers, depending on the state of the select input. Non-selection of memory typically involves disabling row and column decode functionality and possibly internal clock disabling to help reduce power consumption. Thermal access and data I / O blocks typically have thermal access and decode functions, data input registers, data write drivers, and data output sense and buffer circuits.

FIG. 15 shows an implementation of the shadow light feature for a three port RAM with one single-ended write only port and two single-ended read only ports. The 3-port RAM cell shown is typically a memory type with a series of NMOS write access and buffered read-only ports (lead bit lines do not directly access node C or CN of the latch, but are buffered by the inverter). The latch has two inverters 711 and 712 connected to its nodes C and CN. The details of the latch are shown in FIG.

In FIG. 15, node C is connected to the source of N-channel FET 714 whose drain is connected to the source of N-channel FET 716. In FIG. The drain of the FET 716 is connected to the line 718 provided with the write bit line signal blw. The gates of FETs 714 and 716 are connected to lines 720 and 722 provided with the w port column select signal yiw and the write word line signal wlw, respectively. The node CN is connected to the input terminal of the inverter 724 whose output terminal is connected to the drains of the N-channel FETs 726 and 728. The sources of FETs 726 and 728 are connected to lines 730 and 732 provided with a and b port lead bit line signals bla and blb, respectively. Gates of FETs 726 and 728 are connected to lines 734 and 736 provided with a-port and b-port read word line signals wla and wlb, respectively. Line 730 is connected to the drains of N-channel FETs 738 and 740. Line 732 is connected to the grains of N-channel FETs 742 and 744. The output terminal of the NOR gate 746 is connected to the line 718. The w port shadow light enable signal sww and the w port light data entering signal dw are supplied to the non-inverting and d inverting input terminals of the NOR gate 746, respectively.

The a and b port shadow light enable signals swa and swb are supplied to the gates of FETs 738 and 742, respectively. The a and b port column select signals yia and yib are supplied to the gates of the FETs 740 and 744, respectively. Sources of FETs 740 and 744 are connected to the data bus.

FETs 738 and 742 are read port shadow light drivers. FETs 740 and 744 are thermal access devices.

Normal read and write operations (mission mode lead or light) are executed when shadow light mode is disabled, a port shadow light enable signal swa, b port shadow light enable signal swb and w port shadow lin enable signal sww is me. The read cycle is executed by operating a word line signal (e.g. wla) and a column select line signal (e.g. yia). This causes the cell to drive the bit line in a high or low state. The thermal access device delivers read data through the data bus to the data output. The a port read data signal dba or the b port read data signal dbb is provided through the FET 740 or 744. Write is achieved by driving write data on for the write bit line signal blw during the cell selection (the write word line signal wlw and the w port column select signal yiw are high). While the write word line signal wlw and the port shadow column select signal yia are active, the cell contents are overwritten by turning the write bit line signal blw high or low.

The shadow light is enabled for the read only port (eg a port) by setting the shadow light control signal (eg, a port shadow light enable signal swa) to high. Due to the shadow light enabled for the a port, the a port lead bit line signal bla is driven low. A bit line short is detected between a port (e.g., a port) with shadow light mode enabled and a port under test (e.g., port b). If high data is expected for line 732 (port to be tested) and a short is present at line 730 (port of shadow light), a port lead bit line signal bla by the shadow light driver [FET 738] bla The voltage driven at causes the invalid read for the line 732 of the b-port riddle bit line signal blb falling low.

All word lines of the port in shadow light mode must be disabled to avoid unnecessary power consumption when the cell storing 1 data is accessed by the word line of the port of shadow light. This allows a port in shadow light mode to be achieved by non-selection if the memory selection capability per port is available. Otherwise, shadow light control row decoder non-selection must be added to the memory control logic.

The shadow light is enabled for the light dedicated port (w port) by setting the w port shadow light enable signal sww to high. With shadow light enabled for the w port, the write bit line signal blw is driven low to sense a short to the bit line at any other port. Like the read only port, the write only port row decode must be disabled to avoid contention of memory cell contents while the write port is shadow write code. In this example, the w port column select signal yiw runs parallel to the bit line and is tested as if it were a bit line, so it is driven by the shadow light word (low).

By driving all of the word line signals low relative to the shadow light port (lead or light port), a substantial low speed is achieved by reduced lead word line driving due to shorting of any word line short between the port of the shadow light and the port under test. This may cause a read operation. These delay defects can be detected by running a fast or self-timed test on the memory.

If some port interaction is physically impossible, shadow light control must be added to each individual lead port as independent control or group control for each circuit. The selection of the shadow light source potential (the voltage at which the shadow light driver makes the bit line shadow light) does not need to be grounded as in this case. Any known potential to detect a defect is sufficient. For example, in this example, the Vdd potential applied to the bit line of the shadow light by the PMOS shadow light driver is used.

Manufacturing test applications of lead only shadow light circuits can be achieved by observing data read at the lead only port during shadow light. In this example, the expected data is all low (when the bit line polarity is the same as the data output polarity) because all the bit line signals of the shadow light port are driven. If the shadow write port data cannot be read, the logical OR test function circuit of all the bit lines in the shadow write mode can be used as shown in FIG.

In FIG. 16, the line 730 and the other a port bit line are connected to the OR circuit 750. In FIG. Line 732 and the other b-port bit line are connected to OR circuit 752. The a port and b port test result signals are provided by the OR circuits 750 and 752, respectively, as described with reference to FIG.

The main effect of this shadow light invention is to simplify the manufacturing test algorithms for testing multi-port memory as a whole. By application of the shadow light circuit shown in FIG. 15 or FIG. 16, a very complicated and configuration dependent test algorithm can be replaced with a simple MARCH type algorithm. All inter-port bit line and word line defects are detected in addition to the defect types detected by the selected algorithm. Only the BIST circuit overhead incurred beyond the standard BIST is added to the port select and lead / light port circuits, which test the shadow light circuits as described above and the shadow light enable and port non-select functions for the ports of the shadow lights. And a shadow light manufacturing test circuit.

The feature of this embodiment is that it can be standardized. Although specific examples have been described, the shadow light feature can be applied to any multi-port memory having any combination of single-ended read only, write only or read-write ports. The single-ended shadow light feature is used in conjunction with the differential port shadow light feature to detect bit line and word line shorts between ports in a multi-port RAM having any combination of differential read only, write only or read-write ports.

This feature is not limited to SRAM applications. This can be used for any multi-port static memory architecture or multi-port dynamic memory architecture.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary.

Claims (19)

m rows comprising n x n columns of RAM cells, each RAM cell having storage means for storing binary data, wherein each row of RAM cells are commonly coupled to each set of M data paths, where m, n and M are integers A multi-port random access memory, the multi-port random access memory comprising: access means for executing data access to the random access memory cell via the data path; And path selection means for determining a data path such that data access is enabled through the selected data path and data access is disabled through the unselected data path. 2. The multi-port random access memory according to claim 1, wherein the access means includes data read means for reading binary data stored in the storage means through a selected data path in a read mode. 2. The access means according to claim 1, wherein the access means stores a binary data in the storage means via a data path selected in a write mode, and b) reads binary data stored in the storage means through a selected data path in a read mode. And a data write and read means for the data. 2. The multi-port random access memory of claim 1 wherein the path selection means comprises n sets of M switching means coupled to each M data path. 5. The multi-port random access memory according to claim 4, wherein each of the M switching means sets each data path to a predetermined voltage level when the switching means is operated. 6. The apparatus of claim 5, wherein the multi-port random access memory further comprises actuating means for selectively actuating selected ones of the M switching means in response to a control signal such that the data path is set to a predetermined voltage level. Multi-port random access memory. 7. The apparatus of claim 6, wherein each of the switching means comprises a field effect transistor (FET) having a drain-source coupled between the respective data path and a predetermined voltage level terminal, wherein the control signal is selective to the gate of the FET. Multi-port random access memory, characterized in that applied to. 7. The multi-port random access of claim 6, wherein said actuating means comprises means for alternately applying said control signal to each of two or more groups constituting one set of said M switching means. Memory. 2. The apparatus of claim 1, wherein the binary data is differential binary data, each of the data paths comprising a pair of differential bit lines, the path selection means comprising n sets of M switching means, each of the switching means being Multi-port random access memory, each connected to a pair of differential bit lines. 2. The apparatus of claim 1, wherein the binary data is single-ended binary data, each of the data paths comprising a single-ended bit line, the path selection means being n sets of M switching means. Wherein each of the switching means is connected to a respective single-ended bit line. 3. The multi-port random access memory according to claim 2, wherein the multi-port random access memory further comprises test function means for determining whether the binary data read from the storage means is the desired data. 12. The multi-port random access memory of claim 11 wherein the binary data is differential binary data. 12. The multi-port random access memory of claim 11 wherein the binary data is single-ended binary data. 4. The multi-port random access memory according to claim 3, wherein the multi-port random access memory further comprises test function means for determining whether the binary data read from the storage means is the desired data. 15. The multi-port random access memory of claim 14 wherein the binary data is differential binary data. 15. The multi-port random access memory of claim 14 wherein the binary data is single-ended binary data. 2. The multi-port random access memory of claim 1 wherein the random access memory cell is a dynamic random access memory cell. 2. The multi-port random access memory of claim 1 wherein the random access memory cell is a static random access memory cell. 15. The multi-port random access memory of claim 11 or 14, wherein the test function means comprises an OR function circuit for receiving data at each port of each random access memory cell, respectively.