CA2180421A1 - Multi-port random access memory - Google Patents

Multi-port random access memory

Info

Publication number
CA2180421A1
CA2180421A1 CA002180421A CA2180421A CA2180421A1 CA 2180421 A1 CA2180421 A1 CA 2180421A1 CA 002180421 A CA002180421 A CA 002180421A CA 2180421 A CA2180421 A CA 2180421A CA 2180421 A1 CA2180421 A1 CA 2180421A1
Authority
CA
Canada
Prior art keywords
port
random access
access memory
ram
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002180421A
Other languages
French (fr)
Other versions
CA2180421C (en
Inventor
Steven William Wood
Garnet Frederick Randall Gibson
Robert George Gibbins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Priority to DE69623707T priority Critical patent/DE69623707T2/en
Priority to EP96305700A priority patent/EP0757353B1/en
Priority to KR1019960032314A priority patent/KR100199315B1/en
Publication of CA2180421A1 publication Critical patent/CA2180421A1/en
Application granted granted Critical
Publication of CA2180421C publication Critical patent/CA2180421C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

Disclosed is an architecture of a RAM (random access memory) with BIST
(built-in self test) or functional test function. The RAM has a memory cell for storing differential or single-ended binary data and bit line signals are fully differential or single-ended. Shadow write is applied to read only and read-write bit lines. With the test function, port-to-port bit line shorts and port-to-port word line shorts are sensitized.
CA002180421A 1995-08-03 1996-07-03 Multi-port random access memory Expired - Fee Related CA2180421C (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE69623707T DE69623707T2 (en) 1995-08-03 1996-08-01 Multitordirektzugriffspeicher
EP96305700A EP0757353B1 (en) 1995-08-03 1996-08-01 Multi-port random access memory
KR1019960032314A KR100199315B1 (en) 1995-08-03 1996-08-02 Multi-port random access memory

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US185595P 1995-08-03 1995-08-03
US60/001,855 1995-08-03
US2081696P 1996-06-20 1996-06-20
US2081796P 1996-06-20 1996-06-20
US66782896A 1996-06-20 1996-06-20
US60/020,816 1996-06-20
US08/667,828 1996-06-20
US60/020,817 1996-06-20

Publications (2)

Publication Number Publication Date
CA2180421A1 true CA2180421A1 (en) 1997-02-04
CA2180421C CA2180421C (en) 2001-09-18

Family

ID=27485120

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002180421A Expired - Fee Related CA2180421C (en) 1995-08-03 1996-07-03 Multi-port random access memory

Country Status (2)

Country Link
KR (1) KR100199315B1 (en)
CA (1) CA2180421C (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100460141B1 (en) * 2002-07-08 2004-12-03 삼성전자주식회사 Dual port static memory cell and semiconductor memory device comprising the cell
US7665003B2 (en) * 2006-12-15 2010-02-16 Qualcomm Incorporated Method and device for testing memory
US11367480B2 (en) * 2019-12-04 2022-06-21 Marvell Asia Pte, Ltd. Memory device implementing multiple port read
US11750287B2 (en) 2021-05-25 2023-09-05 Ciena Corporation Optical DSP operating at half-baud rate with full data rate converters

Also Published As

Publication number Publication date
KR19980013716A (en) 1998-05-15
KR100199315B1 (en) 1999-06-15
CA2180421C (en) 2001-09-18

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Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed