KR100196330B1 - A synchronous semiconductor memory device and a method of driving the column decoder thereof - Google Patents

Abstract

The present invention relates to a high-density synchronous semiconductor memory device. Since the absolute time for performing a write operation is reduced, the memory device enters a read cycle to overcome the problem of progressing to a new operation cycle before the write operation is finished. The column decoder is selected by the first control signal PCSL_EN for selecting the column decoder after a predetermined first time T1 from the time when the external clock CLK transitions to the high level, and immediately after the external clock. After a predetermined second time T2 from the time when CLK transitions to the high level, the corresponding column decoder is deselected by the second control signal PCSL_PRE for non-selection of the column decoder, and the memory device is written in write cycles. When entering, after the third time T3 less than the first time T1 from the time when the external clock CLK transitions to the high level It causes the column decoder is selected by the first control signal (PCSL_EN) for selecting a column decoder. This makes it possible to compensate for the enable time of the CSL signal during the write cycle, thereby enabling high frequency operation of the high density semiconductor memory device.

Description

Synchronous semiconductor memory device and its column decoder driving method

1 is a schematic diagram of a memory cell array structure of a typical semiconductor memory device.

2 is a circuit diagram illustrating an example of a column decoder.

3 is an operation timing diagram of a column decoder.

4 is a circuit diagram showing a preferred embodiment of the operation cycle detection circuit according to the present invention.

5 is a timing diagram for explaining a column decoder driving method according to the present invention.

6 is a circuit diagram showing a preferred embodiment of the decoder selection control circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

21: differential amplifier 23,25: transfer gate circuit

15,27,29: latch circuit 40,50: delay circuit

60: selection circuit 70: decoder driving circuit

The present invention relates to a synchronous semi-conductor memory device that performs a read / write operation in synchronization with a clock provided from an outside of a chip.

One operation of a synchronous semiconductor memory device is a write-interrupt-read mode. This mode of operation refers to alternating write and read operations during successive clock cycles. This write-read operation may be performed on the same column address area, but is generally performed on different column address areas, respectively. The problem occurs when the read operation is performed in the next cycle through the input / output line (I / O line) where the voltage difference is increased by the write operation of the previous cycle. In this case, a problem of slowing down the read operation may occur. In a severe case, the selected bit lines may be connected to input / output lines by selecting a column decoder to read. When the voltage already developed through the write operation in the input / output lines inversely affects the bit lines, the charge of a cell stored in the bit lines may be reversed. have. To prevent this, the voltage difference between the input and output lines should be minimized by precharging the I / O lines to a predetermined voltage before the actual read operation occurs.

Therefore, in the case of the write-interrupt-read operation, the selection time of the column decoder in the write operation is shorter than that in the read operation in order to compensate for the time required for precharging the input / output lines. However, when a high density memory device operates at a faster clock cycle, the write operation is a limiting operation rather than a read operation, so this approach is a high density memory device operating at a fast clock cycle. Will be difficult to respond to. This is because the absolute time for performing the write operation is reduced, so that the write operation proceeds to a new operation cycle before the write operation is completed. This is especially a problem for high density memory devices, where the denser the memory device, the more the capacitive loading of the I / O lines increases, causing the write driver to drive the I / O lines. That's because it takes more time. On the other hand, in the case of the read operation, even if the capacitive loading of the input / output lines increases, the use of a current sense read amplifier that senses the current difference between the input / output lines leads to the capacitiveness of the input / output lines. The increase in loading rarely affects the read speed.

Accordingly, it is an object of the present invention to provide a high-density synchronous semiconductor memory device capable of high frequency operation by ensuring correct write operation time.

It is another object of the present invention to provide a method for driving a column decoder to enable high frequency operation of a high density synchronous semi-volatile memory device.

As a feature of the present invention for achieving the above objects, the semiconductor memory device according to the present invention; Column decoding means for selecting at least one of the column decoders in response to a column address; Operation cycle detection means for detecting whether the current operation cycle is a read cycle or a write cycle; The at least one column decoder is selected after a predetermined first time has elapsed from the trigger time of the external clock, and the cycle detecting means indicates the write cycle in response to the cycle detecting means indicating the write cycle. And in response, a decoder selection control means for selecting the at least one column decoder after a predetermined second time less than the first time has elapsed from the trigger time of the external clock.

In the apparatus of this aspect, the operation cycle detection means is further configured to generate a predetermined operation cycle detection signal corresponding to the write enable signal in response to predetermined signals corresponding to the internal clock, the column address strobe signal, and the chip select signal, respectively. Output

In the apparatus of this aspect, the decoder selection control means comprises: first delay means for delaying the internal clock for a first predetermined time, and delaying the internal clock for a second predetermined time less than the first time; Second delay means, selection means for selectively outputting one of an output of the first delay means and an output of the second delay means in response to the cycle detection signal, and an output of the selection means is provided Drive means for providing a predetermined control signal to the column decoder to drive the at least one column decoder.

In another aspect, the method of driving a column decoder according to the present invention includes selecting a column decoder after a predetermined first time has elapsed from a first time point at which the external clock transitions to a high level when the semiconductor memory device enters a read cycle. Selecting the corresponding column decoder by generating a first control signal for the non-selection of the column decoder after a predetermined second time elapses from a second time point at which the external clock transitions back to a high level. Deselecting the corresponding column decoder by generating a second control signal, and relative to the first time from the second time point when the external clock transitions to a high level when the semiconductor memory device enters a write cycle; Generating the first control signal for selection of the column decoder after a small third time has elapsed. Selecting the corresponding column decoder and generating the second control signal for non-selection of the column decoder after a predetermined fourth time elapses from a third time point when the external clock transitions back to a high level. Thereby deselecting the corresponding column decoder.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The selection of the column decoder is performed by column decoding means and decoder selection control means. The column decoding means comprises a column address buffer and a pre-decoder. The decoder selection control means generates control signals for finally selecting / deselecting the column decoder. Selecting / deselecting a column decoder means that the output of the color decoder is enabled / disabled. When the output of the column decoder is enabled, this means that the bit lines are coupled to the input / output lines.

Figure 1 schematically shows an example of the memory array structure of a typical synchronous memory device. In FIG. 1, reference numeral 1 denotes a cell array region, 3 is word lines, 5 is bit lines, 7 is sense amplifiers, 9 is NMOS transistors, 11 is input / output lines, 13 is column decoders. Each is shown. Bit lines 5 and input / output lines 11 are typically connected across the NMOS transistor 9, the gate of which is electrically connected to the output of the column decoder 13. Thus, in this case, the selection of the column decoder 13 indicates that the output of the column decoder 13 connected to the gate of the NMOS transistor 9 is pulled up to a high level. The gate of the NMOS transistor 9 will be referred to as a 'Column Select (CSL) gate' and the output signal of the column decoder 13 will be referred to as a 'CSL signal'. Such a structure may have various variations depending on the storage device, but these also fall within the scope of the present invention.

Meanwhile, since the column address buffer circuit and the pre decoder circuit are already well known in the art, only the matters related to the gist of the present invention will be described later, and the detailed description thereof will not be provided herein.

The output of the predecoder is provided to the column decoder 13, which takes as input a particular combination of predecoder outputs for column coding. In order to adjust the selection / non-selection timing of the column decoder in each of the read cycle and the write cycle, a control signal for controlling the column decoder is required in addition to the output (in other words, the column address) of the predecoder.

2 shows an example of a column decoder circuit to which the present invention is applied. Referring to FIG. 2, the column decoder circuit includes a NOR gate NOR1, two PMOS transistors MP1 and MP12, an NMOS transistor MN1, and two inverters INT1 and INT12. It consists of (1). As can be seen from FIG. 2, as the signals input to the column decoder 13, the output signal DCA of the predecoder and the control signal PCSL_EN for enabling the column decoder (hereinafter referred to as 'first control signal') are shown. And a control signal PCSL_EN (hereinafter referred to as a second control signal) for disabling the column decoder. In FIG. 3, CLK denotes an external clock, CAi denotes a column address, PCLK denotes an internal clock of a memory device, DCA denotes an output of a decoder, PCSL_EN denotes a first control signal, PCSL_PRE denotes a second control signal, and CSL denotes an external clock. Shows the output of the column decoder.

The operation of selecting / deselecting the column decoder will be described below with reference to FIGS. 2 and 3.

First, in order for the column decoder to be selected, the output (DCA) of the predecoder inputted to the corresponding column decoder must be enabled. However, even if the output DCA of the predecoder is enabled at a low level, the output of the NOR1 NOR1 remains at a low level as long as the first control signal PCSL_EN remains at a high level. The decoder is left in an unselected state.

On the other hand, the second control signal PCSL_PRE is initially at a high level. At this time, when the first control signal PCSL_EN is enabled at a low level for a predetermined time, the output of the NOR gate NOR1 is at a high level. As a result, the NMOS transistor MN1 is turned on to enable the output signal CSL of the column decoder to a high level.

On the contrary, in order to deselect the column decoder, the second control signal PCSL_PRE must be enabled at a low level. At this time, since the first control signal PCSL_EN has a pulse shape, the first control signal PCSL_EN is already at a high level when the second control signal PCSL_PRE is enabled for non-selection of the column decoder. . As a result, the output of the NOR gate NOR1 maintains a low level. Therefore, when the second control signal PCSL_PRE is enabled at the low level, the output signal CSL of the column decoder is disabled at the low level.

As described above, it can be seen that the time point of selecting or not selecting the column decoder is not controlled by the column decoding means but by the separate control signals PCSL_EN and PCSL_PRE. Accordingly, it can be seen that control signals (or control signals) may be controlled differently according to each operation cycle in order to change the selection time point or the non-select time point of the column decoder according to the read cycle or the write cycle.

In order to control the control signals differently according to each read cycle and write cycle, it is necessary to know which operation cycle (read or write cycle) the memory device is currently in. This is indicated by a write enable (/ WE) signal input to the device. Specifically, for example, in order to allow the memory device to enter a read cycle, a chip select (//) prior to a predetermined set-up time before the external clock transitions to a high level. The CS signal and the column address strobe (/ CAS) signal must be at the low level and remain at the low level until a constant hold time after the external clock transitions to the high level. In addition, the write enable (/ WE) signal must maintain the 'high level' state while satisfying the setup / hold time similarly to the above signals.

In the write cycle, it is exactly the same as in the read cycle described above except that the write enable (/ WE) signal remains in the 'low level' state. Therefore, the combination of signals can determine whether the memory device enters a read or write cycle.

4 shows a preferred embodiment of an operating cycle detection circuit according to the present invention. Referring to FIG. 4, the operation cycle detection circuit includes a differential amplifier circuit 21, transfer gate circuits 23 and 25, latch circuits 27 and 29, and other logic circuits 31 and 33. It consists of. In the present embodiment, the differential amplifier circuit 21 outputs a low level when the level of the write enable signal / WE is lower than that of the reference voltage signal Vref (that is, during a write operation) and outputs a reference voltage. When the level of the write enable signal / WE is higher than the level of the signal Vref (that is, during a read operation), a high level is output. The transfer gate circuit 23 (hereinafter referred to as 'first transfer gate circuit') is controlled by an internal clock PCLK, and the transfer gate circuit 25 (hereinafter referred to as 'second transfer gate circuit') It is controlled by the NAND gate 31 which performs logical NANDing of the three signals PCLK, PCS, and PCF. PCS and PCF signals will be described later in detail. In FIG. 4, 24a, 26a, 28a, 28b, 30a, 30b and 33 represent inverters and 24b and 26b represent transfer gates. The inverter indicated by reference numeral 33 serves to invert the output level of the amplifier 21. The operation cycle detection circuit of this embodiment having such a configuration outputs a low level cycle detection signal PWR in a read operation and a high level in a write operation.

The internal clock PCLK is a signal obtained by converting the external clock CLK for use in the storage device. In FIG. 4, the output 22 of the differential amplifier 21 is transmitted to the first latch circuit 27 through the first transfer gate circuit 23 at the moment when the internal clock PCLK becomes high level. When the inverted signal PCS of the chip select signal / CS, the inverted signal PCF of the column address strobe signal / CAS and the internal clock PCLK are both at a high level, the second transfer gate circuit ( It is transmitted to the second latch circuit 29 through 25. At this time, the inverter 33 inverts the output of the differential amplifier 21 latched by the second latch circuit 29 and outputs it as the cycle detection signal PWR. As a result, the cycle detection signal PWR maintains a low level when the memory device enters a read cycle and maintains a high level when the memory device enters a read cycle. By using the cycle detection signal PWR, an operation time point of the first and second control signals PCSL_EN and PCSL_PRE for controlling selection / non-selection of the column decoder may be controlled according to read / write cycles.

5 shows a case where read-write-read cycles are performed continuously. As shown in FIG. 5, the time at which the output of the column decoder CSL for the read cycle from the external clock CLK is enabled (ie, the time at which the corresponding column decoder is selected) is called T1 and it is disabled. The time (that is, the time when the corresponding column decoder is not selected) is called T2, and the time when the output (CSL) of the column decoder for the write cycle from the external clock is enabled is T3 and the time when the disable is T4. In the conventional case, T1 = T2 = T3 = T4 (actually there may be some time difference depending on the transition of the signal). Here, T1-T4 is a time (hereinafter, referred to as 'Tp') for precharging the input / output lines in the write-interrupt-read mode. The larger the value of Tp, the more the enable time of the write CSL signal is at least Tp less than the clock cycle time. This can be obtained by making T3 of the write CSL signal smaller than T1. For example, when T1-T3 = Tp, the enable signal of the write CSL signal is completely compensated. However, since T1 is larger than T3, the enable time of the read CSL signal is shortened, so that 0T1-T3Tp can be set. Therefore, the control of the timing of the output signal CSL of the column decoder in the read and write operations according to the present invention is performed as follows.

Referring to FIG. 5, first, when the memory device enters a read cycle, the column decoder is selected after a preset first time T1 from the time when the external clock CLK (see Nth clock) transitions to a high level. The corresponding column decoder is selected by the first control signal PCSL_EN. Therefore, at this time, the corresponding column decoder outputs the high level signal CSL.

Next, by the second control signal PCSL_PRE for non-selection of the column decoder after the second preset time T2 from the time when the next external clock CLK (see N + 1 th clock) transitions to the high level. This column decoder is deselected. At this time, the corresponding column decoder outputs a low level signal CSL.

When the storage device enters the write cycle, the column decoder is selected after the third time T3 less than the first time T1 from the time when the external clock CLK (see N + 1 th clock) transitions to the high level. The corresponding column decoder is selected by the first control signal PCSL_EN.

Next, by the second control signal PCSL_PRE for non-selection of the column decoder after the fourth time T4 preset from the time when the next external clock CLK (see N + 2 th clock) transitions to a high level. This column decoder is deselected.

6 shows a preferred embodiment of a decoder selection control circuit for generating a control signal for selecting a column decoder according to read and write cycles as described above. Referring to FIG. 6, the decoder selection control circuit includes first and second delay circuits 40 and 50 for delaying the internal clock PCLK by a predetermined time, respectively, and the operation cycle detection circuit shown in FIG. A selection circuit 60 for selecting and outputting either one of the output of the first delay circuit 40 and the output of the second delay circuit 50 in accordance with the output PWR, and the output of the selection circuit 60 are provided. In response, the first control signal PCSL_EN is provided to the column decoder to drive (or select) the decoder.

In the decoder selection control circuit according to this embodiment, the selection circuit 60 selects the output of the first delay circuit 40 having a longer delay time when the cycle detection signal PWR is at a low level, and the cycle detection signal Select the output of the second delay circuit 50 with a relatively small delay time when PWR is high level.

As described above, when the absolute time that the CSL signal is enabled during the write cycle is a limiting factor in the high frequency operation, as in the present invention, a technique for compensating the enable time of the CSL signal during the write cycle is as described in the present invention. It will be appreciated that this is a solution to enable high frequency operation.

Claims (4)

A semiconductor memory device having a plurality of column recorders and operating in synchronization with an external clock; Column decoding means for selecting at least one of the column decoders in response to a column address; Operation cycle detection means for detecting whether the current operation cycle is a read cycle or a write cycle; In response to the cycle detecting means indicating the read cycle, selecting the at least one column decoder after a predetermined first time has elapsed from the trigger time of the external clock, and wherein the cycle detecting means indicates the write cycle. And a decoder selection control means for selecting the at least one column decoder after a predetermined second time less than the first time has elapsed from a trigger time point of the external clock in response. The method of claim 1, wherein the operation cycle detection unit outputs a predetermined operation cycle detection signal corresponding to a write enable signal in response to predetermined signals corresponding to an internal clock, a column address strobe signal, and a chip select signal, respectively. A synchronous semiconductor memory device, characterized in that. 3. The apparatus of claim 2, wherein the decoder selection control means comprises: first delay means for delaying the internal clock for a predetermined first time, and a second delay means for delaying the internal clock for a predetermined second time less than the first time; Second delay means, selection means for selectively outputting one of an output of the first delay means and an output of the second delay means in response to the cycle detection signal, and in response to the output of the selection means being provided And means for providing a predetermined control signal to the column decoder for driving the at least one column decoder. A method of driving a column decoder of a semiconductor memory device operating in synchronization with an external clock, wherein a predetermined first time elapses from a first time point when the external clock transitions to a high level when the semiconductor memory device enters a read cycle. Selecting a corresponding column decoder by generating a first control signal for selection of the column decoder after the predetermined time has passed, and after a predetermined second time has elapsed from a second time point at which the external clock transitions back to a high level. Deselecting the column decoder by generating a second control signal for non-selection of the column decoder, and from the second time point when the external clock transitions to a high level when the semiconductor memory device enters a write cycle; Selection of the column decoder after a third time that is less than the first time has elapsed Selecting the corresponding column -C coder by generating the first control signal for the < RTI ID = 0.0 > and < / RTI > And deselecting said column decoder by generating a fraudulent second control signal for non-selection.