KR100195396B1 - Pulse generator and microcomputer with it - Google Patents

Abstract

The pulse generating device according to the present invention is operated according to a pulse control command including output time data for a given output pulse from an external device such as a CPU. The pulse control command including the output time data for the output pulse is transmitted from the outside to the master memory of the memory device at an arbitrary timing. The contents of this master memory are copied to the slave memory in response to the copyable signal transmitted from the copyable device. A copyable signal is transmitted each time a preset number of synchronization signals representing the end of the pulse period is generated from the time interval timer. When the timer value of the time interval timer matches the time data of the slave memory, the memory device reads the output control command of the output pulse from the slave memory. The output control circuit transmits an output pulse corresponding to the control command read as described above. As a result, when the output time data is reloaded at an arbitrary timing from the outside, air generation of the output pulse width can be prevented. Moreover, the CPU load is reduced.

Description

Pulse generator, microcomputer with same and soft memory device for pulse generator

1 is an overall structural diagram illustrating one embodiment of the present invention.

2 is a detailed structural diagram illustrating a time interval timer.

3 is a timing chart of triangular waveform carriers

4 is a timing chart of triangular waveform carriers

5 is a timing chart of tooth carrier

6 is a block diagram illustrating the structure of a copyable circuit.

7 is a block diagram illustrating the structure of a frequency divider circuit.

8 is a timing chart of a frequency divider circuit.

9 is a block diagram for explaining the structure of the parallel comparative type memory.

10 is a block diagram illustrating the structure of an output control circuit.

11 is a diagram for explaining a specific structure of an output control command.

12 is a timing chart of PWM pulse generation when a tooth carrier is applied.

13 is a timing chart of PWM generation when a triangular waveform carrier is applied.

14 is an overall structural diagram illustrating another embodiment of the present invention.

15 and 16 are structural diagrams respectively illustrating subprocessors.

FIG. 17 is an operation timing chart of the structure of FIG. 14 to which the subprocessor of FIG. 16 is applied.

18 is a block diagram for explaining another embodiment of the pulse generator of the present invention.

FIG. 19 is a timing chart illustrating the operation of the structure of FIG. 18. FIG.

20 is a timing chart illustrating a PWM pulse.

21 and 22 illustrate a time chart for explaining another embodiment of the pulse generation calculation method, respectively.

24 is a timing chart for explaining another embodiment of the pulse generating device of the present invention.

25 is a structural diagram illustrating an embodiment of a motor control microcomputer of the present invention.

FIG. 26 is a diagram for explaining the main parts of the structure of FIG. 25. FIG.

27 and 28 illustrate the effect of load current and dead time on the output voltage, respectively.

FIG. 29 is a timing chart for an operation operated by a CPU of FIG. 25. FIG.

The present invention relates to a pulse generator, and in particular, a pulse generator capable of generating a power switch device driving pulse signal, such as pulse generation data transmitted from a CPU, and microcomputers and pulse generators having such pulse generation thresholds. Relates to a device.

Pulse width modulation (PWM) pulse generators are used to control the voltage to be supplied to multiple devices. For example it acts as a device for converting the supplied voltage data computed by the CPU into the power switch device drive signal of the PWM inverter.

The conventional apparatus of the type described above is Japanese Patent Laid-Open Nos. 59-113792, 61-116994, Japanese Laid-open Patent No. 60-2510, 63-18018, Japanese Laid-Open Patent Publication No. 62-163579 It is published in the issue.

Furthermore, devices inherent in microcomputers (product number 18096) manufactured by Inkel, USA and other devices in microcomputers (product number HD6475328) manufactured by Hitachi are also known.

For the above prior art, there is a PWM pulse generator having several time interval timers and several registers. The PWM pulse generators operate to compare the value of the time interval timer with the time data representing the pulse width defined in each register to change the binary state of the PWM pulses corresponding to the time they coincide with each other.

Another PWM pulse generator is known which has a mnemonic suppressor configured in such a way that the time when the binary state of the free run timer is changed is a tag, and the binary state after the change is data as a data. have. According to this method, the value of the principal run timer and all tags are compared in the memory.

Then the data corresponding to the matching tag is sent.

However, there is a problem that a pulse width error occurs due to the timing at which the value of the register indicating the PWM pulse width is reloaded.

Moreover, whenever the time data of the PWM pulse changes, etc., writing is performed in the register, so that an excessive load is applied to the CPU.

The device using the free-run timer consists of the first and last conversion of the PWM pulses being commanded in each period of the PWM carrier.

The time instruction of the above type increases the load applied to the CPU, thereby reducing the processing capacity in the CPU-operated processing. For example, at least 24 data items must be generated and transmitted in a bridged three-phase inverter to control motor rotation because U, V, W gate pulses for the device switch for three phase x6 arms must be generated.

The upper and lower arms of the bridge structure, which are turned off and turned on, complement each other. A pair of gate pulses corresponding to the upper arm and the lower arm each have a dead time with both arms turned off to prevent the short cut of the upper and lower arms.

However, the prior art does not have a means of reducing the number of data items transmitted at the time of pulse generation, which causes a problem in that an excessive load can be transferred to the CPU at the data transmission time. In particular, an excessive load is applied during the transmission process if necessary for the pulse width modulation (PWM) control operation of the high frequency carrier waveform.

Similarly, another problem arises when processing the dead time when the high frequency waveform is obtained and the load applied to the CPU becomes too large.

Thus, it is possible to use a method in which the time interval timer is used in place of the free run timer and the need for the time command is eliminated in the period in which the PWM signal has a predetermined waveform. However, when the value of the tag is reloaded to a value less than the time interval timer value, the tag and the search key cannot coincide with each other in the PWM period when the value is reloaded. This raises the concern that errors can occur in the pulse width.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pulse generating device capable of preventing the occurrence of a pulse width error due to the fact that pulse width data and the like are reloaded, and to provide a microcomputer having the device.

Another object of the present invention is to provide an associative memory device capable of realizing stable associative operation even when a tag is reloaded.

It is still another object of the present invention to reduce the number of data items required to generate a pair of pulses, the properties of each pulse having a predetermined correlation and the timing relationship between the first and last conversion points of the pulse (e.g. It is to provide a pulse generator that can reduce the load applied to the upper CPU by performing calculations to control the dead time.

In order to achieve the above object, one aspect of the present invention provides a CPU (central processing unit) for computing an output control command indicating a binary state of an output pulse and a pulse control command including time data for indicating a change timing of a binary state; Starts operation according to the operation start command supplied from the CPU, generates a preset pattern timer value that is sequentially changed with the clock signal according to the timer period defined by the control command supplied from the CPU, and the timer value is displayed at the end of the timer period. A time interval timer for sending a simultaneous signal each time that the numerical value is indicated and for resetting the timer value; Copyable means for receiving a simultaneous signal transmitted from a time interval timer and transmitting a copy signal in response to a preset simultaneous signal of the simultaneous signal; Output time master memory for storing time data for output data moved from the CPU and output slave memory for copying and storing time data of the output time master memory in response to the copy signal, instructions of the memory compared and supplied from the CPU The output time master memory or the output time slave memory is compared with the timer value of the timer register and when the values match each other, a comparator for transmitting simultaneous signals and a synchronization signal transmitted from the comparator. Output control command from output control master memory in response to copy signal and output control master memory for storing output control command representing binary status of output pulse supplied from CPU to send output control command corresponding to slave memory Copy and save An associative memory device having an output control slave memory; And an output control circuit for receiving an output control command transmitted from the associative memory device and for transmitting an output pulse corresponding to the output control command.

The copyable means is configured to generate a copy signal each time a synchronization signal is supplied a predetermined number of times. Moreover, the copyable means is configured to be operable to correspond to the copy signal supplied from the CPU and to generate a copy signal simultaneously with the supplied synchronization signal immediately after the copy instruction is supplied.

The associative memory is configured to have a plurality of output time master memory, an output time slave memory and a comparator, and one of the plurality of output time master memory, the output time slave memory and the comparator are each assembled and associated with a plurality of tag word cells. The memory device includes a plurality of output control master memories and output control slave memories, and one output control slave memory of the plurality of control master memories is gathered to be composed of output data word cells, and the output data word cells are provided to correspond to each other. do.

Each comparator of the memory device compares each output time master memory or each output time slave memory in parallel with a timer value according to a given parallel comparison command, and continuously compares a specific output time master memory or a specific output time slave memory with a given continuous comparison command. To be compared with a timer value.

The Time Interval Timer is a timer register for saving the timer value and a cycle register for storing the maximum timer value to clarify the period of the output pulse.The timer value of the timer register is fetched to send to the timer register, and the unit value is added to the timer value. A timer arithmetic means comprising an adder for adding a sigma, a comparator for comparing the values of the period register and a timer register to transfer a coincidence circuit when they coincide with each other, and a synchronizing signal simultaneously with the generated clock signal condition. It is determined to be provided with a clear circuit which receives the coincidence signal in order to erase the adder and the synchronizing signal generating circuit for generating.

The structure in which the CPU is connected to the pulse generation device so that the CPU (central processing unit) calculates an output control command defined by the binary state of the output pulse and the like and a pulse control command including time data indicating the binary state conversion timing Can be realized. The pulse control command calculated as described above is transmitted to the time interval timer, the copyable means, and the memory. Furthermore, the subprocessor may be coupled in addition to the CPU to cause the subprocessor to perform operations performed by the CPU, e.g., binary conversion timing of the output pulses and operations of time data representing transfer functions to registers. .

According to the pulse generating device constructed as described above according to the present invention, the contents of each master memory are copied to each slave memory whenever a synchronization signal is generated a predetermined number of times. Since the timing of the copy function is limited in response to a synchronization signal indicating that the value of the time interval timer becomes the last value, it is possible to prevent the occurrence of errors in the pulse width or output due to the reload timing of the pulse output time data.

Furthermore, since the pulse control data such as time or memory is provided to the memory in use of the data comparison function, if the tag is being reloaded, it can be performed using the tag for the state of the reloading of the stable associative function. In addition, since the tag memory and the comparator are integrally formed and the associative function memory are integrally formed, the wiring length can be shortened and the area of the chip can be reduced.

When the memory device is configured in such a manner that the contents of the time interval timer and the output time master memory or the output time slave memory are sequentially compared, the output data corresponding to each tag is sequentially arranged even if the same tag is recorded in multiple tags. Can be read.

As a result, even if the conversion time of the multiple pulse signals is distributed for each signal, a pulse signal having a desired waveform can be obtained.

According to the time interval timer, the carrier may be selected from a triangular waveform carrier and a sawtooth carrier by a pulse signal modulation method.

The second object of the present invention can be realized by the above-described reminding device.

Another aspect of the present invention to achieve the third object of the present invention is a reference time data register for storing reference time data for indicating the timing axis of the generated pair of pulses; First and second working time data registers for storing working time data representing timing relationships of respective pulses with respect to the reference time data; First and second pulse output registers for respectively storing state data in which a pair of pulses indicate a binary state of each pulse; A counter for clock fill counting; A unit of operation for retrieving the reference time data and each operation time data to numerically obtain time data for the first and last transformation of each pulse; A transmission control unit for transmission timing control of each pulse time data obtained in an operation unit; First and second time data registers for storing respective pulse time data transmitted from the transmission control unit; There is a pulse generator comprising first and second comparators for comparing the value of the counter with the time data of each time data register, respectively, to transmit a coincidence signal when they coincide with each other. Here, the operation unit performs a defined operation in response to the operation control signal stored in the control register, the transmission control unit controls the zone transfer timing of each time data in response to the transmission control signal stored in the control register, the first pulse output The register has an output terminal reset to a binary state realized by reversing stored state data, the second pulse output register has an output terminal reset to a binary state of the stored state data, and the first and second pulse outputs. The registers each reverse the binary state of the output terminal when one match signal is supplied from the corresponding comparator and reset the binary state of the output terminal when the next match signal is supplied.

The counter is reset in response to the reset signal periodically stored in the control register, and the reference time data, each working time data, the status data, and the control signal are supplied from the outside in accordance with the transmission period of the counter's count-up reset signal.

Moreover, when the working time data for each pulse is structured in such a way as to match the reference time data, the reference time data register or the first operating time data can be omitted from the structure and the number of transmitted data items can be reduced by one. have.

Each pulse output register preferably has a reverse output terminal maintained in an inverted state of the output terminal. In this case, an output switch capable of selecting an output terminal or an inverting output terminal of each pulse output register is provided, and the polarity of the generated pulse when each switch is structured in a controlled manner in response to an output switch control signal stored in the control register. Can represent the feasibility of a general purpose.

The counter includes a general free run counter or an up / down counter. In this case, the content of the operation performed by the operation unit and the control signal is determined according to the type of counter used.

Since the structure of the pulse generator according to the present invention is as described above, the third object of the present invention can be achieved with the following effects.

That is, the time data for the first and second transform points of a pair of pulses is obtained by a unit of operation using one reference time data item and a pair of work time data items. The data thus obtained is stored in a pair of pulse output registers.

When it is determined by the comparator that the value of the counter matches the first transition or time data, the output terminal of the first pulse output register is changed to a specific binary state (positive or negative) and then the counter matches the last conversion time data. Is reset when Similarly, the output terminal of the second pulse output register is operated in the reverse way.

As a result, a pair of pulses can be generated in a pattern suitable for operating the upper and lower arm switching elements that are complementary to each other. As a result, one item of time data can be sent to the upper CPU. Thus, the load applied to the upper CPU at the transfer operation time can be reduced. Furthermore, the load can be reduced because the operation to be performed by the upper CPU can be eliminated for the purpose of controlling the time difference between the pair of pulses.

When configured to have an up / down counter, the first and last transition points of the pulse can be controlled using only one time data item by performing the up-reset and down-reset functions consistent with the period of the PWM carrier wave. As a result, the number of operations to be performed in units of operations may be reduced.

An embodiment of the present invention will be described with reference to the drawings. 1 shows a main part of an embodiment of a microcomputer using a PWM pulse generator according to the present invention. As shown in FIG. 1, the apparatus according to this embodiment includes a CPU 100, a control register 110, a time interval timer 120, a copyable circuit 130, a parallel comparison type reminiscent memory 140, and output control. Circuit (150)

And a sub-processor 160. Each element such as the control register 110 is connected to the CPU 100 via the system bus BO. The CPU 100 is an operation command means for transmitting a command necessary to generate a PWM signal by performing various operation processing. Various instructions generated by the CPU 100 are transmitted to the control register and the sub-processor 160 and the like.

The control register 110 has an area of 16 bits each allocated as shown in Table 1 and stores corresponding information items.

The contents of the instructions stored in the corresponding bits of the control registers shown in Table 1 are then described. The interrupt request state (IRS) is data showing whether or not a request is made to the CPU 100 for interruption processing. The interruption request is the interruption request enable bit IRE when the copy signal S3 is generated. The interruption request signal S19 requests the CPU 100 with the enable IRS · IRE-1 when the interruption request state IRS is requested. Save). The function start bit STR stores a command for instructing the function start of the PWM pulse generator according to the present invention. The carrier wave select bit CWS stores a command for selecting a carrier related to the generation of the PWM signal from triangular waves or sawtooth waves. The clock source selector CSS selects a timer clock S11 for the time interval timer 120. Stores instructions for selecting from multiple clock signals with periods. The subprocessor function enable unit SPE stores a control command that causes the subprocessor 160 to operate the output time data of the output pulse instead of the CPU 100. The periodic copy enable unit PCE stores a command for specifying a period for copying data from the master memory 141 to the slave memory 142. The copy period is determined by the CPU 100 based on the synchronization signal S12 transmitted by the time interval timer 120, for example. The data N for generating the copy signal S13 is stored each time the synchronization signal S12 is transmitted N times (N is a natural number). The random copy enable unit RCE stores a command for the CPU 100 to enable random copying from each of the periodic copies. When this command is issued, the copy signal S13 is generated in synchronization with the subsequent synchronization signal S12. The master memory comparison bit (CMM) stores a command to store a memory compared with the time interval timer 120. When the command becomes 1, the master memory is selected. When this goes to zero, the slave memory is selected.

As a result, the two-layer memory structure of the parallel comparison type memory device 140 can be equivalently made into a single layer. The scan bit SCN stores a command specifying a method of comparing the time interval timer 120 with the parallel comparative type memory 140. The comparison is run sequentially when the command is one. When this is zero, parallel comparison is enabled. The output signal reset bit OSR stores a command to reset the output signal. When the command is 1, output of all signals in the output signal group S17 is prohibited. When this is 0, the normal output is produced.

If the content of the start bit STR is 1, it means operation. Moreover, a zero of this means no operation. The state before the operation of the PWM pulse generator according to the present invention is defined in accordance with the contents of the operation start signal STR. The time interval timer 120 stops reproducing the contents of the timer register 121 and stops the time counting operation before the operation start signal STR is supplied. When the STR is supplied, the time interval timer 120 starts to operate in accordance with the result of the time coefficient written by the CPU 100. When the start signal STR is not supplied to the copyable circuit 130 and the operation is not started, that is, when the STR is 0, the copyable circuit 130 is connected to the master memory 141 and the slave memory 142. The copy signal S13 is set to 1 to perform the initial call while keeping the contents coincide with each other. As a result, the desired associative function can be performed in accordance with the operation start time.

When the operation start signal STR is supplied to the output control circuit 150, in accordance with the output control command from the parallel comparative associative memory 140 which is not initialized by the contents reproduction CPU 100 of the supply register 154. To prevent this, the supply of the write signal to the output register 154 is prohibited.

The setting and resetting of each bit of the control register 100 performed by the CPU 100 is executed by writing 1 or 0. However, the interruption request state IRS is set by the CPU and reset by the copy signal S13. The total reset of the pulse generating device according to the present invention is performed in response to the total reset signal S10. In order to reduce the load applied to the CPU 100 and to eliminate the delay of the reset signal for the purpose of performing the reset operation, only all bits of the control register 100 are zero in response to the total reset signal S10.

Next, the structure of each element will be described. The time interval timer 120 includes a period register 122, a timer operator 123, and a timer register 121. The time interval timer 120 counts the timer clock S11 to convert the time interval timer value T according to a command written by the CPU 100 to the control register 110 and the command is a PWM from the sawtooth wave and the triangle wave. This command selects a carrier. Further, the synchronization signal S2 is transmitted at the time when the time interval time value T becomes the minimum value, that is, every timer period. The rising signal S18 is generated in response to the periodic signal S12. The rising signal S18 indicates the state of the timer value T as to whether it is increasing or decreasing.

For example, when the time interval timer value T is generating a triangular wave carrier, the timer value T is increased at the beginning of the timer period and decreased at the end of the timer period.

2 signs the specific structure of the time interval timer 120.

Referring to the drawing, the timer 120 includes a timer register 121, a period register 122, a numerical comparator 123g, a 0/1 detector 123h, a flip-flop 123i, and an incrementer / decrementer 123j. ), A clear circuit 123k, a multiplexer 124, and logic circuits G4, G5, G6, and G7. The timer register 121 receives the timer clock S11 from the logic circuit G6 and time intervals between the data received by the numerical comparator 123g, the 0/1 detector 123h, and the incrementer / decrementer 123j. In order to transmit the timer value T, the timer register 121 receives the timer clock S11 from the logic circuit G6 and receives data from the multiplexer 124 simultaneously with the timer clock S11.

The period register 122 stores the maximum value T of the time interval timer T for the system bus BO. The maximum value T is the maximum value for specifying one cycle of the PWM signal when it is changed into a sawtooth form with a timer value T.

The numerical comparator 123g compares the time interval timer value T and the maximum value T to set the maximum value signal S123g to 1 when the two values coincide with each other. This also makes the maximum value signal S123g zero when they do not coincide with each other.

The 0/1 detector 123h transmits a minimum value signal S123ha that shows whether the time interval timer value T is 0 and a 1-detection signal S1234hb that shows whether it is 1 or not.

When the time interval timer value T is 0, the maximum value signal S123ha becomes 1. When the time interval timer value T is not zero, the minimum signal S123ha becomes zero. When the time interval timer value T is 1, the 1-detection signal S123hb becomes 1. When the time interval timer value T is not 1, the 1-detection signal S123hb becomes 0. The rising signal S18 and the clear signal S123ic are in response to the maximum value signal S123g, the minimum value signal S123ha, the 1-detection signal 123hb and the carrier waveform selection CWS transmitted from the control register 110. Is generated. This is also the maximum value for designating the one cycle of the PWM signal when it is changed in the form of a triangle of the timer value T.

The numerical comparator 123g compares the time interval timer value T and the maximum value T to set the maximum value signal S123g to 1 when the two values coincide with each other. This also sets the maximum value signal S123g to zero when they do not coincide with each other.

The 0/1 detector 123h transmits a minimum value signal S123ha showing whether the time interval timer T is 0 and a 1-detection signal S123hb showing whether it is 1. When the time interval timer value T is 0, the maximum value signal S123ha becomes 1 and when the time interval timer value T is not 0, the minimum value signal S123ha becomes 0. When the time interval timer value T is 1, the 1-detection signal S123hb is 1, and when the time interval timer value T is not 1, the 1-detection signal S123hb is 0. The rising signal S18 and the clear signal S123ic are generated in response to the super-value signal S123g, the minimum value signal S123ha, the 1-detection signal 123hb and the carrier waveform selection CWS transmitted from the control register 110. do. As a result, the operation performed by the incrementer / decrementer 123j and the clear circuit 123k is controlled. The rising signal S18 becomes 1 when the time interval timer value T increases. In this state, the incrementer / decrementer 123j adds one. The rising signal S18 is zero when the time interval timer value T decreases. In this state, the incrementer / decrementer 123j is subtracted. When the clear signal S123ic is 1, the output value TK from the clear circuit 123k is made zero. The supply value is transmitted as it is when the clear circuit signal S123ic is zero.

The operation when the triangular waveform carrier is assigned is explained based on FIG. 3 and FIG. The flip-flop 123i is set when the triangular wave is assigned to the carrier by setting the carrier wave selection CWS to one. As a result, the rising circuit S18 becomes 1 so that the addition instruction is supplied to the incrementer / decrementer 123j. Thus, the output value from the timer register 121 is sequentially added to the incrementer / decrementer 123j. The timer value thus obtained is transmitted to the multiplexer 124 via the clear circuit 123k in order to be supplied to the timer register 121 again. When the operation is continued, the time interval timer value T is sequentially increased in the form of a step at the same time as the timer clock S11. When the timer value T approaches the maximum value Tp, each signal changes as shown in FIG. That is, when the rising signal increases from the period C1 to C4, the time interval timer value T becomes Tp-2, Tp-1, Tp while 1 is sequentially increased. The maximum value signal S123g transmitted from the numerical comparator 123g becomes 1 in the period C4 at which the time interval timer value T becomes Tp. As a result, the flip-flop 123i is reset so that the rising signal S18 returns to zero, which is in the decreasing state. So the order of subtraction comes out as an incrementer / decrementer (123j). Then, the time interval timer value T is sequentially subtracted by one from each input of the timer clock S11 so as to change to the state of FIG. In FIG. 4, when the rising signal S18 decreases near the end of the work cycle of the time interval timer, the time interval timer value T is subtracted from 2 to 1 by the timer clock in the period C1 of the operation clock. do. At this time, the 0/1 detector 123h causes the one-detection signal 123hb to be one.

At this time, since the 1-detection signal 123hb becomes 1 and the rise signal S18 becomes 0, the logic circuit G5 transmits a timer clock pulse to the period C3 as the synchronization signal S12. The time interval timer value T is subtracted to zero by the timer clock pulse. At this time, the 0/1 detector 123h sets the minimum value signal S123ha to one.

In response to the minimum value signal S123ha, the flip-flop 123i is set, which causes the rising signal S18 to be reversed to be 1 in the period C4. That is, the addition instruction is issued to the incrementer / decrementer 123j. As a result, the time interval timer value T increases in response to the timer clock pulse. Even if the 1-detection signal S123hb is 1 from the period C6 to C8, the logic circuit G5 does not generate the synchronization signal S12 after the increase of the rising signal. As a result of the operation, a triangular waveform carrier can be obtained. The logic circuit G5 generates only one synchronization signal S12 in one cycle of the triangular waveform carrier.

When the sawtooth carrier is assigned by the carrier wave select bit CWS of the control register 110, each waveform changes as shown in FIG. In this case the carrier wave selection CWS becomes zero, which causes the flip-flop 123i to be set effectively continuously. As a result, the rising signal S18 is maintained at one. Furthermore, the clear signal S123ic becomes equal to the maximum value signal S123g.

When the flip-flop 123i is set and the incrementer / decrementer 123j continuously adds the output value from the timer register 121, the time interval timer value T of FIG. 5 is represented by the period C1 and C3. It is increased by one by the timer clock pulse (S11). In the period C4, the periodic register value Tp and the time interval timer value T coincide with each other such that the maximum value signal S123g becomes one. As a result, the clear signal S123ic becomes 1 and the output value TK from the clear signal 123k becomes zero. The zero thus obtained is stored in the timer register 11 in accordance with the next timer clock pulse.

As a result, the maximum value signal S123g and the clear signal S123ic become zero, which causes the clear circuit 123k to pass the incrementer / decrementer output value Tj. As a result of the operation, the time interval timer value T is increased by one in accordance with the subsequent timer clock pulse S11, which in turn causes it to equal the maximum value Tp.

In this case, the synchronization signal S12 is transmitted simultaneously with the timer clock S11 generated after the clear signal becomes one.

As described above, a triangular wave carrier and a tooth carrier are generated, respectively. The triangular waveform carrier can sufficiently reduce the high frequency components of the three phase inverters as compared with the effect obtained with the tooth carrier. Moreover, it is theoretically found that the main frequency of electromagnetic noise is twice the carrier frequency, so that the noise can be sufficiently reduced when a triangular waveform carrier is applied. Therefore, this embodiment is conventionally a method in which two types of carriers, namely, tooth carriers, included in a microcomputer and a triangular wave carrier are generated. When a triangular waveform carrier is applied as a carrier, DC motor control can be enhanced because the first conversion of the PWM signal coincides with the beginning of the PWM period.

The copyable circuit 130 generates a copy signal S13 whenever the synchronous signal S12 is generated N times, and the copyable circuit 130 matches the value N defined in the control register by the CPU 100. The radiation signal S13 is generated. The copy signal S13 is synchronized with the synchronization signal S12 which shows that the time interval timer value T is the minimum value. Therefore, the problem that the time data of the memory to be compared exceeds the time interval timer value T can be prevented close to the time when the contents of the master memory 141 are copied to the slave memory 142. Therefore, an output control command can be issued at a desired time set for the parallel comparative type memory device 140. Furthermore, the control period of the PWM signal change control device is required to be an integer multiple of the time interval timer period.

The above request can be realized by generating the copy signal S13 each time the synchronization signal S12 is generated a predetermined number of times by the CPU 100 and by driving the associative storage device. The period of the radiation signal S13 serves as a control period for the device to be controlled. The structure of the copy function circuit 130 is then described using FIG.

In response to the frequency division designation signal S611, the copyable circuit 130 copies the periodic copy enable signal S610 in response to a command issued from the synchronization signal S12 frequency division circuit 620 and the control register 110. And a logic circuit G62 for converting to S13). The copyable circuit 130 is configured in such a manner that, when the operation start signal STR is 0, the copy signal S13 is brought into a copy state, that is, 1 by the logic circuit G62. As a result of this operation, the slave 141 is easily initialized. When the above operation is not supplied, it is preferable to have a structure in which the master memory comparison bit CMN becomes 1 and thus the copy signal S13 becomes 1.

However, the structure is constructed in such a way that the master memory 141 is the object of the associative function. Therefore, there is a risk of error in information that is not defined by the master memory compare bit (CMN).

The division circuit 620 generates the period copy enable signal S610 by dividing the synchronization signal S12 in accordance with a command by the period copy enable portion PCE of the control register 110. The periodic copy enable signal S610 is supplied to the logic circuit G62 so that the random copy enable signal S620 also becomes 1 when the CPU 100 writes 1 in the random copyable bit RCE of the control register 110. do. Therefore, the copy signal S13 is generated to the logic circuit G62 simultaneously with the synchronization signal S12 generated immediately after the write operation is performed by the CPU 100. The random copyable bit RCE is reset when the copy signal S13 is generated. When the copy signal S13 is generated, the interruption request state IRS is set. When the interruption request bit IRE is 1, an interruption signal is generated.

7 illustrates a structure of a divider circuit 620 of the copyable circuit 130. According to this embodiment two phase non-overlapping waveforms are applied to the operating club and two phase non-overlapping waveforms are applied to the main part of the high frequency operating CMOS microcomputer.

The reason for this is that two phase overwrapp waveform waveforms require four times the latch of one operating clock period, but two phase nonoverwrapp waveforms only require twice. This effect is obtained in that the size of the circuit can be reduced. The idea is common to all circuits according to the invention. The dividing circuit 620 is a Phillip flop 721, 722, 723, a comparator 710, a logic circuit (G71), (G72). It consists of (G73). As a result, a 3-bit sync counter is constructed. The synchronization signal S12 is counted by the three-bit synchronization counter configured as described above so that the number N indicated by the three-bit CPU2, CPU1, CPU0 of the synchronization copy enable unit PCE is compared with the coefficient by the synchronization counter. do.

If they match with each other, the sync counter is reset. The output from the comparator 710 acts as a periodic copy enable signal S610 by dividing the synchronization signal S12 by the value N of the periodic copy enable unit PCE. In this structure, the flip-flop 721 constitutes a toggle flip-flop as a synchronous clear of the master slave structure.

The operation of frequency divider circuit 620 is described next with reference to FIG.

When the value of the period copy enable unit PCE is 0, the output of each flip-flop is always 0, and the period copyable circuit S610 is always 1.

As a result, the copy signal S13 is generated whenever the synchronization signal S12 is generated. When the value of the periodic copy enable unit PCE is 5, that is, when PCE0 is 1, PCE1 is 0, and PCE2 is 1, the sync counter composed of flip-flops 721 to 723 counts from 0 to 5 and is 0. Return to When the coefficient is 5, the comparator 710 detects a coincidence between the coefficient and the value of the periodic copy enable unit PCE so that the periodic copy enable signal S610 is transmitted. The width of the periodic copy enable signal S610 is equal to one cycle of the synchronization signal S12, and the period thereof is an integer multiple of the synchronization signal S12, that is, an integer multiple of the carrier period. Further, the period of the period copy enable signal S610 is a value obtained by adding work to the value of the period copy enable unit PCE. For example, according to the example of FIG. 8, since the values of the periodic copy enable unit PCE are 0 and 5, the period of the periodic copy signal S610 is one and five times the period of the synchronization signal S12.

The parallel comparison type memory device 140 is composed of a master memory 141, a slave memory 142, and a comparator group 143, and its memory is in the form of a two-layer for arbitrary comparison.

The random write memory from the CPU 100 is the master memory 141, and the comparison memory having the time interval timer 120 is the slave memory 142. The contents of the master memory 141 are copied to the slave 142 in response to the copy signal S13 so that the data recorded by the CPU 100 is reflected by the associative operation. The master memory 141 is divided into an output time master register group corresponding to a tag portion and an output control master register group corresponding to an associative portion. The registers in each of these groups are assigned to respective positions (addresses) of the memory space of the CPU 100. That is, the master memory 141 accesses each register via the system bus BO. Further, the slave memory 142 is divided into an output time master register group of the master memory 141 and an output time slave register group and an output control slave register group so as to correspond to the slave register group at the output. The contents of the output time slave register group are compared in parallel by the comparator group 143 while using the time interval timer value T as the search key.

When a register matching the time interval timer value T is detected as a result of the comparison, a matching signal of a tag number corresponding to the matching output time slave register number n is transmitted. The output control command stored in the output control slave register #n (N: number) corresponding to the tag #n is transmitted via the output command bus S16.

At the same time, an output enable signal S15 representing the output signal group S17 is transmitted in accordance with the command so as to indicate that the data on the bus S16 is valid.

As described above, the associative storage device 140 stores the tag portion, the associative portion, output time data, and output control data. Furthermore, the time interval timer value T is used as the search key. As a result, an output control command can be issued at a desired time. Furthermore, the memory is in the form of two layers and the CPU writes output time data defining the time at which the output signal changes and output control command data defining the binary state after the change in the master memory 141.

Thus, when the contents are reloaded at the midpoint of the period (carrier period) of the time interval timer, the contents of the slave memory 142 are maintained without being reloaded. As a result, the occurrence of the pulse width error of the PWM signal can be prevented. Next, the specific structure of the memory device 140 will be described with reference to FIG.

The associative memory 140 includes an OR gate 914 and a slave memory added to the mnemonic memory I / O circuit 911, the read priority circuit 921, the output of the mnemonic memory output latch 913, and the master memory 141. 142 and a comparator group 140. The master memory 141 and the slave memory 142 are divided into a tag portion and an association portion, respectively.

That is, one output time master register (#n), one output time slave register (#n) and one comparator (#n) are collected to form one layout cell composed of the tag word cells (920). .

The plurality of tag word cells 920 thus formed are supplied.

Furthermore, one output control master register (#n), output control slave register (#n) and one data output circuit (#n) are collected to form one layout cell consisting of output data word cells 930. do. The plurality of output data output cells 930 thus formed are supplied. Where n represents a number. Since the associative memory 140 is configured as described above, the wiring length of the master memory 141, the slave memory 142, and the comparator group 143 can be shortened, and the area required for forming the circuit can be narrowed. Moreover, the load capacity of the circuit is reduced, which has the effect of eliminating or omitting transistors in the output stage of each register. As a result of the two effects, the size of the layout of the memory device 140 is reduced.

In addition, the layout is reduced because the I / O circuit 911 is generally composed of a plurality of registers.

In this structure, when the copy signal S13 is received, the contents of each master register are copied to the slave registers. The time interval timer value T is supplied as a search key for each comparator parallel to be compared in parallel with each output time slave register.

Comparator #i (i: number) whose contents coincide with each other transmits tag #i matching signal S9i. When two or more contents coincide with each other, the read priority circuit 912 reads the output control command of the output control slave register #j via the data output circuit #j via the output data bus Bout. The read signal S9ja is transmitted to a small tag number (e.g., jth). That is, one output control command is generally generated. According to the above structure, the associative memory output latch 913 is a differential amplifier for amplifying the voltage of the output data bus Bout by the amount of the voltage of the output control command bus S16.

The priority circuit 912 can effectively control a space vector type PWM inverter in which output control command generation is sequentially defined. The output control commands sent in the latter sequential order proceed when two or more tags coincide with each other at the same time.

As a result, the pulse width error of the transmitted PWM is prevented. As a method of decoding the output control command, four types of methods are provided which are assigned in accordance with the output control mode (OCM) in the output control command. According to this embodiment two sets of three parallel outputs are applied. When the scan bit SCN for the control register 110 becomes one, only one of the eight comparable signals S1100 to Sf1107 becomes one.

The position of 1 is sequentially moved one by one for each operation clock period.

Moreover, the comparison period with the comparable signal of 1 performs the comparison operation. As a result, all comparison operations for each of the eight operating clock cycles are completed. In the case where two or more tags coincide with each other at the same time and there is a possibility that the read priority circuit 912 may not produce the desired result, the scan bit SCN operates to produce the desired result. The scan bits (all comparable signals S1100 when the SCN is 0) to S1107 become one.

Next, the output control circuit 150 will be described. The control command in the output control command bus S16 is drawn out by the mnemonic storage command register 151. When the output enable signal S15 representing the above described command is efficiently received, the decoder 153 records the value assigned to the assigned bit of the output register 154 according to the above described control command. As a result, the desired PWM pulse is transmitted to the output signal group S17. In the case where the triangular pulse is selected as the carrier of the PWM pulse, the input / output time data type coincides with the internal timer value T that is doubled in front of the real part of the internal timer period.

The PWM pulse generator commands a change in the PWM pulse from the corresponding double to the reverse binary state. For example, the PWM pulse generator should command the output signal to rise in front of the timer period and the fall to the front of the real part. However, the parallel comparison type reminder 140 is different from the real part of the timer period. It does not issue a command. For this purpose, providing two sets of the output control master register group and the output control slave register group to use the real part and the front of the timer period causes the size of the circuit to increase. Therefore, the output value of the same instruction is converted in front of the real part of the timer period, and as a result, the number of required sets of the output control master register group and the output control slave register group is reduced to one. The decoder 153 receives the rising signal S18 transmitted from the internal timer 120 to control the output register 154 according to the above-described rising signal S18 and the control command of the mnemonic suppression command register 151. Receive. The CPU 100 can write the output register 154 in units of 1 bit via the system bus BO. The above-described function of the CPU 100 is a supporting operation when the number of words of the parallel comparative type memory device 140 is not sufficient enough and the output control group S17 is not controlled there. In addition, the output of the PWM pulses may suddenly stop due to captivity. Therefore, these structures are provided with circuitry arranged similarly to the decoder circuitry for the mnemonic storage instruction register 151, and in such a manner arranged so that a CPU instruction register is provided, so that the CPU 100 is configured with a parallel comparison mnemonic ( Similar to 140, by using the output control command, the output signal group S17 can be individually or jointly. However, it is difficult for the CPU 100 to simultaneously change the instructions issued to the CPU instruction register at the actual part and the front of the internal timer cycle. Therefore, the output value that changes corresponding to the real part and the front of the timer period is not executed. Furthermore, in the case where the instruction from the CPU 100 and the instruction from the parallel comparison type memory device 140 are changed to the same output signal, the decoder 153 advances the instruction from the CPU 100.

As a result, the CPU 100 easily operates the output signal group S17.

10 illustrates a detailed structure of the output control circuit 150. As shown in FIG.

As shown in FIG. 10, the output control circuit 150 includes the memory storage command register 151, the CPU command register 152, the bit write decoder 153c, the CPU bit data aligner 153d, and the memory storage write. It consists of a decoder 153a, an mnemonic storage bit data aligner 153b, an output adjustment circuit 153e and an output register 154. The CPU command register 152 is connected to the CPU 100 through the system bus BO. The output control command is applied to the association memory command register 151 through the output control command bus S16. The output control command described above is composed of 8 bits (OSD7-OSD0) of the output signal value (OSD) and 2 bits of the output control mode (OCM) as shown in detail in FIG. An output control mode (OCM) of (0, 0) with 8-bit parallel output is obtained. The output signal value OSDi (i is an integer selected from 0-7) is set to the bit PSi corresponding to the output register 154 to be transmitted.

When the output control mode (OCM) is (0, 1), a parallel output with two sets of parallel output 3-bit enable is obtained. The output signal value OSDi (i is an integer selected from 0-2) is only set to the bit PSi corresponding to the output register 154 when the output signal value OSD3 is one. The output signal value OSDi (i is an integer selected in 4-6) is set only to the bit PSi corresponding to the output register 154 when the output signal value OSD7 is one. 6 PWM pulses that require control of all the space vector three-phase inverters described above are co-converted modes, or three PWM pulsos that require control of a three-phase 120-degree energized brushless motor inverter It is a three-signal mode to allocate, and an electricity supply phase is transmitted jointly. When the output control mode OCM is (1, 0), a parallel output with two sets of 2-bit enable is obtained. The output signal value OSDi (i is 0 or 1) is set to the bit PSi corresponding to the output register 154 only when the output signal value OSD3 is 1 to be transmitted. The mode described above is a mode when the DC motor drive circuit is controlled by the H-type arm. In the H-arm drive circuit, two signals, 2 PWM pulses or 4 PWM pulses, pointing in the energizing direction are transmitted in common. The output signal value OSDi (i is 4 or 5) is set to the bit PSi corresponding to the output register 154 only when the output signal value OSD7 is 1 to be transmitted. When the output control mode OCM is (1, 1), the signal output allocated to the 1-bit position is obtained. The exclusive OR of the output signal value OSD7 and the rising signal S18 correspond to positions defined according to 0-7 given from the output signal values OSD7, OSD6, OSD5 of the output register 154 for transmission. Bit PSi. The above-described mode is provided for the purpose of maintaining the conventional general assignment function of the output terminal of the PWM pulse output circuit.

The two bits OCM1 and OCM0 of the output control mode of the above-described output control command are output signal values (OSD) separated within the recording signal BWam 7-0 in units of 1 bit by the mnemonic storage bit write decoder 153a. The output is enabled in accordance with the output control mode. Similarly, the output control commands recorded in the CPU command register 152 through the system bus BO are distinguished in the write signal BWcpu 7-0 in units of 1 bit by the CPU bit write decoder 153c. The CPU bit data aligner 153d produces an output value with data (ODcpu 7-0) corresponding to the desired output position. At this time, the output value is not inverted by the rising signal S18. The output adjustment circuit 513e is made in accordance with an instruction from the CPU 100 in units of one bit, and its output is obtained in accordance with an instruction from the parallel comparison type memory device 140. Interruption in an arbitrary signal in accordance with an instruction from the CPU 100 is made at a random time for the normal occurrence of a pulse by the parallel comparison type memory device 140. Therefore, it is possible to change the PWM pulse that occurs accidentally during the control of the device.

When the output signal reset bit OSR of the control register 110 is 1, all the bits of the output register 154 are reset. As a result, the motor stops suddenly.

12 and 13 illustrate time charts of operations for generating PWM pulses according to this embodiment. 12 illustrates the case where the sawtooth carrier is selected by obtaining the carrier waveform select bit CWS of the control register 110. In order to provide the silver delay time, it is necessary to send it as a drive signal for the inverter, the output signal PSO is a PWM pulse, the silver delay time is set to deck # 7, and the output signal PSO is set to 1. The command is set as its output control command. Furthermore, the off-time of the output signal PSO is set to deck # 0 in order to obtain the output signal PSO for returning to 1 according to the pulse width obtained from the control operation. The above-described setting is written in the output time master register # 0 in each control cycle to copy to the output time slave register # 0 at the same time as the completion of the last PWM cycle in the control cycle.

According to this embodiment, the random copy enable bit RCE of the control register 110 becomes 1 by the CPU 100 after completion of the control operation, so that the copy in each control period is commanded. According to this method, the periodic radiation enable unit PCE and the divider circuit 620 can be omitted from the structure when the control period is two or three times the PWM period. The result is a smaller circuit. Since the difference in control operation time is 30% or less regardless of whether the control operation time is the shortest time or the longest time, the random enable enable bit (RCE) can be set to 1 in the same PWM period. The random copy enable bit (RCE) is reset and automatically arranged at the same time as the copy operation because the load applied to the CPU is reduced.

The reflection processing is described in the control calculation result with the output signal.

For example, the control operation result TO (j) in the j · th control period is written to the output time dependent register # 0 in the k-1-th internal timer period. In accordance with the copy instruction from the CPU 100 in the above described timer period, at the same time as the end of the above described copying period, the copying path 130 is copied to the output time dependent register # n0 (indication # 0). It is reflected by the output signal PSO in j + 1 th control period. For example, display # 0 coincides at time ta in the k-th timer period in the above-described period because the output signal PSO returns to zero.

13 illustrates the case of the sawtooth carrier selected by having the carrier waveform selection bit CWS of the control register 110.

In this case, the output control mode OCM of the output control command obtains a signal output together with a command for setting the first bit to '1'.

As a result, the output value is inverted by the rising signal S18. Therefore, display # 0 coincides with a double internal timer value T at times ta and tb within the k th timer period. The output signal PSO becomes 1 according to the output control command at time ta, and the output signal PSO becomes 0 which is opposite to the output control command according to the rising signal S18 at the time tb. As a result, the sawtooth carrier is formed by the inversion of the output control command by the rising signal S18.

According to this embodiment, the PWM pulses that generate the circuit required by the CPU in interruption by copying in each cycle are integer multiples of the PWM cycle when the interruption request is one. The CPU executes the control operation of the device in accordance with the interruption request. Therefore, the necessity of the control period interval timer for making the control operation period constant is eliminated according to this embodiment. The PWM pulse generated by the device according to the invention reduces the size of the sieve of the microcomputer for controlling the device.

According to this embodiment as shown in FIG. 1 as described above, the contents of the slave memory are always constant within the pulse period. Therefore, the wiring length becomes shorter, and as a result, the rotational area and the size of the design become smaller.

According to the above-described embodiment, the structure is arranged by the same means as the subprocessor 160 shown in FIG. 1 is stopped, and the CPU performs a function executed by the subprocessor 160. The following describes the function of subprocessor 160. The subprocessor 160 supplies / receives data from the CPU 100 via the system bus BO as shown in FIG.

Therefore, the order for calculating the output time data of the above-described output pulse is programmed or constituted by a logic circuit. In addition, the operation is performed by the subprocessor operation enable unit SPE of the control register 110 becoming one. Therefore, the load applied to the CPU 100 in the procedure for calculating the output time data is reduced. Thus, the throughput of the control calculation processing executed by the CPU 100 is improved.

According to the structure shown in FIG. 1, the subprocessor 160 accesses the output time master registers # 0-# 7 through the multiplexer 170. However, another structure shown in FIG. 14 is configured such that the subprocessor is accessed from the output time master registers # 0 to registers other than # 7 through the multiplexer 180 and the local bus B1. According to the above-described structure, the control pulse is processed simultaneously with the output pulses set from the control register 110 and the period register 122, and the output control master registers # 0- # 7 are also executed by the subprocessor 160, and as a result, the CPU The load applied to 100 is further reduced as compared to the structure shown in FIG. According to the embodiment shown in FIG. 14, the interruption signal S19 is applied to the subprocessor 160 to be processed simultaneously with the output pulse, and as a result, the interruption processing of the CPU 100 is performed by the subprocessor 160. Is executed.

The structure of subprocessor 160 is shown in FIG.

The subprocessor 160 includes a register group 161 composed of general registers # 0- # 7, and an operation unit 162 capable of performing logical and arithmetic operations on data stored in the subprocessor 160 and the register group 161. ) And a transmission control device for data transferred between the subprocessor 160 and other registers. Control of each device included in the subprocessor 160 is performed by a logic circuit or a control program included in each device. The control of each device described above consists of logical and arithmetic operations of data, is recorded in the register group 161 by the CPU, and controlled by execution by the arithmetic unit 162. Moreover, the transfer of the output time data is the result of the operation, and a register such as the origin time master register group is controlled by the transfer control device 153.

The control calculation processing capability of the CPU is enhanced by the processing dispersion by the division portion of the output time calculation operation of one pulse signal not related to another pulse signal. Moreover, the sufficient effect of reducing the loads of the CPU 100 can be obtained by the subprocessor 160 performing an operation related to the output time and the output time of two or more pulse signals can be obtained from different output time. As a detailed example of the above technique, a three-phase inverter, which is an electric converter for driving an electric motor, is controlled as shown in FIG. The three-phase inverter uses six PWM signals consisting of two signals for each phase to generate three-phase AC voltages, namely U, V, and W phases. Two PWM signals for each phase are formed by converting the polarity of the output signal. Here, it is necessary to lower the two PWM signals described above in a certain period because of the characteristics of the transistor for supplying electricity.

The output time of each PWM signal can be obtained by calculating specific time data and reference time data representing the average voltage of the two phases.

For example, in the case of the sawtooth PWM conversion carrier, the output time data TUa (i) and the output time data TUb (i) of the two U-phase PWMs are as follows: the reference time data is TU (i) The time can be expressed as a distinction between working hours DUa and DUb.

When the phase current of the U phase is positive;

Tua (i) = TU (i)

TUb (i) = TU (i) -DUb

When the phase current of the U phase is negative;

TUa (i) = TU (i) + DUa

TUb (i) = TU (i)

General purpose register # 0 is called the operation control register, general purpose register # 1 is the reference time data register, general purpose register # 2 is the work register (1), and general purpose register # 3 is the work register. (2) The CPU 100 not only records the reference time gate of U phase in the reference time data register, but also records information on the phase current value of the U phase in the operation control register in each control period. The subprocessor 160 executes the above-described calculation with the above-described equation according to the contents of the operation control register. The result of the above described operation is then stored in output time master register # 0 and output time master register # 1. As a result, it is determined whether the phase current in the CPU 100 is positive or negative, and the applied load is reduced at the time of calculating the output time data.

In addition, since the reference time data of each of the U, V, and W phases is three-phase AC voltage of zero, it can be obtained by trigonometric calculations of one reference time data and the phase angle of the voltage. The CPU 100 records phase angle data and phase current information of each phase in the operation control register.

Furthermore, the subprocessor 160 can calculate all six PWM signals by using the working time data 1 and 2, the preceding reference time data, and the above-described data. In accordance with the above-described operation sequence, the CPU 100 must be reloaded with only two registers, namely, the register and the reference time data register. Therefore, not only the load applied at the time of operation is reduced but also the load applied at the time of the transmission operation is also reduced.

FIG. 18 is a block diagram illustrating a pulse generator capable of controlling a switching element such as a bridge structure inverter using the functions of the subprocessor 160 described above. According to this embodiment, pulse pairs are generated by arranging such that the pulses have a constant time axis and a width, and their binary states are in a reverse complementary relationship (called reverse polarity). For example it makes it possible to generate gate pulses that drive the switching elements for the upper and lower arms of the inverter.

To construct the binary state of the signal at each point in time, four data items, consisting of a time meter for the first transition point and the last transition point of the data item and pulse, require one pulse. Therefore, the CPU 100 must transmit at least four data items per pulse to the register of the pulse generator. In the case of a three-phase inverter with a bridge construction to control the operation of the motor, gate pulses for the switching elements of the three-phase U, W, and Wx6 arms must be generated. Therefore, at least 24 data items must occur in the data item transfer. do. As a result, excess load is applied to the CPU 100 at the time of data transfer. In particular, when the frequency of the carrier wave rises at the time of control of the pulse width modulation PWM, the load in the transmission operation increases more.

Furthermore, when the upper and lower arms are complementarily turned on and off to prevent shorting of the upper and lower arms of the bridge structure, the gate pulse pairs corresponding to the upper and lower arms have dead time at which the upper and lower arms are turned off.

Therefore, a problem arises in that the load for the CPU 100 rises excessively at the time of calculating the dead time described above. Therefore, in the structure shown in FIG. 18, the number of data items is arranged so that each pulse pair needs to be generated so that a constant correlation is reduced. Furthermore, by performing an operation for controlling the time relationship (for example, dead time) between pulses at the first or the last conversion point, the load on the upper CPU 100 can be reduced.

In the attached FIG. 18, the control register 1, the reference time data register 2, the first and second working time registers 3 and 4, and the first and second status data registers 5 and 6 are connected to a bus ( 7) are connected to the upper CPU respectively. Each of the above-described registers corresponding to register group 161 is shown in FIG. 15 or FIG. Each of the registers described above is arranged to store control signals, reference time data T, first and second working time data T1 and T2, and state data DS transmitted from the upper CPU. The status data DS is transmitted in the initial setting and other data items are periodically transmitted in response to the count up signal as described later.

By the reference time data and the working time data T1 and T2 are drawn out by the twisting apparatus 8, the time data DT1 and DT2 are obtained from a predetermined calculation. Therefore, the time data DT1 and DT2 are transmitted to the first and second time data registers 10 and 11 by the transmission control device 9, respectively. The calculation device 8 and the transmission control device 9 corresponding to the calculation device 162 and the transmission control device 163, respectively, are shown in FIG. 15 or FIG.

The control signal includes a count control signal 12, an operation control signal 13, a transmission control signal 14 and an output switch control signal 15. The counter control signal 12 consists of a count up signal and a count up signal applied to the up / down counter 16 in a predetermined period. The up / down counter 16 is arranged to input the clock pulse CLK. The count value 17 of the up / down counter 16 is applied to the first and second comparators 18, 19. The comparator 18 compares the time data DT1 and DT2 of the time data registers 10 and 11. When the time data DT1 and DT2 coincide, the corresponding coincidence signals 20 and 21 are applied to the first and second pulse output registers 5 and 6. The pulse output registers 5 and 6 are arranged in the same structure consisting of flip-flops each having an output terminal (+) and an inverted output terminal (-) pair each having a complementary state. When state data is input, the inverted state of the state constituted by the state data is reset. The output terminal pair is connected to the output lines 24 and 25 of the pulses 1 and 2 via the output switches 22 and 23. By output switches 22 and 23 switching the above-described output switch control signal, a pulse of a desired polarity is obtained. According to this embodiment, the pulse 1 is set on the positive side and the pulse 2 is set on the negative side.

The operation of the structure constructed according to this embodiment will be described with reference to FIGS. 19 and 20. 20 is a schematic diagram of PWM pulses processed by the upper CPU. The upper CPU compares between the triangular carrier wave and the output voltage command of the inverter to obtain the reference pulse of the upper and lower arms. Then, the working time data is determined to widen the negative pulse and narrow the positive pulse according to the reference pulse obtained in consideration of the dead time described above. The above described operation is performed in each of phases U, V, and W. FIG. Then, the time T from the initial period T0 of the triangular wave to the first variation point of the reference pulse, the working time data T1 of the pulse for the upper arm, and the writing time data T2 of the pulse for the lower arm are obtained.

Furthermore, the above-described data, state data (positive or negative) of the upper pulse (or lower pulse) and control signals are transmitted to the pulse generator.

The above-described transmission is arranged to be executed at a limited time in response to the count-up signal transmitted simultaneously with the initial period of the above-described Samgalpa.

As described above, when data is transmitted to the pulse generator, the up / down counter 16 starts a counting operation. The counting operation starts by the up / down counter 16 being reset by the countdown signal stored in the control register 1 at half time of the period TO. The arithmetic unit 8 starts a calculation in response to the arithmetic control signal 13 in order to obtain time data DT1 and DT2 in a predetermined arithmetic order. Although various methods are applied to perform the above-described calculation, the method according to the present embodiment arranges to add the time data DT1 to the work time data T1 to obtain the time data DT1. The time data DT2 is obtained by subtracting the work time data T2 from the reference time data T. Thus, the obtained time data DT1 and DT2 are transmitted to the time data registers 10 and 11 by the transmission control device 9, respectively, in accordance with the reference time and the position transmitted by the transmission control signal 14 instruction. The computing device 8 and the transmission control device 9 can be constituted by a simple microprocessor. In this case, the arithmetic processing and transmission control described above are performed in accordance with a program. As a result, the control signal given from the upper CPU can be simplified. However, the present invention is not limited to the above described configuration. The above-described calculation and control of data transfer indicate that hardware can be realized.

When the time data DT1 and DT2 are stored in the time data registers 10 and 11, the comparators 18 and 19 compare the count values produced by the up / down counter 16. When the time data and the count value coincide with each other, the coincidence signals 20 and 21 are transmitted to the output registers 5 and 6, respectively. As a result, the flip-flops of each of the pulse output registers 5 and 6 are set so that the output line 24 is converted into the positive polarity and the output line 25 is converted into the negative polarity through the output switches 22 and 23.

The counter 16 is switched to the countdown mode. When the count value again matches the time data DT1 and DT2, the coincidence signals 20 and 21 are transmitted. As a result, the Phillip flop of each of the pulse output registers 5 and 6 is reset so that each polarity of the output lines 24 and 25 is switched.

Therefore, preferable pulses 1 and 2 are obtained.

As described above, in accordance with this embodiment, a pulse pair of complementary relations consisting of a negative pulse and a positive pulse larger than the width of the positive pulse is generated, and the data items DT1 and DT2 are in their relation by the associating device 8. This is derived from the two working data items shown and the reference time data defining the time axis of the pulse pair. Furthermore, the count value obtained from the up / down counter 16 and the obtained data items DT1 and DT2 are compared, thus defining the first and last conversion points.

Therefore, the number of data items must be transmitted from the CPU so that one can be reduced in each pulse pair. Therefore, in the three-phase device, three transmission data are reduced.

Moreover, the two states of the pulse are defined by arranging the two output registers in a complementary relationship. Therefore, the upper CPU should send only one status data item. Thus, in the case of a three-phase device, the number of data items transmitted is reduced by three.

In addition, since the dead time is calculated by the pulse generator, the load applied to the upper CPU at the time of the data transfer operation described above is reduced. Moreover, the load applied at the time of the calculation operation is also reduced.

In addition, since the up / down counters are employed in the configuration, the first and last transition points of the pulse are limited only by the time data. Therefore, the calculation executed by the computing device 8 becomes thin.

In addition, the pulse output registers 5 and 6 have complementary output terminal pairs, and the two states of the pulses are selected by the output switches 22 and 23. Therefore, the present invention can be applied to a pulse generator in addition to a device for generating switching pulses for the upper and lower arms of the inverter. Thus, it has sufficiently wide versatility.

The method of determining the working time data for widening the negative pulse and narrowing the positive pulse in consideration of the dead time described above can be changed as shown in FIGS. 21, 22, and 23 in addition to the embodiment shown in FIG. have.

21 illustrates a structure in which the first variation point of each of the negative and positive pulses delayed with respect to the reference pulse is provided by providing the dead time. Thus, the computing device 8 operates to obtain T + T1 and T-T2 similarly to the first embodiment. However, T + T1 and T are processed to form a set as time data DT1, and T and T-T2 are processed to form a set as time data DT2.

The transmission control device 9 transmits T to the time data register 11 and transmits T + T1 to the time data register 10 simultaneously with the count up signal. Moreover, the transmission control device 9 transmits T-T2 to the time data register 11 and transmits T to the time data register 10 at the same time as the countdown signal. As a result, pulses (1) and (2) shown in the figure are transmitted.

FIG. 22 illustrates an arrangement structure in which the last conversion point of each of the delayed negative pulses and the positive pulses is delayed with respect to the reference voltage, and as a result, the necessary dead time is provided.

FIG. 23 illustrates an arrangement structure in which the last transform point of the negative pulse is moved forward and the first transform point is delayed because both pulses coincide with the reference pulse.

24 is a timing chart of another embodiment of the present invention.

The difference between this embodiment and the first embodiment is that a prune counter is used instead of the up / down counter 16. According to this embodiment, the functions and operations of the computing device 8 and the transmission control device 9 are different from those of the computing device and the transmission control device in the first embodiment. Operation according to this embodiment will be described with reference to FIG. 24 illustrates a pulse similar to that of FIG. 19. FIG. The data transmitted from the upper CPU is almost the same as the transmitted data shown in FIG. The command given to the principal counter is in the form of a reset signal simultaneously with the carrier wave period. The transmission control device 9 is arranged to input the transmission control signal 14 and the above-described reset signal in a half cycle of the carrier signal cycle (corresponding to the countdown signal described above). When each data item is transmitted, the associative control device 8 operates to obtain one set of T + T1 and T0- (T + T1) as the time data DT1, and also one set of time data DT2. It operates to get T-T2 and T0- (T-T2). The operation control device 8 then transfers the time data obtained to the time data registers 10 and 11 in accordance with the above-described transfer timing. Accordingly, pulses 1 and 2 shown in FIG. 19 occur.

Although omitted from the above description, this embodiment allows the generation of modified pulses as shown in FIGS. 21, 22 and 23 degrees.

As described above, according to the embodiment shown in FIG. 18, the following effects can be obtained.

The time data consisting of the first and last transition points of the pulse pair is obtained by the computing device using the working time data item pair and one reference time data item. Thus, the obtained data item is stored in a pulse output register pair. If the comparator determines that the count value coincides with the first conversion time data, the output terminal of the first output pulse register converts to the indicated binary state (positive or negative). The first output pulse register output terminal is then reset when the counted data matches the last conversion time data. The output terminal of the second pulse output register operates in reverse to the first pulse output register. Therefore, pulse pairs having such a pattern are suitable for driving switching elements for the upper and lower arms which complementarily operate. Therefore, the load applied to the upper CPU at the time of data transfer operation decreases. Furthermore, the load on the CPU is reduced because the upper CPU is free from the necessity of computation execution to controlling the time difference between the pulse pairs.

In addition, if the configuration consists of up / down counters, the first and last transition points of the pulse are controlled by one time data item by the counter to perform up-reset and down-reset operations according to the PWM carrier wave period. do.

If the working time data for another pulse coincides with the above-mentioned reference time data, the reference time data register or the first working time data register is omitted, and one data item transmitted is reduced.

Furthermore, each pulse output register described above is arranged with a conversion output terminal and maintains the conversion state of the above described output terminal. Furthermore, an output switch is provided for selecting either the conversion output terminal or the output terminal of the above-described pulse output register.

Thus, each switch is controlled in response to an output switch control signal stored in the above-described control register. Thus the polarity of the generated pulses has a sufficiently wide versatility.

The configuration of an embodiment in the pulse generator according to the present invention used as a device for controlling an electric motor will be described with reference to FIG. 25 and FIG.

According to this embodiment, the above-described dead time providing means is selected according to the direction (polarity) of the load current flowing through the motor.

According to this embodiment, the operation of the electric motor 31 is controlled by the voltage inverter 30. The voltage inverter 30 has switching elements 34a, 34b, 35a, 35b which are switched on / off in response to a pulse transmitted from the inverter controller 33. The inverter controller 33 is composed of a CPU and a pulse generator. The pulse generator generates the pulse described above by the control applied from the CPU. The inverter controller receives the load currents 38a, 38b, 38c of each phase, the magnetic pole position signal of the electric motor, and the rotation direction detection signal from the rotation detector 39.

26 shows the configuration of the pulse generator 33. The PWM pulse generation method is the same in the apparatus according to this embodiment, so only one phase is described. If one of the switches for the upper and lower arms is turned off and the other is turned on at the same time, the arm of the arm is turned off due to the predetermined time during which the on / off operation of controlling the motor is performed in the voltage inverter used as shown in FIG. Short cuts occur. Dead time should be provided in the upper and lower arms to be turned off to prevent short cuts of the arm. The inverter control device 33 draws out a motor current, a magnetic pole position, and a rotation direction in order to perform calculation of the CPU. The CPU calculates the speed of the motor to obtain reference time data T which is data on the duty of the pulse signal corresponding to the deviation between the indicated speed and the detected speed. In addition, the CPU calculates dead time data T1, dead time data T2, and state data DS necessary to generate dead time. In addition, the CPU determines the direction of the current in order to generate the operation and control signal 13, determines the transmission control signal 14 and the data working method in the operation device 8, and executes in the transmission control device 9 Instructs the timing and successive instructions of the completed data transfer. Finally, the CPU stores the reference time data T in the reference time data register 2, stores the dead time data T1 in the work time register 3, and stores the dead time data T2 in the work time register ( 4) and each control signal is stored in a control register. Data stored in each register is subtracted and added by the computing device 8 in accordance with the method indicated by the control signal.

Dead time is provided according to this embodiment by the three methods of switching shown in FIGS. 19, 21 and 22.

The first method arranges so that the first transition point of each of the positive and negative pulses is delayed relative to the reference pulse, while the last transition point of each of the positive and negative pulses is moved forward. In the second method, only the first transition point of each positive and negative pulse is delayed with respect to the reference pulse. In the third method, only the last transition point of each of the positive and negative pulses is moved forward with respect to the reference pulse. The time data obtained in each of the above-described methods is transmitted to the transmission control apparatus 9 for transmission to the time data REG 40 at the timing by the transmission control signal applied from the CPU. The time data sent to the time data REG 40 is immediately compared with the counter value by the counter 16 in the comparator 42. At this time, when the time data and the count value coincide with each other, the binary PWM pulses 1-6 are transmitted from the output switch 43 according to the state data stored in the state data REG 41. Therefore, the electric motor 31 is controlled.

The output voltage within the dead time changes due to the direction of the load current. For example, in the case of the second method, when the load current flows toward the load, the output voltage (point a) decreases in an amount corresponding to the latch portion with respect to the reference pulse. On the other hand, in the case where the load current flows from the motor to the inverter, the output voltage rises by an amount corresponding to the latch portion with respect to the reference pulse. Therefore, if the dead time installation method is limited to only one method, the above-described error voltage is generated. As a result, a problem arises in that control precision is lowered without a desired output voltage.

Thus, in this embodiment, the three methods described above are configured to be switched in accordance with the method of load current. The CPU determines the direction of the load current to select a method in which the above-described error voltage does not occur. The operation control signal is transmitted to the operation control device 8.

FIG. 29 is a time chart of operations executed by the CPU in accordance with the embodiment shown in FIG. The CPU of the inverter controller 33 draws out data concerning the electric current, the rotational direction and the magnetic pole position for performing the control operation. In the control operation, the speed of the motor is controlled as shown in FIG. 29, and the reference time data, which is data for duty-limiting the pulse signal corresponding to the deviation between the indicated signal and the detected signal, is calculated (step 51). Thereafter, working time data T1 and T2 which generate dead time for preventing short cuts of the upper and lower arms of the voltage inverter 30 are generated (step 52). Furthermore, the direction of the current is determined to generate an operation control signal for determining the working method (step 53). The CPU stores the reference time data in the reference time data register 2, stores the working time data T1 and T2 in the working time data registers 3 and 4 and stores the control signal in the control register 1 ( Step 54.)

Therefore, time data for obtaining the desired PWM signal is generated by subtracting or adding the working time data T1 and T2 and the reference time data in the computing device 8 (step 55), and are transmitted to the time data REG 1-6 ( Step 56). Therefore, the load applied to the CPU at the time of operation according to this embodiment is reduced by the function of the computing device 8.

Although the invention has been described in certain forms with particular specificity, the claims herein are intended to be construed as an expression of the invention in its preferred form, with some arrangement and combination altered in detail, without departing from the scope and spirit of the invention. You will have to understand.

Claims (72)

Generates a timer value of a setting pattern that is continuously changed in synchronization with a clock signal by a timer period defined by an externally given control command, and simultaneously whenever the timer value matches a value appearing at the end of the timer period. A time interval timer having timer calculating means for generating a signal and resetting the timer value; Copyable means for receiving said synchronization signal transmitted from said time interval timer and transmitting a copyable signal in response to a set synchronization signal included in said synchronization signal; An output time master memory for storing time data for an externally supplied output pulse, and an output time slave memory for copying and storing the time data of the output time master memory in response to the copyable signal, A comparator for comparing the time data of the output time master memory or the output time slave memory with the timer value of the timer register according to an external command of the memory, and if the values coincide with each other, transmitting a matching signal; An output control memory for storing an output control command defining a binary state of the output pulse supplied from the outside in response to the copyable signal to transmit a command, and the output in synchronization with the match signal sent from the comparator A control memory and the memory device And an output control circuit for receiving the transmitted control command and transmitting an output pulse in response to the output control command. A pulse generating apparatus according to claim 1, wherein the output control memory is configured to transmit a corresponding output control command of an output control master memory or an output control slave memory in synchronization with the coincidence signal transmitted from the comparator. An output control master memory for storing an output control command defining a binary state of the output pulse supplied from the outside in response, and an output control slave memory for copying and storing the output control command from the output control master memory. Pulse generator, characterized in that. The pulse generating device according to claim 1, wherein the copyable means generates the copyable signal when the synchronization signal is supplied by a predetermined number of times. The pulse generating apparatus according to claim 1, wherein the copyable means operates in response to a copy control command supplied from the outside and is synchronized with the registered signal supplied immediately after the copy control command is supplied. Pulse generator, characterized in that for generating. A pulse generating apparatus according to claim 1, wherein said memory is provided with a plurality of said output time master memory, said output time slave memory and said comparator, said plurality of output time master memory, output time slave memory and comparator. Each of the plurality of tag memory cells, each of which is configured to constitute one of a plurality of tag word cells, further includes a plurality of the output control master memory and the output control slave memory, and the plurality of output control master memory and the output control slave memory. Wherein one of the memories is collected to constitute a plurality of output data word cells, and each of the tag word cells and the output data word cells are provided to correspond differently. 6. The pulse generating device according to claim 5, wherein each comparator of the memory device compares the timer value and each output time master memory or each output time slave memory in parallel according to a given parallel comparison command. And sequentially comparing the timer value with a specific output time master memory or a specific output time slave memory according to a given sequential comparison command. The pulse generating apparatus according to claim 1, wherein the time interval timer comprises a timer register for storing the timer value, a period register for storing a maximum timer value for designating a period of the output pulse, and the timer. An adder for adding a unit amount 1 to the timer value such that the calculating means draws out the timer value of the timer register and transfers the value to the timer register, the value of the timer register value and the period register coincide with each other; A comparator for comparing the values so as to transmit a coincidence signal, a clear circuit for receiving the coincidence signal to clear the adder, and for generating a synchronizing signal in synchronization with the clock signal under the condition that the coincidence signal is generated. Pulse generation, characterized in that it comprises a synchronization signal generation circuit Device. A pulse generating apparatus according to claim 1, wherein the time interval timer comprises a timer register for storing the timer value, a period register for storing a maximum timer value for designating a period of the output pulse, and the timer. An adder / subtractor for adding or subtracting a unit amount 1 to the timer value according to a given add / subtract instruction to have the computing means fetch the timer value of the timer register and send it to the timer register, the timer of the timer register A comparator for comparing the values to transmit a coincidence signal when the value and the timer value of the periodic timer coincide with each other. If a coincidence signal is generated in the comparison, Addition / subtraction command means, a pulse generating circuit comprising: a synchronizing signal generation circuit for generating a synchronizing signal to the timer value is synchronized with the clock signal conditions the spirit of the timer register for. The pulse generating apparatus according to claim 1, wherein the time interval timer comprises a timer register for storing the timer value, a period register for storing a maximum timer value for designating a period of the output pulse, and the timer. A comparator for comparing the values so that the operation means transmits a coincidence signal if the timer value of the timer register and the timer value of the period register match, and for detecting when the timer value of the timer register becomes 0/1. 0/1 detector, when the timer value of the timer register becomes 0, add / subtract command means for transmitting a subtract command when the match signal is generated in the comparator, and extract the timer value of the timer register. Given from the add / subtract command means to transfer to the timer register An adder / subtracter for adding or subtracting a unit amount 1 from the timer value according to the add / subtract command, the adder if the control command of an external timer value pattern is a sawtooth waveform and the match signal is transmitted from the comparator And a clearing circuit for clearing the subtractor and a synchronizing signal generating circuit for generating a synchronizing signal in synchronism with a clock signal on condition that said timer value of said timer register becomes zero. A central processing unit (CPU) for computing an output control command for defining a binary state of an output pulse and a pulse control command including time data for defining a change timing of the binary state; Start the operation according to the operation start command provided from the CPU, generate a setting pattern timer value that is continuously changed in synchronization with a clock signal by a timer period defined by the control command provided from the CPU, and generate the timer value. A time interval timer for transmitting a synchronization signal whenever the value coincides with a value appearing at the end of the timer period, and for setting the timer value; Copyable means for receiving said synchronization signal transmitted from said time interval timer and transmitting a copyable signal in response to a setting synchronization signal of said synchronization signal; An output time master memory for storing the time data for the output pulse transmitted from the CPU, an output time slave memory for copying and storing the time data of the output time master memory in response to the copyable signal; Comparing the timer value of the timer with the time data of the output time master memory or the output time slave memory according to a command of a memory to be compared and provided from the CPU and transmitting a coincidence signal when the values coincide with each other. An output control defining a binary state of the output pulse provided from the CPU in response to the copyable signal to transmit a corresponding output control command of the output control memory in synchronization with the match signal sent from the comparator Output control memory for storing commands An associative memory device provided with; And an output control circuit for receiving the output control command sent from the memory device and transmitting an output pulse corresponding to the output control command. A microcomputer according to claim 10, wherein the output control memory is responsive to the copyable signal to transmit a corresponding output control command of an output control master memory or an output control slave memory in synchronization with the match signal sent from the comparator. An output control master memory for storing an output control command defining a binary state of the output pulse provided from the CPU and an output control slave memory for copying and storing the output control command from the output control master memory. Microcomputer characterized in that. A microcomputer according to claim 10, wherein the copyable means generates the copyable signal when the synchronization signal is supplied by a predetermined number of times. A microcomputer according to claim 10, wherein the copyable means operates in response to a copy control command supplied from the CPU and generates the copyable signal in synchronization with the synchronization signal supplied immediately after the copy control command is provided. Microcomputer characterized in that. 12. A microcomputer according to claim 10, comprising: a plurality of said output time master memory, said output time slave memory and said comparator in said associative storage device, said plurality of output time master memory, output time slave memory and comparator One is collected so as to constitute a plurality of tag word cells, and the memory device further has a plurality of the output control master memory and the output control slave memory, and the plurality of output control master memory and the output control slave memory. And each of the tag word cells and the output data word cells are provided to correspond differently to each other to constitute a plurality of output data word cells. 15. A microcomputer according to claim 14, wherein each comparator of said memory is compared in parallel with said timer value and each said output time master memory or each said output time slave memory in accordance with a given parallel comparison command. And sequentially comparing the timer value with a specific output time master memory or a specific output time slave memory according to a given sequential comparison command. 11. The microcomputer according to claim 10, wherein the time interval timer comprises a timer register for storing the timer value, a period register for storing a maximum timer value for the output pulse to specify a period, and the timer operation. An adder for adding a unit amount 1 from the timer value so that means draws the timer value from the timer register and sends the value to the timer register, the value of the timer register coinciding with the value of the periodic register A comparator for comparing the values so as to transmit a coincidence signal and a clear circuit for receiving the coincidence signal to clear the adder, and for generating a synchronizing signal in synchronization with the clock signal under the condition that the coincidence signal is generated. E) comprising a synchronization signal generating circuit; Microcomputer. The microcomputer according to claim 10, wherein the time interval timer comprises a timer register for storing the timer value, a period register for storing a maximum timer value for designating a period of the output pulse, and the timer operation. An adder / subtractor for adding or subtracting a unit amount 1 to the timer value in accordance with a given add / subtract instruction for means to retrieve the timer value of the timer register and to transmit the value to the timer register; A comparator for comparing the values so as to transmit a coincidence signal when the value of and the period register coincide with each other. And the match signal is generated by the comparator. Micro characterized in that the addition / subtraction command means, and in synchronization with the clock signal conditions the timer value of the timer register zero for transmitting a subtraction command including the synchronizing signal generation circuit for generating a synchronizing signal computer. The microcomputer according to claim 10, wherein the time interval timer comprises a timer register for storing the timer value and a period register for storing a maximum timer value for designating a period of the output pulse, the timer operation Means for comparing the values so that the means transmits a coincidence signal when the timer value of the timer register and the value of the period register coincide with each other, and 0 for detecting whether the timer value of the timer register is 0/1. / 1 add and subtract command means for transmitting an add command if the timer value of the detector and the timer register is zero and a subtract command if the coincidence signal is generated in the comparator, and withdraw the timer value of the timer register. Add / subtract to send the value from the timer register An adder / subtracter for adding or subtracting the unit amount 1 from the timer value according to the addition / subtraction command given from the command means, and the control command of the timer value waveform provided from the CPU is sawtooth waveform and the coincidence signal is And a clear signal for clearing the adder / subtractor when transmitted from the comparator, and a synchronization signal generation circuit for generating a synchronization signal in synchronization with a clock signal under the condition that the timer value of the timer register becomes zero. Microcomputer. 11. The microcomputer according to claim 10, wherein a control instruction calculation period is made in the CPU to the output pulse so as to coincide with a copying period of the memory device. A central processing unit (CPU) for calculating a binary state of an output pulse and a pulse control command to define the timing of change of the binary state; A subprocessor connected to the CPU via a system and calculating time data of the change timing of the binary state of the output pulse in accordance with the pulse control command provided from the CPU, and starting operation provided from the CPU or the subprocessor Start an operation according to a command, generate a predetermined pattern timer value according to the timer period defined by the control command and sequentially change in synchronization with the clock signal, wherein the timer value appears at the end of the timer period. A time interval timer for transmitting a synchronization signal and resetting the timer value if it coincides with; Copyable means for receiving the synchronization signal transmitted from the time interval timer and transmitting a copyable signal in response to a predetermined synchronization signal of the synchronization signal; An output time master memory for storing the time data for an output pulse transmitted from the CPU or the subprocessor, an output time slave for copying and storing the time data of the output time master memory in response to the copyable signal Compare the timer value of the timer register with the time data of the output time master memory or the output time slave memory according to a command of a memory and a memory to be compared and provided from the CPU, and transmit a coincidence signal when the values coincide with each other. An output defining a binary state of the output pulse provided from the CPU in response to the copyable signal to transmit a corresponding output control command of an output control memory in synchronization with the match signal sent from the comparator To store control commands Associative memory device having an output control memory; And an output control circuit for receiving the output control command sent from the memory device. 21. A microcomputer according to claim 20, wherein said output control memory is responsive to said copyable signal for transmitting a corresponding output control command of a slave memory at an output control master memory or an output in synchronization with said coincidence signal transmitted from said comparator. An output control master memory for storing the output control command defining a binary state of the output pulse provided from the CPU and an output control slave memory for copying and storing the output control command from the output control master memory. Microcomputer, characterized in that consisting of. A microcomputer according to claim 20, wherein the copyable means generates the copyable signal when the synchronization signal is provided by a predetermined number of times. 21. The microcomputer according to claim 20, wherein the copyable means operates in response to a copy control command provided from the CPU or the subprocessor and sends the copyable signal in synchronization with a synchronization signal applied immediately after the copy control command is provided. A microcomputer characterized in that it occurs. 21. The microcomputer according to claim 20, wherein the memory device comprises a plurality of the output time master memory, the output time slave memory and the comparator, wherein the plurality of output time master memory, output time slave memory and comparator One is collected so as to constitute a plurality of tag word cells, and the memory is further provided with a plurality of the output control master memory and the output control slave memory, wherein the plurality of output control master memory and the output control slave memory; And one is collected to constitute a plurality of output data word cells and each of the tag word cells, and the output data word cells are provided to correspond differently. 25. The microcomputer according to claim 24, wherein each comparator of said associative storage device paralleles said timer value and each said output time master memory or each said output time slave memory in accordance with a parallel comparison command given from said CPU. And comparing the timer value with a specific output time master memory or a specific output time slave memory according to a given sequential comparison command. 21. The microcomputer according to claim 20, wherein the time interval timer comprises a timer register for storing the timer value, a period register for storing a maximum timer value for designating a period of the output pulse, and the timer operation. An adder for adding a unit amount 1 from the timer value such that means draws out the timer value of the timer register and sends the value to the timer register, the value of the timer register coinciding with the value of the period register A comparator for comparing the values so as to transmit a coincidence signal, a clear circuit for receiving the coincidence signal to clear the adder, and for generating a synchronizing signal in synchronization with the clock signal under the condition that the coincidence signal is generated. E) comprising a synchronization signal generating circuit; Microcomputer. 21. The microcomputer according to claim 20, wherein the time interval timer comprises a timer register for storing the timer value and a period register for storing a maximum timer value for designating a period of the output pulse, the timer operation An adder / subtractor for adding or subtracting a unit amount 1 to the timer value according to an add / subtract instruction given by means for retrieving the timer value of the timer register and transmitting the value to the timer register; A comparator for comparing the values to transmit a coincidence signal when the value of and the period register coincide with each other, and if the timer value of the timer register becomes zero according to an instruction issued by the CPU or the subprocessor, the adder / An addition command is sent to the subtractor and the coincidence signal is And a synchronizing signal generating circuit for generating a synchronizing signal in synchronism with the clock signal on the condition that the timer value of the timer register becomes zero when the comparator generates the subtracting command. Microcomputer. 21. The microcomputer according to claim 20, wherein the time interval timer comprises a timer register for storing the timer value and a period register for storing a maximum timer value for designating a period of the output pulse, the timer operation Means for comparing the values so that the means transmits a coincidence signal when the timer value of the timer register and the value of the period register coincide with each other, and 0 for detecting whether the timer value of the timer register is 0/1. / 1 addition and subtraction command means for transmitting an addition command if the timer value of the detector and the timer register is zero and for transmitting a subtraction command if the coincidence signal is generated in the comparator, and withdrawing the timer value of the timer register. Add / subtract to send the value from the timer register The control command of the timer value waveform provided from the CPU or the subprocessor and the adder / subtracter for adding or subtracting the unit amount 1 from the timer value according to the addition / subtraction command given from the command means is a sawtooth waveform and the A clear circuit for clearing the adder / subtractor when a coincidence signal is transmitted from the comparator and a sync signal generation circuit for generating a sync signal in synchronization with a clock signal on condition that the timer value of the timer register becomes zero. Microcomputer featured. 21. The microcomputer according to claim 20, wherein the output pulse in the CPU is such that a control instruction calculation period is matched with a copy period of the mnemonic storage device. An output time master memory for storing time data for an externally provided output pulse, and an output time slave memory for copying and storing the time data of the output time master memory in response to a copyable signal; A comparator for comparing the timer value of the timer register with the time data of the output time master memory or the output time slave memory according to an external command, and transmitting a match signal when the values coincide with each other; An output control command that defines a binary state of the output pulse provided from the outside in response to the copyable signal to transmit a corresponding output control command of an output control memory in synchronization with the clock signal on a condition that the timer value of is equal to zero; Control menu to save data Reminiscent memory device including Mori. 31. An associative memory device according to claim 30, wherein said output control memory transmits a corresponding output control command of an output control master memory or an output control slave memory in synchronization with a clock signal on condition that said timer value of said timer register becomes zero. An output control master memory for storing an output control command that defines a binary state of the output pulse provided externally in response to said copyable signal and an output for copying and storing said output control command from said output control master memory; An associative memory device, comprising a control slave memory. 31. An associative memory device according to claim 30, wherein a control command calculation cycle of said output pulse in said CPU is made coincident with a copy cycle of said memory device. An output time master memory for storing time data for an externally provided output pulse, and an output time slave memory for copying and storing the time data of the output time master memory in response to a copyable signal; A comparator for comparing the timer value of the timer register with the time data of the output time master memory or the output time slave memory according to an external command and transmitting a match signal when the values coincide with each other; An output control command that defines a binary state of the output pulse provided from the outside in response to the copyable signal to transmit a corresponding output control command of an output control master memory or an output control slave memory in synchronization with the matched signal. Output control And an output control slave memory for copying and storing said output control command from said master memory and said output control master memory. 34. An associative storage device according to claim 33, wherein said associative storage device comprises a plurality of said output time master memory, said output time slave memory and said comparator, said plurality of output time master memory, output time slave memory and comparator Is collected so as to form a plurality of tag word cells, and the memory device further comprises a plurality of the output control master memory and the output control slave memory, wherein the plurality of output control master memory and the output control slave memory. Wherein one is collected to constitute a plurality of output data word cells and each of the tag word cells, and the output data word cells are provided so as to correspond differently. A reference time data register for storing reference time data to define a time axis of a pair of pulses to be generated; First and second working time data registers for respectively storing working time data representing a time relationship of each of said pulses with respect to said reference time data; First and second pulse output registers, respectively, for storing state data specifying one binary state of said pulse pair; A control register for storing a control signal; A counter for counting clock pulses; An arithmetic unit for retrieving the reference time data and each of the working time data such that each pulse can obtain the time data for the first transform and the last transform in a mathematical formula; A transmission control device for controlling the transmission timing of the time data of each of the pulses obtained by the computing device; First and second time data registers for storing the time data of each pulse transmitted from the transmission control device, respectively; First and second comparators for comparing the values of the counter and the values of each of the time data registers to transmit a match signal when the time data coincide with each other; Executes a defined operation in response to a stored operation control signal, the transmission control device controls the transmission timing of each of the time data in response to a transmission control signal stored in the control register, and transmits the first pulse output register Has an output terminal reset to a binary state executed by inverting the storage state data, the second pulse output register has an output terminal reset to a binary state of the storage state data, and If one coincidence signal is provided from the comparator corresponding to the first and second pulse output registers, Inverting the binary states respectively and providing the next coincidence signal resets the binary state of the output terminal, the counter is reset in response to a reset signal periodically stored in the control register, and the reference time data And each of the working time data, the top data and the control signal are applied from the outside according to the transmission period of the count-up reset signal of the counter. 36. A pulse generating apparatus according to claim 35, wherein each of said pulse output registers has an inverting output terminal in which the output terminal is kept in an inverted state. 36. A pulse generating apparatus according to claim 35, wherein an output switch for selecting one of said output terminal and said inverting output terminal of each said output pulse register is provided, and each said switch is controlled to an output switch stored in said control register. Pulse generator characterized in that the control in response to the signal. 36. A pulse generator according to claim 35, wherein said counter is a free run counter. 39. A pulse generating apparatus according to claim 38, wherein the arithmetic unit adds the first working time data to the reference data and the 1Ath time data, and the 1Bth time data to subtract the 1Ath time data from the period of the reset signal. Obtain 2Ath time data which subtracts 2Ath time data from the reference time data and 2Bth time data which subtracts 2Ath time data from the period of the reset signal, and the transmission control device responds to the reset signal in response to the reset signal. Transmitting the 1Ath and 2Ath time data to a second time data register and transmitting the 1Bth and 2Bth time data to the first and second time data registers according to a half period of the period of the reset signal. Pulse generator characterized in that. 39. A pulse generating apparatus according to claim 38, wherein the arithmetic unit is 1Ath time data for adding the first working time data to the reference time data, and 1Bth time for subtracting the reference time data from the period of the reset signal. 2Bth time data for subtracting the sum of the reference time data and the second working time data from the period of the data and the reset signal are obtained, and the transmission control apparatus stores the 1Ath and the first and second time data registers. Transmits the reference time data and transmits the 1Bth and 2Bth time data to the first and second time data registers according to one-half period of the period of the reset signal, and the arithmetic unit transmits the time data from the reference time data. 2Ath time data subtracting 2Ath time data, 2Bth time data subtracting 2Ath time data from the reset signal period And the transmission control device transmits the 1Ath and 2Ath time data to the first and second time data registers in response to the reset signal and responds to the 1/2 cycle of the reset signal. And transmitting the 1Bth and 2Bth time data to a second time data register. 39. The pulse generating device according to claim 38, wherein the computing device subtracts the sum of the reference time data and the first working time data from the period of the reset signal, from the reference time data. Obtaining 2Ath time data for subtracting second working time data and 2Bth time data for subtracting the reference time data in the period of the reset signal, and wherein the transmission control device responds to the reset signal to the first and the second; Transmitting the reference time data and the 2Ath time data to a time data register of the first time data register and transmitting the 1Bth and 2B time data to the first and second time data registers according to a 1/2 cycle of the reset signal. Pulse generator. 36. A pulse generating apparatus according to claim 35, wherein said counter is an up / down counter, and said reset signal of said counter is a counter up signal and a count down signal applied alternately at a predetermined period. . 43. A pulse generating apparatus according to claim 42, wherein said computing device subtracts second working time data from said first time data and said reference time data to add said first working time data to said reference time data. Obtaining a second time data subtracting a second time data, and transmitting the first and second time data to the first and second time data registers by the transmission control device; . 43. A pulse generating apparatus according to claim 42, wherein said computing device subtracts second working time data from said first time data and said reference time data to add said first working time data to said reference time data. Obtaining second time data, and transmitting the first time data and the reference time data to the first and second time data registers in synchronization with the count-up signal and synchronizing with the count-down signal. And the reference time data and the second time data are transmitted to first and second time data registers. 43. A pulse generating apparatus according to claim 42, wherein said computing device subtracts said second working time data from said first time data and said reference time data for adding said first working time data to said reference time data. And obtaining the second time data, and transmitting the reference time data and the second time data to first and second time data registers in synchronization with the count up signal, And synchronously transmitting the first time data and the reference time data to the first and second time data. A reference time data register for storing reference time data to define a time axis of a pair of pulses to be generated; First and second working time data registers for respectively storing working time data representing a time relationship of each of said pulses with respect to said reference time data; First and second pulse output registers for storing state data respectively storing one binary state of the pulse pair; A control register for storing a control signal; A counter for counting clock pulses; An arithmetic unit for retrieving the reference time data and each of the working time data so that the time data for the first and last transform of each pulse can be calculated by an equation; A transmission control device for controlling the transmission timing of the time data of each of the pulses obtained by the computing device; First and second time data registers for storing the time data of each pulse transmitted from the transmission control device, respectively; And first and second comparators for comparing the values of the counter and their values so as to send a coincidence signal when the time data of each time data register coincides with each other; Executes a defined operation in response to an operation control signal stored in the controller, and the transmission control device controls the transmission timing of each of the time data in response to a transmission control signal stored in the control register, and each of the pulse output registers. Has an output terminal reset to a binary state differently from the stored state data, and an inverted output terminal maintained in an inverted state of the output terminal, and one coincidence signal from a comparator corresponding to the binary state of the output terminal pair; Is inverted when is applied and is reset when the next coincidence signal is applied, and the counter is reset to the control register. The reference time data, each of the working time data, the state data, and the control signal are reset in response to a reset signal periodically stored in the second terminal, and are provided from the outside according to the transmission period of the count-up reset signal of the counter. Pulse generator, characterized in that. 48. A pulse generating apparatus according to claim 46, wherein an output switch for selecting one of said output terminal and said inverting output terminal of each said pulse output register is provided, and each said switch controls an output switch stored in said control register. Pulse generator characterized in that the control in response to the signal. 48. A pulse generator according to claim 46, wherein said counter is a free run counter. 49. A pulse generating apparatus according to claim 48, wherein the computing device adds the first working time data to the reference time data and the 1Ath time data to subtract the 1Ath time data from the period of the reset signal. Data, 2Ath time data for subtracting 2Ath time data from the reference time data, and 2Bth time data for subtracting 2Ath time data from the period of the reset signal, and the transmission control device responds to the reset signal. Transmitting the 1Ath and 2Ath time data to the first and second time data registers and transmitting the 1Bth and 2Bth time data to the first and second time data registers according to a half period of the reset signal. Pulse generator. 49. The pulse generating apparatus according to claim 48, wherein the arithmetic unit is 1Ath time data for adding the first working time data to the reference time data, and 1Bth for subtracting the reference time data from the period of the reset signal. Obtaining 2Bth time data which subtracts the sum of the reference time data and the second working time data from the time data and the period of the reset signal, the transmission control device sends the 1Ath to the first and second time data registers. Transmitting time data and the reference time data and transmitting the 1Bth time data and the 2Bth time data to the first and second time data registers according to a 1/2 cycle of the reset signal. Device. 49. The pulse generating apparatus according to claim 48, wherein the computing device subtracts the sum of the reference time data data and the first working time data from the period of the reset signal, and the 1Bth time data from the reference time data. 2Ath time data for subtracting second working time data and 2Bth time data for subtracting the reference time data from the period of the reset signal are obtained, and the transmission control apparatus responds to the reset signal to the first and second. Transmitting the reference time data and the 2Ath time data to a time data register of the first data and the 2Bth time data to the first and second time data registers according to a 1/2 cycle of the reset signal. Pulse generator. 48. A pulse generating apparatus according to claim 46, wherein said counter is an up / down counter and said reset signal of said counter is a counter up signal and a counter down signal applied alternately at a predetermined period. 53. A pulse generating apparatus according to claim 52, wherein said computing device subtracts said second working time data from said first time data and said reference time data for adding said first working time data to said reference time data. Obtaining second time data, and transmitting the first and second time data to the first and second time data registers. 53. A pulse generating apparatus according to claim 52, wherein said computing device subtracts said second working time data from said first time data and said reference time data for adding said first working time data to said reference time data. Obtaining the second time data, and transmitting the first time data and the reference time data to the first and second time data registers in synchronization with the counter-up signal, and transmitting the countdown signal. And transmitting the reference time data and the second time data to the first and second time data registers in synchronization with the first and second time data registers. 53. A pulse generating apparatus according to claim 52, wherein said computing device subtracts said second working time data from said first time data and said reference time data for adding said first working time data to said reference time data. And obtaining the second time data, and transmitting the reference time data and the second time data to the first and second time data in synchronization with the count up signal, And synchronously transmitting the first time data and the reference time data to the first and second time data registers. A reference time data register for storing reference time data to define a time axis of a pair of pulses to be generated; First and second working time data registers for respectively storing working time data representing a time relationship of each of said pulses with respect to said reference time data; First and second pulse output registers, respectively, for storing state data specifying one binary state of said pulse pair; A control register for storing a control signal; A counter for counting clock pulses; An arithmetic unit for retrieving the reference time data and each of the working time data so as to obtain time data for the first and last transformation of each pulse; A transmission control device for controlling the transmission timing of the time data of each of the pulses obtained by the computing device; First and second time data registers for storing the time data of each pulse transmitted from the transmission control device, respectively; First and second comparators for comparing the values of the counter and the values of each of the time data registers to transmit a match signal when the time data coincide with each other; Executes a defined operation in response to a stored operation control signal, and the transmission control device controls the transmission timing of each of the time data in response to a transmission control signal stored in the control register, and transmits the first pulse output register. Has an output terminal for resetting the inverted state of the stored state data, the second pulse output register has an output terminal for being reset to a binary state of the stored state data, and two of the output terminal pairs The output is inverted when one coincidence signal is provided from the corresponding comparator and the output stage when the next coincidence signal is provided. Is reset, the counter is reset in response to a reset signal periodically stored in the control register, and the reference time data, each of the working time data, the status data, and the control signal count up of the counter. And a pulse generator provided from the outside in response to the reset signal. 57. A pulse generating apparatus according to claim 56, wherein each of said pulse output registers has an inverting output terminal held in an inverted state of said output terminal. 57. A pulse generating apparatus according to claim 56, wherein an output switch for selecting one of said output terminal and said inverting output terminal of each said pulse output register is provided, and each said switch controls an output switch stored in said control register. A pulse generator, characterized in that it is controlled in response to a signal. 57. A pulse generator according to claim 56, wherein said counter is a free run counter. The pulse generator according to claim 56, wherein the counter is an up / down counter and the reset signal of the counter is a counter up signal and a counter down signal which are alternately applied at a predetermined period. 61. The pulse generating apparatus according to claim 60, wherein the computing device forms the reference time data to be first time data and subtracts the working time data from the reference time data to obtain second time data. And a transmission control device transmits the first and second time data to the first and second time data registers. A reference time data register for storing reference time data to define one time axis of the generated pulse pairs; A working time data register for storing working time data representing a timing relationship between one of the pulse pairs and the other; First and second pulse output registers, respectively, for storing state data specifying one binary state of said pulse pair; A control register for storing a control signal; A counter for counting clock pulses; An arithmetic unit for retrieving the reference time data and each of the working time data so as to obtain time data for the first and last transformation of each pulse; A transmission control device for controlling the transmission timing of the time data of each of the pulses obtained by the computing device; First and second time data registers for storing the time data of each pulse transmitted from the transmission control device, respectively; First and second comparators for comparing the values of the counter and the values of each of the time data registers to transmit a match signal when the time data coincide with each other; Executes a defined operation in response to a stored operation control signal, the transmission control device controls the transmission timing of each of the time data in response to a transmission control signal stored in the control register, and each of the pulse output registers A coincidence signal from a comparator having an output terminal reset to an inverted state of the stored state data and an inverted output terminal operatively associated with the output terminal, wherein the binary state of the pair of output terminals is corresponding; Is inverted when is provided and the binary state of the output terminal is reset when the next coincidence signal is provided. The counter is reset in response to a reset signal periodically stored in the control register, and the reference time data, each of the working time data, the state data, and the control signal respond to a count up reset signal of the counter. Pulse generator, characterized in that provided from the outside. 63. The pulse generating device according to claim 62, wherein each of said pulse output registers has an inverting output terminal held in an inverted state of said output terminal. 63. A pulse generating apparatus according to claim 62, wherein an output switch for selecting one of said output terminal and said inverting output terminal of each said pulse output register is provided, and each said switch controls an output switch stored in said control register. Pulse generator characterized in that the control in response to the signal. 64. A pulse generator according to claim 63, wherein said counter is a free run counter. 63. A pulse generating apparatus according to claim 62, wherein said counter is an up / down counter and said reset signal of said counter is a counter up signal and a counter down signal applied alternately at a predetermined period. A pulse generating apparatus according to claim 66, wherein said computing device forms said reference time data so as to be first time data, and subtracts said working time data from said reference time data to obtain second time data. And a transmission control device transmits the first and second time data to the first and second time data registers. A CPU for comparing the output voltage command of the inverter circuit for motor rotation and a carrier wave to calculate a PWM pulse for controlling the switching element of the inverter circuit and from the data to the switching element to generate the PWM pulse transmitted from the CPU. An electric motor control microcomputer having a pulse generator for generating and transmitting a gate pulse, comprising: a reference time data register for storing reference time data defining a time axis of a pair of pulses generated; First and second working time data registers for storing working time data respectively representing timing relationships of the respective pulses with respect to the reference time data; First and second pulse output registers for storing state data specifying binary states of one pulse of said pulse pair, respectively; A control register for storing a control signal; A counter for counting clock pulses; An arithmetic unit for retrieving the reference time data and each of the working time data so that the time data for the first and last transform of each pulse can be calculated by an equation; A transmission control device for controlling the transmission timing of the time data of each of the pulses obtained by the computing device; First and second time data registers for storing said time data of each said pulse transmitted from said transmission control device, respectively; A pulse generating device comprising first and second comparators for comparing the values of the counter and their values so as to send a coincidence signal when the time data of each time data register coincides with each other; Executes the defined operation in response to the operation control signal stored in the control register, and the transmission control device controls the transmission timing of each of the time data in response to the transmission control signal stored in the control register, A pulse output register of 1 has an output terminal reset in an inverted state of said storage state data, said second pulse output register has an output terminal reset in a binary state of said storage state data, and The binary state of the output terminal pair is reversed if one match signal is provided from the corresponding comparator and the next match signal Is reset if provided, the counter is reset in response to a reset signal periodically stored in the control register, and the reference time data, each of the working time data, the status data, and the control signal are stored in the counter. A reference for defining the timing axis for a pair of PWM pulses provided for the pair of upper and lower arms of the inverter to be provided from the outside according to the transmission period of the count-up reset signal and stored in a corresponding register of the pulse generator. An electric motor including time data, working time data representing a functional relationship of the PWM pulse pairs to the reference time data, state data for designating one binary state of the PWM pulses, and a CPU for generating the control signal; Control microcomputer. A CPU for comparing the output voltage command of the inverter circuit for motor rotation and a carrier wave to calculate a PWM pulse for controlling the switching element of the inverter circuit and from the data to the switching element to generate the PWM pulse transmitted from the CPU. An electric motor control microcomputer having a pulse generator for generating and transmitting a gate pulse, comprising: a reference time data register for storing reference time data defining a time axis of a pair of pulses generated; A working time data register for storing working time data indicating a timing relationship between the one pulse and the other pulse; First and second pulse output registers for storing state data specifying binary states of one pulse of said pulse pair, respectively; A control register for storing a control signal; A counter for counting clock pulses; An arithmetic unit for retrieving the reference time data and each of the working time data so as to obtain time data for the first and last transformation of each pulse; A transmission control device for controlling the transmission timing of the time data of each of the pulses obtained by the computing device; First and second time data registers for storing said time data of each said pulse transmitted from said transmission control device, respectively; A pulse generating device comprising first and second comparators for comparing the values of said counter and their values so as to transmit a coincidence signal when the time data of each said time data register coincides with each other, and said computing device Executes a defined operation in response to an operation control signal stored in the control register, and the transmission control device controls the transmission timing of each of the time data in response to a transmission control signal stored in the control register, The pulse output register has an output terminal reset in an inverted state of the stored state data and an inverted output terminal that is complementary to the output terminal, wherein the binary state of the pair of output terminals is one coincidence signal; Is inverted if provided from the corresponding comparator and reset if the next match signal is provided, Is reset in response to a reset signal periodically stored in the control register, and the reference time data, each of the working time data, the state data, and the control signal are transmitted during the count up reset signal of the counter. Reference time data for defining the timing axis of the pair of PWM pulses for the pair of upper and lower arms of the inverter so as to be externally provided and stored in a corresponding register of the pulse generator. Working time data indicating a functional relationship of the PWM pulse pairs with respect to each other; and a state data for designating one binary state of the PWM pulses and a CPU for generating the control signal. A CPU for comparing a carrier wave with an output voltage command of the inverter circuit for motor rotation to calculate a PWM pulse for controlling the switching element of the inverter circuit, and the switching element from the data for generating the PWM pulse transmitted from the CPU An electric motor control microcomputer having a pulse generator for generating and transmitting gate pulses, comprising: a reference time data register for storing reference time data to define a time axis of a pair of pulses generated; First and second working time data registers for storing working time data respectively representing timing relationships of the respective pulses with respect to the reference time data; First and second pulse output registers for storing state data specifying binary states of one pulse of said pulse pair, respectively; A control register for storing a control signal; A counter for counting clock pulses; An arithmetic unit for retrieving the reference time data and each of the working time data to obtain time data for the first and last transformation of each pulse; A transmission control device for controlling the transmission timing of the time data with each of the pulses obtained by the computing device; First and second time data registers for storing said time data of each said pulse transmitted from said transmission control device, respectively; A pulse generating device comprising first and second comparators for comparing the values of the counter and the values so as to send a coincidence signal when the time data of each time data register coincides with each other; Executes a defined operation in response to the operation control signal stored in the control register, and the transmission control device controls the transmission timing of each of the time data in response to the transmission control signal stored in the control register, A pulse output register of 1 has an output terminal reset in an inverted state of said storage state data, said second pulse output register has an output terminal for resetting said storage state in a binary state of data, The binary state of the output terminal pair is inverted when one coincidence signal is provided from the corresponding comparator and the next coincidence signal is Is reset if provided, the counter is reset in response to a reset signal periodically stored in the control register, and the reference time data, each of the working time data, the status data, and the control signal are stored in the counter. A reference time for defining the timing axis of the pair of PWM pulses for the pair of upper and lower arms of the inverter to be provided externally in response to the count-up reset signal and to be stored in a corresponding register of the pulse generator. Motor control micros including data, working time data indicating a functional relationship of the PWM pulse pairs to the reference time data, state data for designating one binary state of the PWM pulses, and a CPU generating the control signal computer. A CPU for comparing a carrier wave with an output voltage command of the inverter circuit for motor rotation to calculate a PWM pulse for controlling the switching element of the inverter circuit, and the switching element from the data for generating the PWM pulse transmitted from the CPU An electric motor control microcomputer having a pulse generator for generating and transmitting gate pulses, comprising: a reference time data register for storing reference time data to define a timing axis of a pair of pulses generated; First and second working time data registers for storing working time data respectively representing timing relationships of the respective pulses with respect to the reference time data; First and second pulse output registers for respectively storing state data specifying binary states of one pulse of said pulse pair; A control register for storing a control signal; A counter for counting clock pulses; An arithmetic unit for retrieving the reference time data and each of the working time data so that the time data for the first and last transform of each pulse can be calculated by an equation; A transmission control device for controlling the transmission timing of the time data of each of the pulses obtained by the computing device; First and second time data registers for storing said time data of each said pulse transmitted from said transmission control device, respectively; A pulse generating device including first and second comparators for comparing the values of the counter and the values so as to transmit a coincidence signal when the time data of each time data register coincides with each other; Executes a defined operation in response to an operation control signal stored in the control register, and the transmission control device controls the transmission timing of each of the time data in response to a transmission control signal stored in the control register, A pulse output register has an output terminal reset in an inverted state of the stored state data and an inverted output terminal that is complementarily operated in relation to the output terminal, wherein the binary state of the output terminal pair has a single coincidence signal. The counter is inverted if provided from the corresponding comparator and reset when the next match signal is provided, and the counter Reset in response to a reset signal periodically stored in the control register, wherein the reference time data, each of the working time data, the state data, and the control signal are external in response to the count-up reset signal of the counter. Reference time data for defining said timing axis of a pair of PWM pulses for a pair of upper and lower arms of said inverter to be stored in corresponding registers of said pulse generator, said PWM for said reference time data And a CPU for generating the control signal and working time data indicating a function pair of a pulse pair, state data for designating one binary state of the PWM pulses. CPU means for conveying an output voltage command and a carrier wave of the inverter circuit exclusively for electric motor operation to calculate a PWM pulse for controlling a switching element of the inverter circuit, and the switching from data to generate the PWM pulse transmitted from the CPU. A motor control microcomputer having a pulse generator for generating and transmitting gate pulses to an element, said motor axis being defined, wherein said timing axis of said PWM pulses is defined for a pair of upper and lower arms to be stored in corresponding registers of said pulse generator. Reference time data for performing, a working time data eye team for defining dead time between the positive pulse and the sub-pulse, and state data for designating one binary state of the positive PWM pulse and the sub-PWM pulse. And a phase relative to the reference pulse according to the load current detection direction of the inverter circuit. A first method in which the first conversion of the positive pulse is delayed and the last conversion is moved in the forward direction and a second method in which only the first conversion of the positive PWM pulse is moved in the forward direction relative to the reference pulse and the reference signal Generate a control signal generated by selecting a method capable of preventing an error of an output voltage from a third method in which only the last conversion of the positive PWM pulse is delayed, and the control signal including the operation control signal A reference time data register for storing reference time data that defines a CPU for generating the timing axis of the generated pulse pair; First and second working time data registers for storing working time data respectively representing timing relationships of the respective pulses with respect to the reference time data; First and second pulse output registers for storing state data specifying binary states of one pulse of said pulse pair, respectively; A control register for storing a control signal; A counter for counting clock pulses; An arithmetic unit for retrieving the reference time data and each of the working time data so as to obtain time data for the first and last transformation of each pulse; A transmission control device for controlling the transmission timing of the time data of each of the pulses obtained by the computing device; First and second time data registers for storing said time data of each said pulse transmitted from said transmission control device, respectively; And a pulse generating device including first and second comparators for comparing the values of the counter and the time data value of each of the time data registers to compare the values so as to transmit a matching signal. Executes the operation defined in response to the operation control signal stored in the register, and the transmission control device controls the transmission timing of each of the time data in response to the transmission control signal stored in the control register, A pulse output register having an output terminal reset in an inverted state of the stored state data, the second pulse output register having an output terminal reset in a binary state of the stored state data, the output The binary state of a terminal pair is reversed when one match signal is provided from the corresponding comparator and the next match Is reset, the counter is reset in response to a reset signal periodically stored in the control register, and the reference time data, each of the working time data, the status data, and the control signal of the counter are reset. And a motor control microcomputer provided in response to a transmission period of the count-up reset signal.