KR100195244B1 - Manufacturing method of semiconductor memory device - Google Patents
Manufacturing method of semiconductor memory device Download PDFInfo
- Publication number
- KR100195244B1 KR100195244B1 KR1019960039144A KR19960039144A KR100195244B1 KR 100195244 B1 KR100195244 B1 KR 100195244B1 KR 1019960039144 A KR1019960039144 A KR 1019960039144A KR 19960039144 A KR19960039144 A KR 19960039144A KR 100195244 B1 KR100195244 B1 KR 100195244B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- silicon nitride
- substrate
- nitride film
- semiconductor memory
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 52
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 238000001039 wet etching Methods 0.000 claims abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 4
- 238000005452 bending Methods 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- 230000010354 integration Effects 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체 메모리 디바이스의 제조방법에 관한 것으로서, 더 상세하게는 반도체 메모리 디바이스의 STI(shallow trench isolation)를 위한 공정시 웨이퍼의 휨(warpage)을 방지할 수 있도록 한 반도체 메모리 디바이스의 제조방법에 관한 것이다. 이를 위한 본 발명은, STI 공정을 포함하는 반도체 메모리 디바이스의 제조방법에 있어서, 소정의 기판상에 패드 산화막을 형성하고, 소정의 CMP 식각의 저지층으로 작용하는 실리콘 질화막을 저압 화학기상증착법으로 증착하는 제1단계와, 상기 실리콘 질화막의 상면부에만 플라즈마 화학기상증착법으로 제1산화막을 증착하는 제2단계와, 상기 제1산화막을 이용하여 상기 기판의 배면부에 증착되어 있는 실리콘 질화막을 습식식각으로 제거하는 제3단계와, 상기 제3단계 후 상기 제1산화막을 습식식각으로 제거하는 제4단계와, 상기 제4단계 후에 상기 기판의 상면부에 형성된 실리콘 질화막상에 트렌치 에칭 마스크용으로 작용하는 제2산화막을 형성하고 이 제2산화막으로 소정의 사진공정을 하여 패터닝하는 단계를 포함하는 것을 특징으로 한다. 따라서, 본 발명은 기판의 상면부에만 실리콘 질화막을 형성시킴으로써 STI를 위한 공정시 기판이 휘는 것을 방지할 수 있는 이점을 제공한다.The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device capable of preventing warpage of a wafer during a process for shallow trench isolation (STI) of the semiconductor memory device. It is about. According to the present invention, in the method of manufacturing a semiconductor memory device including an STI process, a silicon oxide film, which forms a pad oxide film on a predetermined substrate and serves as a stop layer for a predetermined CMP etching, is deposited by low pressure chemical vapor deposition. Performing a first step of depositing a first oxide film on the upper surface of the silicon nitride film by plasma chemical vapor deposition, and wet etching the silicon nitride film deposited on the back surface of the substrate using the first oxide film. A third step of removing; and a fourth step of wet removing the first oxide film after the third step; and after the fourth step, a trench etching mask is formed on the silicon nitride film formed on the upper surface of the substrate. And forming a second oxide film and patterning the second oxide film by a predetermined photo process. Therefore, the present invention provides an advantage of preventing the substrate from bending during the process for STI by forming the silicon nitride film only on the upper surface portion of the substrate.
Description
본 발명은 반도체 메모리 디바이스의 제조방법에 관한 것으로서, 더 상세하게는 반도체 메모리 디바이스의 STI(shallow trench isolation)를 위한 공정시 웨이퍼의 휨(warpage)을 방지할 수 있도록 한 반도체 메모리 디바이스의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device capable of preventing warpage of a wafer during a process for shallow trench isolation (STI) of the semiconductor memory device. It is about.
최근에 반도체 기술의 발달에 따라 반도체 디바이스의 집적도가 점점 커지고 있다. 이와 같은 반도체 디바이스의 고집적도는 반도체 메모리 디바이스에 적용되어 대용량의 반도체 메모리 디바이스의 개발이 가속화되고 있는데, 이를 사진공정등의 제조공정 측면에서 볼 때 각 공정시 평탄화는 필수적으로 요구되고 있다. 그리고, 메모리 집적화에 따른 소자 분리(isolation)구조는 LOCOS(local oxidation of silicon)계열에서 보다 우수한 분리 특성을 갖는 STI(shallow trench isolation)로 변화하고 있는데, 상기 STI는 공정상의 많은 문제를 갖고 있어 그 적용에 많은 어려움이 있는 실정이다. 즉, 상기 STI를 위한 공정은 도 1a 내지 도 1f 에 도시되어 있는 바와 같이, 실리콘 기판(1)에 패드 산화막(미도시)를 형성하는 단계(도 1a); 상기 패드 산화막이 형성된 기판(1)상에 CMP(chemical mechanical polishing)의 저지층으로 작용하는 실리콘 질화막(2)을 증착하는 단계(도 1b); 상기 실리콘 질화막(2)에서 발생되는 파티클(particle)을 방지하며 트렌치 마스크 역할을 수행하는 제1산화막(3)을 증착하는 단계(도 1c); 제1산화막(3)을 이용하여 상기 기판(1)의 상면에 트렌치부(7)를 형성하는 단계(도 1d); 상기 트렌치부(7)의 제1산화막을 제거하고 소정의 CMP 공정을 수행하는 단계(도 1e); 상기 단계 후 디바이스의 고집적화등을 위해 고온 열처리 공정을 수행하는 단계(도 1f);를 포함한다.Recently, with the development of semiconductor technology, the degree of integration of semiconductor devices is increasing. Such high integration of semiconductor devices has been applied to semiconductor memory devices to accelerate the development of large-capacity semiconductor memory devices. In view of manufacturing processes such as photographic processes, planarization is required for each process. In addition, the isolation structure due to memory integration is changing to shallow trench isolation (STI) having better isolation characteristics in the local oxidation of silicon (LOCOS) series, and the STI has many problems in the process. There are many difficulties in application. That is, the process for the STI may include forming a pad oxide film (not shown) on the silicon substrate 1 as shown in FIGS. 1A to 1F (FIG. 1A); Depositing a silicon nitride film (2) serving as a stop layer of chemical mechanical polishing (CMP) on the substrate (1) on which the pad oxide film is formed (FIG. 1B); Depositing a first oxide film 3 that prevents particles generated in the silicon nitride film 2 and serves as a trench mask (FIG. 1C); Forming a trench portion 7 on the upper surface of the substrate 1 using the first oxide film 3 (FIG. 1D); Removing the first oxide film of the trench portion 7 and performing a predetermined CMP process (FIG. 1E); And performing a high temperature heat treatment process for high integration of the device after the above step (FIG. 1F).
그런데, 상기의 제조공정에 있어서, 상기의 CMP 공정 후에 수행되는 고온 열처리 공정시에 상기 기판(1)의 배면에 증착되어 있는 실리콘 질화막(2)의 압축 스트레스로 인해 도 1f에 도시되어 있는 바와 같이 웨이퍼, 즉 기판(1)이 휘어지는 문제점이 발생하였다. 상기와 같이 기판(1)의 휘어짐이 발생하면 상기 공정 단계이후의 습식식각 공정등을 통해 상기 실리콘 질화막(2)을 제거하여도 상기 기판(1)의 휘어짐은 복구되지 않아 사진공정과 같은 후속 공정에서 부정합(misalign)이 발생하는 문제점이 있었다.However, in the above manufacturing process, due to the compressive stress of the silicon nitride film 2 deposited on the back surface of the substrate 1 during the high temperature heat treatment process performed after the CMP process, as shown in FIG. 1F. The wafer, that is, the problem that the substrate 1 is bent occurs. If the warpage of the substrate 1 occurs as described above, even if the silicon nitride film 2 is removed through a wet etching process or the like after the process step, the warpage of the substrate 1 is not restored, and thus a subsequent process such as a photographing process is performed. There was a problem that misalignment occurs in.
본 발명이 이루고자 하는 기술적 과제는, 기판의 상면부에만 실리콘 질화막을 형성시킴으로써 STI를 위한 공정시 기판이 휘는 것을 방지할 수 있도록 한 반도체 메모리 디바이스의 제조방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a semiconductor memory device in which a silicon nitride film is formed only on an upper surface of a substrate to prevent the substrate from bending during a process for STI.
도 1a 내지 도 1f 는 종래 반도체 메모리 디바이스의 제조방법에 따른 공정 순서를 도시한 공정도이다.1A to 1F are process diagrams showing a process sequence according to a method of manufacturing a conventional semiconductor memory device.
도 2a 내지 도 2f 는 본 발명에 따른 반도체 메모리 디바이스의 제조방법에 의한 공정 순서를 도시한 공정도이다.2A to 2F are process diagrams showing a process sequence by the method of manufacturing a semiconductor memory device according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
10...기판,10 ...
20...실리콘 질화막,20 ... silicon nitride film,
30...제1산화막,30, the first oxide film,
40...제2산화막.40. Second oxide film.
상기 과제를 이루기 위하여 본 발명에 따른 반도체 메모리 디바이스의 제조방법은, STI 공정을 포함하는 반도체 메모리 디바이스의 제조방법에 있어서, 소정의 기판상에 패드 산화막을 형성하고, 소정의 CMP 식각의 저지층으로 작용하는 실리콘 질화막을 저압 화학기상증착법으로 증착하는 제1단계와, 상기 실리콘 질화막의 상면부에만 상기 실리콘 질화막과 선택비를 갖는 제1막을 증착하는 제2단계와, 상기 제1막을 이용하여 상기 기판의 배면부에 증착되어 있는 실리콘 질화막을 습식식각으로 제거하는 제3단계와, 상기 제3단계 후 상기 제1막을 습식식각으로 제거하는 제4단계와, 상기 제4단계 후에 상기 기판의 상면부에 형성된 실리콘 질화막상에 트렌치 에칭 마스크용으로 작용하는 제2막을 형성하고 이 제2막으로 소정의 사진공정을 하여 패터닝하는 단계를 포함하는 점에 그 특징이 있다.In order to achieve the above object, a method of manufacturing a semiconductor memory device according to the present invention, in the method of manufacturing a semiconductor memory device comprising an STI process, forming a pad oxide film on a predetermined substrate, and as a stop layer for a predetermined CMP etching A first step of depositing a functioning silicon nitride film by a low pressure chemical vapor deposition method, a second step of depositing a first film having a selectivity with the silicon nitride film only on an upper surface of the silicon nitride film, and the substrate using the first film A third step of wet etching the silicon nitride film deposited on the rear surface of the second step; a fourth step of wet removing the first film after the third step; and a fourth step of forming the upper surface of the substrate after the fourth step. A second film is formed on the silicon nitride film to serve as a trench etching mask, and the second film is patterned by a predetermined photographic process. Its feature is that it includes steps.
본 발명의 바람직한 실시예에 있어서, 상기 제2단계에서 상기 제1막 대신에 상기 제1막과 유사한 특성을 갖는 소정의 막질, 예를 들면 상기 실리콘 질화막보다 스트레스가 적은 제2의 실리콘 질화막을 증착시킬 수 있다.In a preferred embodiment of the present invention, in the second step, instead of the first film, a predetermined film quality having properties similar to the first film, for example, a second silicon nitride film having less stress than the silicon nitride film is deposited. You can.
또한, 본 발명의 반도체 메모리 디바이스의 제조방법에 있어서, 소정의 기판상에 패드 산화막을 형성하고, 소정의 CMP 식각의 저지층으로 작용하는 실리콘 질화막을 상기 기판의 상면부에만 플라즈마 화학기상증착법으로 증착하는 단계와, 상기 기판의 상면부에 형성된 실리콘 질화막상에 트렌치 에칭 마스크용으로 작용하는 소정의 막을 형성하고 이 막으로 소정의 사진공정을 하여 패터닝하는 단계를 포함하는 점에 그 특징이 있다.Further, in the method of manufacturing a semiconductor memory device of the present invention, a silicon oxide film, which forms a pad oxide film on a predetermined substrate and serves as a stop layer for a predetermined CMP etching, is deposited only on the upper surface of the substrate by plasma chemical vapor deposition. And forming a predetermined film serving as a trench etching mask on the silicon nitride film formed on the upper surface of the substrate and patterning the film by performing a predetermined photo process.
이하, 첨부된 도면을 참조하면서 본 발명에 따른 반도체 메모리 디바이스의 제조방법의 바람직한 실시예를 상세하게 설명한다.Hereinafter, a preferred embodiment of a method of manufacturing a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.
본 발명에 따른 반도체 메모리 디바이스의 제조방법은, 기판의 상면부에만 CMP 공정시 식각 저지층으로 작용하는 실리콘 질화막을 형성시킴으로써 고집적화등을 위한 후속 고온 열처리 공정시 기판이 휘는 것을 방지한 것으로서, 특징적으로 STI 공정을 수반하는 제조공정에서 기판의 배면부에 형성되는 실리콘 질화막을 제거하는 공정 또는 상기 기판의 전면부에만 실리콘 질화막을 형성하는 공정을 포함한다.The method of manufacturing a semiconductor memory device according to the present invention is to prevent the substrate from bending during a subsequent high temperature heat treatment process for high integration by forming a silicon nitride film acting as an etch stop layer during the CMP process only on the upper surface of the substrate. A process of removing the silicon nitride film formed on the back portion of the substrate in the manufacturing process accompanying the STI process or the step of forming a silicon nitride film only on the front portion of the substrate.
먼저, 본 발명에 따른 반도체 메모리 디바이스의 제조방법에 있어서, 소정의 패드 산화막(미도시)이 형성된 반도체 실리콘 기판(10)상에 CMP 저지층으로 작용하는 실리콘 질화막(Si3N4)(20)을 1000Å - 2000Å 정도의 두께로 증착 형성한다(도 2a, 도 2b ). 여기서, 상기 실리콘 질화막(20)은 저압 화학기상증착에 의해 형성되는 것이 바람직하다. 상기 실리콘 질화막(20)의 상면부에는 도 2c에 도시되어 있는 바와 같이 플라즈마 화학기상증착에 의해 소정의 제1막(30)이 증착되는데, 이는 실리콘 질화막(20)에서 발생되는 파티클(particle)을 방지하는 역할을 한다. 상기와 같이 제1막(30)을 실리콘 질화막(20)의 상면부에만 증착시키는 이유는 기판(10)의 배면부에 형성된 실리콘 질화막(20)의 제거를 용이하게 하기 위함이다. 즉, 제1막(30)을 실리콘 질화막(20)의 상면부에만 증착시킴으로써, 고온 열처리 공정시에 기판(10)을 휘게 하는 기판(10)의 배면부에 형성된 실리콘 질화막(20)의 제거를 용이하게 한다. 여기서, 상기 플라즈마 형태의 제1막(30)은 기판(10)의 배면부에 형성된 실리콘 질화막(20)의 식각시 충분한 양의 오버 에치(over etch)를 할 경우 식각되는 양의 2배정도로 하는 것이 바람직하다. 상기 제1막은 상기 실리콘질화막과 선택비를 가지는 막질을 가지며, 플라스마 및 산화막에 국한되지는 않는다.First, in the method of manufacturing a semiconductor memory device according to the present invention, a silicon nitride film (Si3N4) 20 serving as a CMP blocking layer is formed on a semiconductor silicon substrate 10 on which a predetermined pad oxide film (not shown) is formed. It deposits and forms in thickness of about 2000 microseconds (FIG. 2A, FIG. 2B). Here, the silicon nitride film 20 is preferably formed by low pressure chemical vapor deposition. As illustrated in FIG. 2C, a predetermined first film 30 is deposited on the upper surface of the silicon nitride film 20 by plasma chemical vapor deposition, which generates particles generated from the silicon nitride film 20. It serves to prevent. The reason why the first film 30 is deposited only on the upper surface of the silicon nitride film 20 as described above is to facilitate the removal of the silicon nitride film 20 formed on the rear surface of the substrate 10. That is, by depositing the first film 30 only on the upper surface portion of the silicon nitride film 20, it is easy to remove the silicon nitride film 20 formed on the back portion of the substrate 10 that warps the substrate 10 during the high temperature heat treatment process. Let's do it. Here, the plasma type first film 30 is about twice the amount that is etched when a sufficient amount of over etch is performed during the etching of the silicon nitride film 20 formed on the rear surface of the substrate 10. desirable. The first film has a film quality having a selectivity with respect to the silicon nitride film, and is not limited to plasma and oxide films.
그 다음, 도 2d에 도시되어 있는 바와 같이, 상기 제1막(30)과 선택비를 갖는 실리콘 질화막(20)을 습식식각하여 기판(10)의 배면부에 형성된 실리콘 질화막(20)을 제거하고, 도 2e에 도시되어 있는 바와 같이 제1막(30)을 실리콘 질화막(20)과 선택비를 갖는 습식식각으로 제거한다.Next, as illustrated in FIG. 2D, the silicon nitride film 20 having the selectivity with respect to the first film 30 is wet-etched to remove the silicon nitride film 20 formed on the rear surface of the substrate 10. As shown in FIG. 2E, the first film 30 is removed by wet etching having a selectivity with the silicon nitride film 20.
상기와 같이 제1막(30)이 제거되었으면, 도 2f에 도시되어 있는 바와 같이 기판(10)의 상면부에 형성된 실리콘 질화막(20)상에 트렌치 에칭 마스크용으로 작용하는 제2막(40)을 형성하고 이 제2막(40)으로 소정의 사진공정을 하여 패터닝함으로써, STI형성시 소성에 의한 산화막 밀집화(oxide densification)에 의해 그 후 사진공정에서 발생될 수 있는 기판의 휨 발생을 방지할 수 있게 된다. 바람직하기로는 상기 제2막은 산화막이다.When the first film 30 is removed as described above, the second film 40 serving as a trench etching mask on the silicon nitride film 20 formed on the upper surface of the substrate 10 as shown in FIG. 2F. And patterning the second film 40 by a predetermined photo process to prevent warpage of the substrate, which may occur in the subsequent photo process, by oxide densification by firing during STI formation. You can do it. Preferably, the second film is an oxide film.
본 발명의 다른 실시예로서 상기 제1막(30)은 이와 유사한 특성을 갖는 소정의 막질, 예를 들면 상기 실리콘 질화막(20)보다 스트레스가 적은 제2의 실리콘 질화막으로 할 수 있다. 이와 같이 상기의 제1막(30)을 상기와 같은 제2의 실리콘 질화막으로 하게 되면 재료를 일원화할 수 있는 장점을 제공하게 된다.In another embodiment of the present invention, the first film 30 may be a predetermined film quality having similar characteristics, for example, a second silicon nitride film having less stress than the silicon nitride film 20. In this way, the first film 30 as the second silicon nitride film as described above provides an advantage of unifying the material.
또한, 본 발명의 또 다른 실시예로서, 기판(10)상에 미도시된 패드 산화막을 형성하고, 소정의 CMP 식각의 저지층으로 작용하는 실리콘 질화막(20;도 2f 참조)을 상기 기판(10)의 상면부에만 플라즈마 화학기상증착법으로 증착하고, 상기 기판(10)의 상면부에 형성된 실리콘 질화막(20)상에 트렌치 에칭 마스크용으로 작용하는 산화막(40; 도 2f 참조)을 형성하고 이 산화막으로 소정의 사진공정을 하여 패터닝할 수도 있다. 이와 같이 하면, 첫번째 실시예에 있어서 플라즈마 형태의 제1산화막 증착, 실리콘 질화막 배면부의 습식식각, 제1산화막 제거의 공정이 배제되는 장점을 갖게 된다.In addition, as another embodiment of the present invention, a silicon nitride film 20 (see FIG. 2F), which forms a pad oxide film (not shown) on the substrate 10 and serves as a stop layer for a predetermined CMP etching, may be formed on the substrate 10. Is deposited on the upper surface portion of the C-type) by plasma chemical vapor deposition, and an oxide film 40 (refer to FIG. 2F) serving as a trench etching mask is formed on the silicon nitride film 20 formed on the upper surface of the substrate 10. May be patterned by a predetermined photographic process. In this way, in the first embodiment, the plasma oxide first oxide film deposition, the wet etching of the silicon nitride film back portion, and the first oxide film removal process are eliminated.
상술한 바와 같이 본 발명에 따른 반도체 메모리 디바이스의 제조방법은, 기판의 상면부에만 실리콘 질화막을 형성시킴으로써 STI를 위한 공정시 기판이 휘는 것을 방지할 수 있는 이점을 제공한다.As described above, the method of manufacturing a semiconductor memory device according to the present invention provides an advantage of preventing the substrate from bending during the process for STI by forming the silicon nitride film only on the upper surface portion of the substrate.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960039144A KR100195244B1 (en) | 1996-09-10 | 1996-09-10 | Manufacturing method of semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960039144A KR100195244B1 (en) | 1996-09-10 | 1996-09-10 | Manufacturing method of semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980020625A KR19980020625A (en) | 1998-06-25 |
| KR100195244B1 true KR100195244B1 (en) | 1999-06-15 |
Family
ID=19473256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960039144A KR100195244B1 (en) | 1996-09-10 | 1996-09-10 | Manufacturing method of semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100195244B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101606372B1 (en) | 2013-07-25 | 2016-03-25 | 미쓰비시덴키 가부시키가이샤 | Method of manufacturing semiconductor device |
-
1996
- 1996-09-10 KR KR1019960039144A patent/KR100195244B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101606372B1 (en) | 2013-07-25 | 2016-03-25 | 미쓰비시덴키 가부시키가이샤 | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980020625A (en) | 1998-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4690728A (en) | Pattern delineation of vertical load resistor | |
| US5911110A (en) | Method of forming shallow trench isolation with dummy pattern in reverse tone mask | |
| US5856227A (en) | Method of fabricating a narrow polycide gate structure on an ultra-thin gate insulator layer | |
| US6066570A (en) | Method and apparatus for preventing formation of black silicon on edges of wafers | |
| US5985725A (en) | Method for manufacturing dual gate oxide layer | |
| US6015755A (en) | Method of fabricating a trench isolation structure using a reverse mask | |
| KR100195244B1 (en) | Manufacturing method of semiconductor memory device | |
| US6238997B1 (en) | Method of fabricating shallow trench isolation | |
| US6103581A (en) | Method for producing shallow trench isolation structure | |
| US6184106B1 (en) | Method for manufacturing a semiconductor device | |
| KR20010046153A (en) | Method of manufacturing trench type isolation layer in semiconductor device | |
| KR100478496B1 (en) | Formation method of trench oxide in semiconductor device | |
| KR100808377B1 (en) | Fabrication method of semiconductor device | |
| US6303461B1 (en) | Method for fabricating a shallow trench isolation structure | |
| KR100226728B1 (en) | Method of forming a device isolation film of semiconductor device | |
| US7256100B2 (en) | Manufacturing method of semiconductor device having trench type element isolation | |
| KR20020002164A (en) | Method of forming isolation layer of semiconductor device | |
| US6218307B1 (en) | Method of fabricating shallow trench isolation structure | |
| KR100829375B1 (en) | Formation method of trench in semiconductor device | |
| JPH11163118A (en) | Manufacture of semiconductor device | |
| KR100190065B1 (en) | Trench isolation method | |
| KR20000051689A (en) | Shallow trench manufacturing method for isolating semiconductor devices | |
| KR20030002702A (en) | Method of forming an isolation layer in a semiconductor device | |
| KR100244712B1 (en) | Method of fabricating semiconductor device | |
| TW452924B (en) | Method for forming trench isolation area with spin-on material |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100114 Year of fee payment: 12 |
|
| LAPS | Lapse due to unpaid annual fee |