KR100190068B1 - Circuit of non-volatile memory cell using ferroelectric gate capacitor - Google Patents

Abstract

A circuit of an inert, non-destructive memory cell having a novel ferroelectric gate capacitor is disclosed. One field field effect transistor having a ferroelectric gate capacitor on the gate, one access transistor for driving the field field effect transistor, a first word line and a second word line orthogonal to each other, and the first and second words One drive line and one sensing line are orthogonal to each other and perpendicular to the line. Since one memory cell consists of two transistors, the circuit can be simplified and the chip area can be reduced.

Description

Circuit of Inactive Memory Cell Using Ferroelectric Gate Capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to inert memory devices, and more particularly to circuits of inert memory cells using ferroelectric gate capacitors.

Dynamic random access memory (DRAM) has the advantages of high integration and fast operation speed, while information charge accumulated in the cell's storage capacity decreases over time due to leakage current. The disadvantage is that operation is required. On the other hand, non-volatile memory (NVM), such as static RAM (SRAM), electrically erasable programmable read only memory (EEPROM), and flash memory, has advantages in terms of data storage, but high operating voltages and high integration are difficult. Or slow operation speed. Accordingly, there is an active attempt to develop a memory device that can utilize both of the above advantages by using the physical properties of the ferroelectric material.

The ferroelectric material has spontaneous polarization inside the material by the application of an external electric field, and a part of the spontaneous polarization remains after the external electric field is removed, and the direction of the external electric field is changed to change the direction of the spontaneous polarization. It is a substance that can change direction. Since the bistable nature of ferroelectrics coincides with the basic concept of binary memory, which is now the basis of widely used digital memory devices, ferroelectrics such as PZT attract attention as a memory material from early on. come. The first memory devices using ferroelectrics are made of bulk materials, and their size and operating voltage are not suitable for fabricating highly integrated memory devices. However, with the recent advances in thin film manufacturing techniques such as sol-gel, sputtering, and metal organic chemical vapor deposition (MOCVD), ferroelectric thin film manufacturing techniques such as PZT With such a great advance, Ramtron, a pioneer in the field of ferroelectric thin films, is already producing and selling ferroelectric memory devices using PZT.

There are two main methods for manufacturing a memory device using a ferroelectric thin film. One method is to use a transistor to fabricate a ferroelectric capacitor and to read and write signals in two directions stored in the capacitor, so-called one transistor / one capacitor (1T / 1C) or two transistors / two capacitors (2T / 2C). ) Is called. Such a memory device is commonly referred to as a ferroelectric RAM (FRAM), and has a basic concept in accordance with the operation principle of DRAM. Unlike DRAM, it does not require refreshing and does not erase stored information even when electricity is turned off. It is an inactive memory device. However, since the memory device uses the inversion and non-inversion of the polarization stored in the capacitor, since the information is erased when the stored information is read once, the information destruction type that requires writing the same information as when reading again is required. (destructive read out; DRO) memory device.

On the other hand, there is a method of reading stored information without destroying it. It is a so-called nondestructive read out (NDRO) ferroelectric memory device which is considered to be the ultimate memory when it is practically used by Japanese and US advanced companies recently. It is an element to receive. Such a memory device basically forms a ferroelectric capacitor on the gate of a transistor, and the presence of a channel formed on the surface of the silicon substrate under the gate oxide film is determined by the polarization direction of the ferroelectric capacitor. For example, the principle of operation is to recognize that the channel is recorded as 1 when conducting and 0 when it is not conducting. Such a memory device is advantageous in terms of integration since a memory cell is composed of only a single transistor without fabricating a capacitor as compared to a conventional DRAM or FRAM. However, an access or select transistor for selecting a specific cell for a random access operation like a DRAM must be added to a transistor having a ferroelectric gate capacitor. Such an NDRO type ferroelectric memory is collectively referred to as a ferroelectric floating gate RAM (hereinafter referred to as FFRAM).

Compared to NVM such as flash memory using conventional tunneling electrons, the FFRAM has the following advantages in principle. First, the flash memory can only obtain the number of writes of about 10 ⁵ to 10 ^{6 due} to the deterioration of the tunneling oxide film, whereas the FFRAM uses the polarization inversion of the ferroelectric, and thus the number of writes is much larger. In case of using precious metal electrode such as platinum (Pt), although there is a problem of fatigue, it is possible to record about 10 ⁹ times. When using oxide conductor electrode, 10 ¹⁴ ~ 10 ¹⁵ times It is reported to be possible. In addition, the operating voltage of the device can be reduced to about 5V or 3V by controlling the thickness of the ferroelectric thin film to reduce the coercive voltagae, thereby lowering the voltage. In addition, since polarization inversion occurs at a much higher speed (about 10 nsec or less) by electron tunneling through the oxide film, it is possible to realize an inert, non-destructive memory device having a high speed operation as compared with a flash memory.

In order to realize such FFRAM, it is necessary to first design the operation principle of FFRAM and to design a circuit. The most active company about this fabrication is Japan's Rohm, and recently, NEC, Hitachi, Matsushita, etc. It is showing positive movement. Another big obstacle to the realization of FFRAMs is that PZT, the most promising ferroelectric material when forming a ferroelectric on the gate of a transistor, produces very severe chemical reactions or interdiffusion with silicon and silicon dioxide (SiO ₂ ). The process is extremely difficult. Recently, Rohm has reported that iridium dioxide (IrO ₂ ) has been developed as an electrode material that can solve this problem and formed on SiO ₂ to show excellent characteristics as an electrode material of PZT.

FIG. 1 is a circuit diagram designed to enable Rohm to make FFRAM practical while using IrO ₂ as an electrode material, and is disclosed in US Patent No. 5,345,414.

Referring to FIG. 1, one ferroelectric transistor (FTr) is used as one memory basic unit, and one write and erase transistor and one read transistor are added to drive one FTr. That is, one memory cell includes one ferroelectric transistor (FTr) and two transistors (write / erase and read transistors), two side-by-side word lines, and one orthogonal to and parallel to the word lines. It consists of a drive line and one sensing line. As a result, one memory cell has a circuit composed of three transistors.

An object of the present invention is to use a single access transistor to drive a single ferroelectric transistor and to add a drive line necessary for reading a signal, thereby inactivating a non-destructive memory device that can simplify the circuit and reduce the chip area. To provide a circuit.

1 is a circuit diagram of an inert, non-destructive memory cell using a conventional ferroelectric gate capacitor.

FIG. 2 is a diagram illustrating a process of writing a signal of 1 only to a first cell and writing 0 to second, third, and fourth cells in an inactive, non-destructive memory cell using a ferroelectric gate capacitor according to the present invention. Circuit diagram showing the potential of the line.

Fig. 3 is a circuit diagram showing the potential of each line and the position of an output signal when reading a signal of 1 written in a first cell in an inactive, non-destructive memory cell using a ferroelectric gate capacitor according to the present invention.

The present invention to achieve the above object,

A field field effect transistor having a ferroelectric gate capacitor on the gate;

One access transistor for driving the field field effect transistor;

A first word line and a second word line orthogonal to each other; And

According to an aspect of the present invention, there is provided a circuit of an inert, non-destructive memory device, comprising one drive line and one sensing line that are orthogonal to each other and perpendicular to the first and second word lines.

The drain of the access transistor is connected to the upper electrode of the ferroelectric gate capacitor of the field field effect transistor.

The first word line is connected to a gate of the access transistor, and the second word line is connected to a source of the access transistor.

The drive line is connected to the source of the field field effect transistor, and the sensing line is connected to the drain of the field field effect transistor.

In order to write a signal to an arbitrary cell, the potentials of the first and second word lines are respectively adjusted so that the channel of the field field effect transistor is conducted only in a cell in which both are high.

In order to read the signal, the potential of an arbitrary drive line is increased, and at this time, the potential of only the sensing line connected to the cell in which the signal 1 is written is increased to read information at an arbitrary position.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a diagram illustrating a process of writing a signal of 1 only to a first cell and writing 0 to second, third, and fourth cells in an inactive, non-destructive memory cell using a ferroelectric gate capacitor according to the present invention. A circuit diagram showing a potential of a line. Fig. 3 is a circuit diagram showing the potential of each line and the position of an output signal when reading a signal of 1 written in a first cell in an inactive, non-destructive memory cell using a ferroelectric gate capacitor according to the present invention.

As shown in Figs. 2 and 3, an inert, non-destructive memory cell of the present invention has one field field effect transistor (FTr) having a ferroelectric gate capacitor on the gate thereof, and the drain thereof has the field field effect transistor (FTr). One access transistor (ATr) connected to the upper electrode of the ferroelectric gate capacitor of to drive the field effect transistor (FTr), the first and second word lines (W / L1, W / L2) orthogonal to each other, And one drive line D / L and one sensing line S / L that are orthogonal to each other and perpendicular to the first and second word lines W / L1 and W / L2, respectively.

In this case, the first word line W / L1 is connected to the gate of the access transistor ATr, and the second word line W / L2 is connected to the source thereof. The drive line D / L is connected to a source of the field field effect transistor FTr, and the sensing line S / L is connected to a drain thereof.

Referring to FIG. 2, the steps of writing information to a memory cell are described below.

For example, in order to conduct a channel of the field field effect transistor FTr, a bias is applied to the upper electrode of the ferroelectric gate capacitor. In this operation, the potential of the second word line W / L2 is set to high ( If the potential of the first word line W / L1 is also made high ( ), The access transistor ATr is operated to apply a desired bias to the upper electrode of the ferroelectric gate capacitor of the field field effect transistor FTr, thereby causing the channel of the field field effect transistor FTr to conduct. Thus, signal 1 is written into the cell. On the other hand, the signal 1 remains as it is by the spontaneous spontaneous polarization of the ferroelectric even when the signals of the first and second word lines W / L1 and W / L2 are removed, thereby functioning as an inactive memory. If you want to write zero in any cell, that is, if you want the channel of the field field effect transistor in that cell to be non-conductive, the first word line W / L1 or the second word line W / The potential of either L2) may be set low. As a result, since signal 1 is written only in the cell where the potential of both orthogonal word lines becomes high, random access to any cell becomes possible as in the case of DRAM.

Referring to FIG. 3, the steps of reading out the stored information are as follows.

First, the potentials of the first and second word lines W / L1 and W / L2 of all cells are set low ( Ie when the access transistors are all closed and the potential of the drive line (D / L) of any cell is set high ( ), Current flows through the open cell (that is, the cell where signal 1 is recorded) and reaches the sensing line (S / L). However, in the case of the cell in which the channel is closed (that is, the cell in which the signal 0 is recorded), the current does not reach the corresponding sensing line S / L. Accordingly, a sensing line connected to a cell in which signal 1 is recorded among cells connected to one drive line D / L by the arrangement of the drive lines D / L and the sensing line S / L which are orthogonal to each other ( ) Only the potential of the cell can be distinguished to distinguish the positions of the cells in which the signals 1 and 0 are recorded.

As described above, according to the circuit of an inactive, non-destructive memory device having a ferroelectric gate capacitor according to the present invention, in order to drive one transistor having a ferroelectric gate capacitor, only one access transistor is required and the signal is required for reading a signal. Add a driveline. Therefore, since one memory cell is composed of two transistors, the circuit can be simplified and the chip area can be reduced.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (6)

A field field effect transistor having a ferroelectric gate capacitor on the gate; One access transistor for driving the field field effect transistor; A first word line and a second word line orthogonal to each other; And And one drive line and one sensing line that are orthogonal to each other and orthogonal to the first and second word lines, respectively. The circuit of claim 1, wherein the drain of the access transistor is connected to an upper electrode of a ferroelectric gate capacitor of the field field effect transistor. 2. The circuit of claim 1, wherein the first word line is connected to a gate of the access transistor and the second word line is connected to a source of the access transistor. The circuit of claim 1, wherein the drive line is connected to a source of the field field effect transistor, and the sensing line is connected to a drain of the field field effect transistor. 2. The signal of claim 1, wherein the potential of the first and second word lines is adjusted so that the channel of the field field effect transistor is conducted only in a cell in which both are high. An inactive, nondestructive memory device circuit. 2. The inert, non-destructive memory of claim 1, wherein the potential of an arbitrary drive line is increased, wherein the potential of only the sensing line connected to the cell in which signal 1 is written is increased to read information at an arbitrary position. Circuit of the device.