KR100189693B1 - Semiconductor integrated circuit having logic gates - Google Patents

Abstract

Disclosed is a semiconductor integrated circuit including a switching element in a circuit portion in which b input gates among a input gates include common logic gates over c, and a node common across c cores is set to H level. (a, b, c are natural numbers). This switching element has a structure including at least one PMOS transistor.

Description

Semiconductor integrated circuit including logic gate

1 is a circuit diagram showing an example of a conventional decoder circuit.

2 is a circuit diagram showing the configuration of a read circuit and a data write circuit of a semiconductor memory according to the prior art.

3 is an embodiment of a semiconductor integrated circuit of the present invention, in which (a) shows a circuit diagram and (b) shows a logic diagram.

4 is a circuit diagram showing a composite circuit of a MOS transistor and a bipolar transistor.

5 is another embodiment of the present invention using the circuit of FIG. 4, wherein (a) shows a circuit diagram and (b) shows a logic diagram.

FIG. 6 is a circuit diagram showing a composite circuit of a MOS transistor and a bipolar transistor replacing part of the embodiment of FIG. 5. FIG.

Fig. 7 is a circuit diagram showing an embodiment in which a gate is grounded to a device having an output potential of H level, so that a p-type MOS transistor in an always on state is not used.

8 is a simulation operation waveform diagram showing the effect of shortening the operation delay time by adding a p-type MOS transistor.

9 is a logic diagram showing an example of a decoder circuit.

10A and 10B are a logic diagram and a circuit diagram of a conventional example, respectively, and a logic diagram and a circuit diagram according to the present invention.

11 is a block diagram showing the structure of a semiconductor memory.

12 is a block diagram showing the role of a decoder circuit.

13 is a circuit diagram showing an example of a circuit in which a decoder circuit is simplified.

14 is a logic diagram illustrating an example of a row decoder circuit.

FIG. 15 is a circuit diagram of 128 logic gates connected to the output terminal of the logic gate of FIG.

16 is a diagram showing a relationship between an output load capacity of a logic gate and a delay time.

Fig. 17 is a circuit diagram showing the structure of a read circuit and a data write circuit of a semiconductor memory according to the first embodiment of the present invention.

FIG. 18 is a circuit diagram showing the structure of a read circuit and a data write circuit of the semiconductor memory according to the second embodiment. FIG.

19 is a circuit diagram showing an overall configuration of a semiconductor memory according to the present embodiment.

20 is a timing chart for showing the operation of the semiconductor memory.

21 is a circuit diagram showing the configuration of a data line load circuit.

22 is a circuit diagram showing a configuration of a memory cell.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits including logic gates operating at high speed, and are particularly suitable for semiconductor devices having a memory function. For example, logic gates are used in decoder circuits of semiconductor devices having memory functions.

As a conventional technique, a decoder circuit composed of MOS transistors and having common input gates across eight logic gates is, for example, IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 23 NO.5, 1988 pp. 1068-1069.

A decoder circuit having an input gate in common across the eight logic gates of the above document is shown in FIG. This circuit shows eight two-input NAND gates.

In the figure, the drain of the first p-type MOS transistor whose gate is grounded is connected to the drain of the first n-type MOS transistor, and the source of the first n-type MOS transistor is the second input having the input gate in common. It is connected to the drain of an n-type MOS transistor. The second n-type MOS transistor is described in this figure as COMMON NMOS FOR 8 NANDS. These three MOS transistors constitute one NAND gate.

In general, the operation state of a two-input NAND gate is four.

Here, if the two input terminals are A and B, if both A and B are at L level, the output will be at H level, if A is at L level, and if B is at H level, the output will be at H level as well. Even when it is H level and B is L level, an output becomes H level. The output becomes L level only when both A and B become H level.

Here, when the gate of the first n-type MOS transistor is input A and the gate of the second n-type MOS transistor is input B, when either A or B is L level, the first n-type MOS transistor or The second n-type MOS transistor is turned off and the output becomes H level. When both A and B are at the H level, the first n-type MOS transistor and the second n-type MOS transistor are turned on and the output is at L level.

When the signal to the input gate B of the second n-type MOS transistor changes from the H level to the L level, whereby the output changes from the L level to the H level, the current flowing out of the first p-type MOS transistor is Through the on-state first n-type MOS transistor, the junction capacitance on the source side of the other n-type MOS transistor in the off state is charged, and then the output is brought to the H level. For this reason, there is a drawback that the time (operation delay time) from the change of the input signal to the change of the output signal becomes large.

The increase in the operation delay time is not limited to the case where the input gates are common to the eight logic gates described above, and increases as the number of common logic gates increases.

In general, the delay time from the input of the decoder circuit to the input of the decoder circuit and the output of the signal to the output to select one memory cell is determined by the number of logic gates constituting the decoder circuit.

For this reason, in order to speed up the decoder circuit, it is necessary to reduce the number of logic gates.

However, when the number of logic gates is reduced, as described later, the fan out number of the output portion of the logic gate increases and the gate capacitance connected to the output portion increases. This increases the delay time of the logic gate, and conversely, increases the delay time of the decoder circuit.

Therefore, the reduction in the number of stages of the logic gate and the number of fan-outs are in a trade-off relationship. Thus, a remarkable effect has not been obtained on speeding up the decoder circuit.

In recent years, memory integration is rapidly progressing. As the memory integration proceeds and the number of memory cells increases, the number of decoder circuits for selecting memory cells must also increase. This increase in number is a major problem for the high speed of the decoder circuit of a memory cell of high integration.

In addition, control of data writing and reading operations is also important in obtaining a memory device that operates at high speed.

As a data readout circuit and a data write circuit in a conventional semiconductor memory, it is known to be discussed in ISSCC, Digest of Technical Papers, pp. 186-187, 1988.

2 is a schematic diagram of a read circuit and a data write circuit in this conventional semiconductor memory.

는 데이터선 쌍, WL은 워드선, 2는 메모리셀, 101(M1), 102(M2)는 기입용의 트랜스퍼 게이트, M3, M4는 독출용 트랜스퍼 게이트, 3은 컬럼 선택신호(

)와 기입 제어신호(

)를 입력으로 하는 2입력 NOR 게이트, 4는 어드레스 A₀∼A_n에 의하여 컬럼 선택신호(

)를 발생하는 디코더 회로, 10은 메모리 셀의 데이터를 독출하기 위한 공통 독출선, 11은 메모리 셀에 데이터를 기입하기 위한 공통 기입선이다.1 is a data line load circuit, D,

Is a data line pair, WL is a word line, 2 is a memory cell, 101 (M1), 102 (M2) is a write transfer gate, M3 and M4 are read transfer gates, and 3 is a column select signal (

) And write control signal (

) A two-input NOR gates and outputs in-4 is the column select signal by the address A ₀ ~A _n (

A decoder circuit for generating data, 10 denotes a common read line for reading data of a memory cell, and 11 denotes a common write line for writing data to a memory cell.

In the common read line 10 and the common write line 11, a plurality of columns of data lines have read transfer gates 103 (M3), 104 (M4) and write transfer gates 101 (M1), 102 (M2). Connected via

The operation of the semiconductor memory according to this prior art will be described below.

)에 전위차로 되어 나타난다.In the operation of reading data from the memory cell, the data held in the memory cell 2 due to the rise of the word line WL causes the data line pair D,

Appears as a potential difference.

)는 H, 또 컬럼 선택신호(

)는 선택되어 있으므로 L이다. 따라서, 기입용 트랜스퍼 게이트(101(M1), 102(M2))는 오프, 독출용 트랜스퍼 게이트(103(M3), 104(M4)는 온이되고, 데이터선 쌍(D,

)에 나타난 전위차는 공통 독출선(10)에 전달되어 독출된다.In this case, since it is a read cycle, the write control signal (

) Is H, and the column select signal (

) Is L because it is selected. Therefore, the write transfer gates 101 (M1) and 102 (M2) are turned off, the read transfer gates 103 (M3) and 104 (M4) are turned on, and the data line pairs D,

The potential difference indicated by) is transmitted to the common read line 10 to be read out.

) 및 컬럼선택신호(

)가 모두 L가 되기 때문에, 기입용 트랜스퍼 게이트(101(M1), 102(M2)) 및 독출용 트랜스퍼 게이트(103(M3), 104(M4))가 모두 온이 된다.On the other hand, in the data write operation, the write control signal (

) And column selection signal

) Becomes L, so that both the write transfer gates 101 (M1) and 102 (M2) and the read transfer gates 103 (M3) and 104 (M4) are turned on.

)에 전달되어 선택되어 있는 워드선(

)의 메모리 셀(2)에 기입된다.Data written to the common write line 11 is passed through the write transfer gates 101 (M1) and 102 (M2) to the data line pairs D,

) Is passed to the selected word line (

In the memory cell 2).

The written data is also transferred from the data line to the common read line 10 via the read transfer gates 103 (M3) and 104 (M4).

As described above, reading and writing of the memory cell 2 are realized in the conventional semiconductor memory.

Since the semiconductor memory according to the prior art is configured as described above, the common read line is charged and discharged every time data writing to the memory cell occurs.

However, since a plurality of columns are connected, there is a problem that charging / discharging a common read line with a heavy load every time data writing to a memory cell occurs increases the time required for writing.

When the data writing to the memory cell is completed, the data line is not recovered from the writing potential to the potential upon reading in order to prevent the writing of wrong data into the memory cell or the delay of the read time immediately after the writing. In the prior art, however, the potential of the common read line with a heavy load must be recovered along with the data line, resulting in an increase in time required for recovery.

Since the increase in the capacity of the semiconductor memory causes an increase in the load of the common read line, such a problem is important in the recent demand for the increase in the capacity of the semiconductor memory and the high speed access.

It is also against the demand for low power consumption.

One object of the present invention is to provide a semiconductor integrated circuit including a logic gate capable of high-speed operation due to a small input gate capacity in spite of a large number of fan outs in a semiconductor integrated circuit including a plurality of logic gates. .

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a semiconductor integrated circuit including a logic gate in which b input gates of a input gates are common to c, wherein the nodes common to c are set to H level. It is to provide a semiconductor integrated circuit having a switching element in the circuit portion.

Specifically, a switching element having a node common to c of the logic gates as H level is a p-type MOS transistor.

In order to achieve the above object, the present invention also provides a semiconductor integrated circuit including a logic gate in which e input gates of the d input gates are common across f (where d, e, f are natural numbers). The circuit portion for changing the potential of the node where the logic gate is common over f is proposed as a semiconductor integrated circuit comprising a composite circuit of a MOS transistor and a bipolar transistor.

The reason why the operation delay time increases when the signal from the second n-type MOS transistor to the input gate B is changed from the H level to the L level, and thus the output changes from the L level to the H level is as follows. Same as

When the signal to the input gate B changes from the H level to the L level, the second n-type MOS transistor is turned off from the on state. However, the first n-type MOS transistor remains on. The current flowing from the first p-type MOS transistor flows through the first n-type MOS transistor in an on state, flows into the drain of the second n-type MOS transistor, and changes the potential of the drain portion of the second n-type MOS transistor to L. It is set to H state from a state. However, the current flowing from the first n-type MOS transistor flows into the source portions of the seven n-type MOS transistors that are in other off states, charges the junction capacitance of the seven source portions, and then sets the potential to H level. . Therefore, the time (operation delay time) from the input signal to the output signal is increased.

Thus, the drain of the second p-type MOS transistor is connected to the drain of the second n-type MOS transistor, and the gate of the second p-type MOS transistor is connected to the same input gate B as the second n-type MOS transistor. When connected, the operation delay time when the signal to the input gate B changes from the H level to the L level is shortened. This causes the signal to the gate B to change from the H level to the L level so that the second n-type MOS transistor is turned off from the on state, and the added p-type MOS transistor is turned off from the off state and current flows out. This is because the time for setting the potential of the drain portion of the second n-type MOS transistor to H level is shortened.

8A and 8B are simulation operation waveform diagrams showing the effect of shortening the operation delay time by adding a p-type MOS transistor. FIG. 8 (a) is a case of adding a p-type MOS transistor newly designed as shown in FIG. 8 (b). It can be seen from the figure that the operation delay time when the output potential changes from the L level to the H level is shortened by adding the p-type MOS transistor.

Hereinafter, the reason why the decoder circuit can be increased by using the logic gate described above will be described.

In order to speed up the decoder circuit that selects the highly integrated memory cell, it is necessary to reduce the number of logic gates constituting the decoder circuit. When l, m, n, o, and p are natural numbers, in the decoder circuit comprising l logic gates, the load capacitance C _OUT connected to the output of the n-th logic gate is the wiring capacitance (C _LINE ). The sum of the total input gate capacity (C _GATE ) and the next stage (n + 1 stage) logic gate

C _OUT = C _LINE + C _GATE (1)

Becomes

Meanwhile, the total input gate capacity C _GATE of the next logical gate is represented by the following equation.

C _GATE = F × C _G (2)

Where F is the fan-out count and C _G is the gate input capacity per one logic gate in the next stage.

If the number of logic gates is reduced to speed up the decoder circuit, as described below, the fan out F connected to the output terminal of the logic gate at the nth stage is increased. This results in an increase in the total input gate capacitance C _GATE of the next logical gate from equation (2), and an increase in the load capacitance C _TOTAL of the n-th logic gate from equation (1).

In general, as the output load capacity of the logic gate increases, the delay time tpd from the signal input to the logic gate to the output increases.

As a result, if the number of logic gates is to be reduced without any research on the logic gate, the delay of the logic gate is increased and the delay of the decoder circuit is increased.

Therefore, as shown in FIG. 9, in the p-th n + 1-th logic gate, if 0 input gates are common across p to one logic gate having m input gates, the total input gate capacitance (C _GATE ) is considerably smaller than when it is not used in common.

As a result, from the above formula (1), the load capacitance C _OUT connected to the output of the n-th logic gate can be reduced, and the delay time of the n-th logic gate can be shortened.

A general method of reducing the total input gate capacitance is to use a p-type MOS transistor whose gate is grounded in a device whose output of the logic gate of the conventional example of FIG. 10 (a) is H level. Therefore, as shown in Fig. 10 (d), by using a p-type MOS transistor whose gate is grounded in an element whose output of the logic gate is at the H level, and reducing the total input gate capacity by sharing the input gate described above, It can be remarkable. However, the above structure has the drawback that the time required for raising the potential of the output terminal of the circuit portion having the input gate in common becomes longer. For this reason, a p-type MOS transistor having a drain connected to the output end of the common circuit part is added to increase the potential of the output terminal of the circuit part having the input gate in common.

In addition, when the number of input gates in common is increased, a large load capacitance is connected to an output terminal of a circuit section having the input gate in common, and the delay of the logic gate of the n + 1st stage becomes large. This is due to the fact that the circuit portion having the input gate in common is composed only of the MOS transistors. In general, a logic gate of a composite circuit composed of a MOS transistor and a bipolar transistor has a feature of small increase in delay time with respect to an increase in load capacity from a logic gate composed of only a MOS transistor. Therefore, if the circuit portion having the input gate in common is a composite circuit of the MOS transistor and the bipolar transistor, the delay time of the logic gate of the n + 1 stage is also shortened, so that the delay time of the entire decoder circuit can be shortened.

Another object of the present invention is to speed up the writing time of data into a memory cell in a semiconductor memory and to speed up the data line recovery time.

In order to achieve the above object, the present invention is connected to a memory cell, a write line for writing data into the memory cell, a read line for reading data from the memory cell and a memory cell, and at the time of reading data from the memory cell. A data line connected to the read line via a first electronic switch connected to and interrupted when data is written into the memory cell, and connected to the write line via a second electronic switch when writing data to the memory cell; And a means for interrupting the first electronic switch connecting the data line and the read line at the time of data writing.

The present invention also provides a memory cell, a write line for writing data into the memory cell, a read line for reading data from the memory cell, a data read from the memory cell connected to the memory cell. Connected to the readout line via a first electronic switch connected at the time of release and writing of data into the memory cell and a second electronic switch blocking at the time of writing data into the memory cell, and at the time of writing data into the memory cell. A second semiconductor memory is provided, which has a data line connected to the write line via a third electronic switch connected to the second line.

In order to achieve the above object, a memory cell array consisting of memory cells arranged in a matrix, an address decoder for selecting memory cells, a common write line for writing data into each memory cell, and data of each memory cell are read out. A common read line and a data line of a memory cell selected when data is read from the memory cell are connected to the common read line, and a data line and a common read line of the selected memory cell are blocked when writing data to the memory cell. And a means for connecting the data line of the selected memory cell to the common write line when writing data to the memory cell.

In addition, it is preferable that semiconductor integrated circuits such as one-chip CPUs, cache memory LSIs, and other controller ICs contain the first, second, or third semiconductor memories. Moreover, it is preferable that the information processing apparatuses, such as a computer, provide the said 1, 2 or 3 semiconductor memory as the memory.

According to the first semiconductor memory of the present invention, the first electronic switch connects the data line and the read line at the time of reading data from the memory cell, and cuts off the data writing to the memory cell. The second electronic switch connects the data line and the write line at the time of writing data into the memory cell.

Further, according to the second semiconductor memory of the present invention, the first electronic switch is connected at the time of reading data from and writing data to the memory cell, and the second electronic switch is writing data to the memory cell. Block at o'clock.

Therefore, the data line and the read line are connected when reading data from the memory cell. The third electronic switch connects the data line and the write line at the time of writing data into the memory cell.

According to the third semiconductor memory of the present invention, the data line of the memory cell selected at the time of reading data from the memory cell is connected to the common read line, and the data of the memory cell selected at the time of writing data to the memory cell. Block the line and the common readout line. The data line of the selected memory cell at the time of writing data into the memory cell is connected to the common write line.

As described above, according to the first, second and third semiconductor memories, since the data line and the common read line are blocked at the time of data writing, the potential change of the common write line is not transmitted to the common read line having a large load.

That is, the common read line with a large load is separated from the data line at the time of writing, and the potential does not change.

Therefore, at the time of writing, the total capacity of the load to be charged and discharged is reduced, so that the writing time can be increased. Also, at the time of recovery, the potential of the common read line does not change, so only the data line is recovered, and as a result, the recovery time can be increased.

Also, information processing such as a semiconductor integrated circuit such as a one-chip CPU or a cache memory LSI incorporating the first, second or third semiconductor memory, or a computer having the first, second or third semiconductor memory as the memory. The device can access the memory at high speed, and thus can achieve high performance.

EMBODIMENT OF THE INVENTION Hereinafter, with reference to drawings, embodiment of this invention is described in detail.

11 is a block diagram of a semiconductor memory. Generally, a semiconductor memory consists of an input buffer circuit, a decoder circuit (row decoder circuit, a column decoder circuit), a memory cell array, a sense amplifier, and an output buffer circuit. In the figure, the input buffer circuit receives an external input signal and outputs a signal to the decoder circuit. The row decoder circuit receives a signal from the input buffer circuit and applies a row address to the memory array. The column decoder circuit receives a signal from the input buffer circuit and applies an address to the memory cell array. In the memory cell array, memory cells of 2 ^M rows x 2 ^N columns are arranged in a matrix.

The sense amplifier amplifies the signal of the memory cell selected by the decoder circuit and transmits the amplified signal to the output buffy circuit. The output buoy circuit receives a signal from the sense amplifier and outputs the signal to the outside.

Semiconductor memory is required for large capacity, high speed, and low power consumption. As for the large capacity and low power consumption, a CMOS memory having only a MOS transistor is most suitable. However, since the speed of the CMOS memory is slower than that of the bipolar memory, efforts for high speed have continued. The speed of the memory is defined as the delay time (access time) from the input of the signal to the input buffer circuit and the output of the signal to the output buffer circuit. To speed up the access time, it is necessary to speed up each of the input buffer circuit, decoder circuit, sense amplifier, and output buffer circuit. In a high speed memory, the speed of each of these circuits is several nsec to several tens nsec, and the improvement of each speed is followed by a large speed improvement as a whole of the memory system. In particular, the speed improvement of the decoder circuit is effective because it contributes to the speed of the subsequent sense amplifier, the output buffer circuit, etc. in addition to the speed of its own.

As shown in FIG. 12, the decoder circuit has a structure in which a plurality of logic gates are arranged in plural stages in both the row decoder circuit and the column decoder circuit. One row of memory cells arranged in a matrix from the row decoder circuit is selected, and one column of memory cells is selected by the column decoder circuit, so that one memory cell in which they cross is selected.

13 shows an example of a simplified decoder circuit, in which (a) shows a case in which the logic gate constituting the decoder circuit has a three-stage configuration, and (b) shows a case in a two-stage configuration.

In the logic gate three-stage configuration shown in Fig. 13A, the logic gates 101 to 107 are two input gates. Complementary input signals 1301, 1302, 1303, and 1304 are input to and output from 1307. The fan out number of the logic gates 1301, 1302, 1303, and 1304 (denoted by f 占 in the figure) is 8, and the fan out number of the logic gates 1305 and 1306 is 8, respectively.

On the other hand, in the logic gate two-stage configuration shown in Fig. 13B, the logic gates 1311 and 1312 are four input gates, and 1313 are two input gates. The fan out number of the logic gates 1311 and 1312 is 16.

As a result, when the number of logic gates constituting the decoder circuit is reduced, it can be seen that the fan out number of logic gates increases.

14 is a logic diagram of one embodiment of a row decoder circuit. A decoder circuit for selecting a highly integrated memory cell is usually composed of logic gates of three stages to one stage (where L is a natural number), but in this method, the logic gate has a two-stage structure to speed up the decoder circuit. have. Again, this embodiment is composed of three input and four input logic gates, a signal is input to the logic gates of 1401 to 1416, one logic gate is selected from A1 to p128, and a row address is applied to the memory cell array. In this case, the number of fan outs of the first-stage logic gate is 128.

FIG. 15 is an example of a circuit diagram of 128 logic gates connected to the output terminal of the logic gate 1401 of FIG. As a result, as described in Equation (2) above, when the gate input capacitance per stage is C _G , C _G is the sum of the gate capacitances of the p-type MOS transistor and the n-type MOS transistor, and is applied to the output terminal of the logic gate 1401. The total gate capacity connected is 128 x C _G. Since the relationship between the output load capacity of the logic gate and the delay time is in a proportional relationship as shown in FIG. 16, the delay time increases as the output load capacity increases.

Here, the fan-out number of the first-stage logic gate is 128, but this is only an example. In the future, as the capacity of memory cells increases, the number of fan outs will inevitably increase. This is a great obstacle to the speeding up of the decoder circuit.

An embodiment of a semiconductor integrated circuit according to the present invention for solving this problem will be described with reference to FIG. FIG. 3A is a circuit diagram of one embodiment of a logic gate according to the present invention, and FIG. 3B is a logic diagram replacing the circuit of FIG. 3A, and shows a form in which a plurality of NAND gates having a plurality of input gates are arranged.

In FIG. 3A, MAIP to MANP are p-type MOS transistors, MAIN to MANN are n-type MOS transistors, and the drain of the p-type MOS transistor and the drain of the n-type MOS transistor are connected to the output terminals OUT Al to OUT AN. have. The drains of the p-type MOS transistor MAP and the n-type MOS transistor MAN having an input AAl connected to the gate are N (N is a natural number) sources of the n-type MOS transistors MALN to MANN (node AA). ) As can be seen from FIG. 3B, the input AAl is a common input to N NAND gates.

When MAlP to MANP, MAlN to MANN, MAD, and MAN are the blocks Al, the blocks A2 to AM have the same structure as the blocks Al. M blocks (M is a natural number) are connected to a source (source BB) of a p-type MOS transistor MBP and an n-type MOS transistor MBN. If blocks Al to AM, MBP and MBN are referred to as blocks Bl, blocks B2 to BL have the same configuration as blocks Bl. Hereinafter, a plurality of blocks are constructed with the same idea.

As described above, in the configuration in which the input gates of the plurality of NAND gates are common, the input gate capacity is markedly smaller than in the conventional configuration in which the input gates commonly used so far are not common. As a result, the output load capacity of the logic gate connected to the front end is reduced, and the delay time of the logic gate is shortened. In general, since the logic gates have a configuration in which several logic gates are serially slowed, the delay time of the entire logic gate group is shortened. In addition, since the operation principle of the circuit shown in FIG. 3A is the same as that of the circuit of FIG. 5 mentioned later, it abbreviate | omits here.

In the example of FIG. 3A, L, M, and N, which represent the number of blocks, are assumed to be natural numbers, indicating that arbitrary numbers are possible. However, when L, M, and N become too large numbers, large capacities are connected to the nodes AA, BB, CC,... In such a case, the delay time when the signal to the inputs AAl, BB1, CC1... Changes and the potential of the output outs A1... This is due to the use of a CMOS inverter consisting of MAP and MAN, MBP and MBN, ... to change the potentials of the nodes AA, BB, CC, ....

On the other hand, as shown in FIG. 16, the Bic MOS inverter, which is a composite circuit of the MOS transistor and the bipolar transistor, has a small increase in delay time with respect to the increase in the output load capacity as compared with the CMOS inverter. Therefore, if the CMOS inverter circuit portion consisting of MAP, MAN, MBP, and MBN ... is composed of a plurality of circuits of the MOS transistor and the bipolar transistor shown in Figs. 4A and 4B, the short logic of delay time is achieved even if the number of L, M, and N increases. The gate can be configured.

5A is a circuit diagram of another embodiment of the present invention. 5b is a logic diagram of the circuit diagram of FIG. 5a. In FIG. 5A, MA1 to MA8 in the block 1 are p-type MOS transistors MA9 to MA16 are n-type MOS transistors, MB1 is a p-type MOS transistor, and MB2 is an n-type MOS transistor. Blocks 2 to 16 are configured in node 1 in the same configuration as block 1. Block 17 is a composite circuit of a MOS transistor and a bipolar transistor in the common gate input circuit section. MC1 in the block 17 is a p-type MOS transistor, MC2 and MC3 are n-type MOS transistors, and QC1 is an npn low sum bipolar transistor.

As can be seen from FIG. 5A and FIG. 5B, the block 1 represents eight three-input NAND gates. Since there are 15 blocks (blocks 2 to 16) having the above configuration, the total number of NAND gates is 8 x 16 = 128. One of the three inputs of the NAND gate is common over 128. Here, 128 common input nodes are set to C, and eight common input nodes are set to B1 to B16.

In the decoder circuit having such a logic gate configuration, the fan-out count of the preceding logic gate does not change to 128 as compared with the examples of FIGS. 14 and 15 described above, but the total gate input capacity is 1 × C _C. Since the delay time of the preceding logic gate is shortened, the decoder circuit can be speeded up.

Although the embodiment of Fig. 5A sets the number of common input gates to 128, although this is an example, the present circuit has the above advantages, but its operation is more complicated than the conventional example shown in Fig. 15.

Therefore, the circuit operation of FIG. 5A will be described below. In addition, since the operation of the blocks 2 to 16 is exactly the same as the block 1, the operation of the block 1 will be described below.

In the block 1, since the gates of the p-type MOS transistors MA1 to MA8 are grounded, they are always turned on and operate like a resistor. The p-type MOS transistor MB1 and the n-type MOS transistor MB2 form a CMOS inverter with respect to the input B1, and the output 2 is connected with the sources of eight n-type MOS transistors MA9 to MA16. . The block 17 is an inverter circuit composed of a composite circuit of a MOS transistor and a bipolar transistor, and an inverted signal of the input c is outputted to the node 1. The inverter circuit of the block 17 can also be operated once in a CMOS inverter circuit composed of a p-type MOS transistor and an n-type MOS transistor. However, since 128 junction capacities are connected to the output terminal 1 of the block 17, and the load capacitance is extremely large, the delay time of the block 17 becomes extremely extreme compared to the case where a signal is input to another input gate. In this respect, the BiCMOS method of this embodiment is advantageous.

The logic of the three input NAND gate is equal to eight. Even at three inputs, the output is at the L level only at the H level. Otherwise, the output is at the H level. Hereinafter, each case will be described.

One NAND gate N1 is formed in the p-type MOS transistors MA1 and MB1, the n-type MOS transistors MA9 and MB2 and the block 17 in the block 1. In this case, when the potentials of the input nodes All, Bl, and C are at the H level, the n-type MOS transistor MA9 is in an ON state, the p-type MOS transistor MB1 is in an off state, and the n-type MOS transistor MB2 is in an on state. Becomes On the other hand, the p-type MOS transistor MC1 and the n-type MOS transistor MC2 in the block 17 form a CMOS inverter, the p-type MOS transistor MC1 is in an off state, and the n-type MOS transistor MC2 is on. In this state, the output of the CMOS inverter, that is, the potential of the base C1 of the bipolar transistor Q1 becomes L level, and the bipolar transistor Q1 is turned off. The n-type MOS transistor MC3 is turned on. As described above, the current from the p-type MOS transistor MA1 in the always-on state flows through the path of the n-type MOS transistors MA9, MB2, and MC3 ground. The potential of the output (out1) is determined by the resistance ratios of the p-type MOS transistor MA1 and the n-type MOS transistors MA9, MB2, and MC3, and the out 1 becomes L level.

Next, when the potentials of the nodes A1 and B1 are at the H level, and only the potential of the node C is at the L level, the p-type MOS transistor MC1 is on and the n-type MOS transistor MC2 is off. Since the node C1 is at the L level, the bipolar transistor QC1 is turned on. Since the n-type MOS transistor MC3 is in an off state, the node 1 becomes H level. From this, since the gate-source potential of the n-type MOS transistor MB2 that is in the on state becomes equal to or less than the threshold voltage Vth of the n-type MOS transistor, the n-type MOS transistor MB2 is turned off to output (out 1). ) Becomes H level.

Even when the nodes A11 and C are at the H level and the node B1 is at the L level, it can be considered that they are exactly the same as above. In this case, since B1 is at the L level, the p-type MOS transistor MB1 is turned on and the n-type MOS transistor MB2 is turned off, so that the node 1 is at the H level. As a result, the output (out 1) becomes H level.

Since the output (out 1) is the same as that described above also in the cases other than H, the description thereof is omitted.

In FIG. 5, although the block 17, which is a common input unit of 128 NAND gates, is a composite circuit of a MOS transistor and a bipolar transistor, the potential of the output node node 1 is used as the falling element, and the n-type MOS transistor MC3 is used. The above operation can be performed even if the portion is changed in FIG. 6A (a) using a bipolar transistor. However, when the inputs A11 and B1 change from H level to L level at the H level, and the output (out 1) changes from L level to H level, there is a property that a large delay time is required.

Further, the block 17 can also be configured with only the n-type MOS transistor shown in FIG. 6B. However, in the output stage 1, when the load capacitance such as the junction capacitance or the wiring capacitance of the n-type MOS transistor increases, the delay time when only the potential of the input C changes is increased.

In addition, the CMOS inverter section including the p-type MOS transistor MB1 and the n-type MOS transistor MB2, which are eight common input sections, may be an inverter circuit of a composite circuit of MOS transistors and bipolar transistors as shown in FIGS. 6C and 6D. Do.

5 shows 128 NAND gates, and in this case, one NAND gate is selected from the 128 NAND gates. From this, power consumption was not a problem even when a p-type MOS transistor whose gate was grounded to a device having an output potential of H level and always turned on. However, power consumption becomes a problem when a plurality of NAND gates are selected at the same time. For example, when eight NAND gates are simultaneously selected from 128 NAND gates, the gate is grounded, and the normal current from the always-on p-type MOS transistor is eight times that of the logic gate, and eight times the power consumption. Will be consumed. Therefore, it is not preferable to use a p-type MOS transistor whose gate is grounded to an element whose output potential is H level and is always on.

7 is a logic gate having a logic configuration in which eight NAND gates are selected from 128 NAND gates. The basic configuration is the same as that in FIG. 5, but a p-type MOS transistor in which the gate is grounded and is always on is not used for an element having an output potential of H level. Therefore, the power consumption is as good as when one NAND gate is selected.

The operation of the circuit of FIG. 7 is the same as the operation of FIG. 5 and is therefore obviously omitted.

5 and 7 have 8 and 4 input gates in common, but this is merely an example, and the number is not particularly specified.

Although the above embodiments have been described only with respect to the decoder circuit of the semiconductor memory, the present invention need not be limited only to the decoder circuit, and the present invention can be applied to any semiconductor integrated circuit in which a plurality of logic gates are arranged and a logic relationship of the multi-input signal is required. .

According to the present invention, a semiconductor integrated circuit including a decoder circuit capable of high-speed operation with a small input capacity despite a large fan out number is obtained.

17 shows the structure of a read circuit and a data write circuit of a semiconductor memory according to the present invention.

는 데이터선 쌍, WL은 워드선, 2는 메모리 셀, 101(M1), 102(M2)는 기입용의 트랜스퍼 게이트, 103(M3), 104(M4)는 독출용의 트랜스퍼 게이트(3), 컬럼 선택신호(

)와 기입제어신호(

)를 입력하는 2입력 NOR 게이트, VCC는 전원 전압을 나타낸다.1 is a data line load circuit, D,

Is a data line pair, WL is a word line, 2 is a memory cell, 101 (M1), 102 (M2) is a transfer gate for writing, 103 (M3), 104 (M4) is a transfer gate 3 for reading, Column select signal

) And write control signal (

) Is a two-input NOR gate, where VCC represents the supply voltage.

)가 L일 때, 103(M3), 104(M4)의 게이트 전압을 H레벨로 올리는 풀업(MOS), 106(M6)은 기입 제어신호(

)가 H일 때 컬럼 선택신호(

)의 신호를 103(M3), 104(M4)의 게이트에 전하는 트랜스퍼 게이트, 4는 어드레스(A₀내지 A_n)에 의하여 컬럼 선택신호(

)를 발생하는 디코더 회로, 10은 메모리 셀의 데이터를 독출하기 위한 공통 독출선, 11은 메모리 셀에 데이터를 기입하기 위한 공통 기입선이다. 공통 독출선(10) 및 공통 기입선(11)에는 도면 이외의 다른 복수의 컬럼의 메모리 셀의 데이터선이 독출용 트랜스퍼 게이트(103(M3)), (104(M4)) 및 기입용 트랜스퍼 게이트 (101(M1)), (102(M2))를 거쳐 접속되어 있다.105 (M5) denotes a write control signal (

When L is L, the pull-up (MOS) for raising the gate voltage of 103 (M3) and 104 (M4) to the H level is performed.

Column selection signal when

) Is a transfer gate that transmits a signal of 103 (M3), 104 (M4) to a gate, and 4 is a column selection signal (A ₀ through A _n ).

A decoder circuit for generating data, 10 denotes a common read line for reading data of a memory cell, and 11 denotes a common write line for writing data to a memory cell. In the common read line 10 and the common write line 11, data lines of memory cells of a plurality of columns other than the drawings are read transfer gates 103 (M3), 104 (M4) and write transfer gates. It is connected via 101 (M1) and 102 (M2).

The operation will be described below.

)에 전위차가 되어 나타난다.In the data read operation from the memory cell, first, the data held in the memory cell 2 due to the rise of the word line WL is stored in the data line pair D,.

Appears as a potential difference.

)는 H 또 컬럼 선택신호(

)는 선택되어 있기 때문에 L이다.In this case, since it is a read cycle, the write control signal (

) Is the H or column select signal (

) Is L because it is selected.

Therefore, the output of the two-input NOR gate 3 becomes L, and the write transfer gates 101 (M1) and 102 (M2) are turned off.

)는 트랜스퍼 게이트(M6)를 거쳐 103(M3), 104(M4)의 게이트에 전달되고, 독출용 트랜스퍼 게이트(103(M3), (104(M4))는 온이 된다. 이리하여 데이터 선 쌍(D,

)에 나타난 전위차는 공통독출선(10)에 전해져 독출된다.In addition, since the transfer gate M6 is turned on, the column select signal (

Is transferred to the gates 103 (M3) and 104 (M4) via the transfer gate M6, and the read transfer gates 103 (M3) and 104 (M4) are turned on. (D,

The potential difference indicated by) is transmitted to the common read line 10 to be read out.

) 및 컬럼 신택신호(

)는 공통으로 L이다. 이에 의하여 2입력 NOR 게이트(3) 출력은 H 가 되고, 기입용 트랜스퍼게이트(101(M1)), (102(M2))는 온하다. 또, 기입제어신호(

)에 의하여 트랜스퍼 게이트(106(M6))는 오프, 풀업 MOS(105(M5))는 온이되고, 게이트 전압이 풀업된 독출용 트랜스퍼 게이트(103(M3)), (104(M4)는 오프가 된다. 따라서, 공통 기입선(11)에 기입된 데이터는 기입용 트랜스퍼 게이트(101(M1)), (102(M2))를 거쳐 데이터 선 쌍(D,

)에 전달되고 메모리 셀(2)에 기입된다.On the other hand, in the data write operation room, the write control signal (

) And column syntax signal (

) Is commonly L. As a result, the output of the two-input NOR gate 3 becomes H, and the write transfer gates 101 (M1) and 102 (M2) are turned on. In addition, the write control signal (

The transfer gate 106 (M6) is turned off, the pull-up MOS 105 (M5) is turned on, and the read transfer gates 103 (M3) and 104 (M4) are turned off when the gate voltage is pulled up. Therefore, the data written in the common write line 11 passes through the write transfer gates 101 (M1) and 102 (M2) to the data line pair D,

) And write to the memory cell 2.

)에서 강제적으로 행할 수가 있고, 데이터 기입시에 있어서 데이터 선쌍(D,

)에 기입된 데이터가 공통 독출선(10)에 전해지는 일이 없다.According to the present embodiment, the control for turning off the read transfer gates 103 (M3) and 104 (M4) is set to the write control signal (

), And data line pairs (D,

The data written in the parentheses) are not transmitted to the common read line 10.

Therefore, data written to the memory cell via the data line is not transmitted to the common read line having a large load capacity. That is, since the potential of the common read line does not change due to data writing, the total capacity of the load to be charged and discharged at the time of writing is reduced, and the writing time can be increased. Also, in the recovery of returning the data line or the like from the potential immediately after writing to the potential that can be read, the potential of the common read line does not change from the potential at the time of data reading. It has the effect of speeding up.

18 shows the structure of the read circuit and the data write circuit of the semiconductor memory according to the first embodiment.

In the figure, the same parts as those of the semiconductor memory shown in the previous embodiment (see Article 17) are denoted by the same reference numerals, and description thereof is omitted.

)에 의하여 제어되는 제1의 독출용 트랜스퍼 게이트, 107(M7), 108(M8)은 기입 제어신호(

)의 반전신호에 의하여 제어되는 제2의 독출용 트랜스퍼 게이트, 5는 기입 제어신호(

)를 반전 출력하는 인버터회로이다.103 (M3) and 104 (M4) are column selection signals (

The first read transfer gates 107 (M7) and 108 (M8) controlled by the < RTI ID = 0.0 >

The second read transfer gate controlled by the inversion signal of < RTI ID = 0.0 >

) Is an inverter circuit for inverting output.

The operation will be described below.

)에 전위차로 되어 나타난다.In the operation of reading data from the memory cell, first, the data held in the memory cell 2 due to the rise of the word line WL is placed on the data line D,

Appears as a potential difference.

)는 H 또, 컬럼 선택신호(

)는 선택되어 있기 때문에 L이다. 따라서, 2입력 NOR 게이트(3)의 출력은 L가 되고, 기입용 트랜스퍼 게이트(101(M1)), (102(M2))는 오프가 된다.In this case, since it is a read cycle, the write control signal (

) Is H or column select signal (

) Is L because it is selected. Therefore, the output of the two-input NOR gate 3 becomes L, and the write transfer gates 101 (M1) and 102 (M2) are turned off.

)가 L이므로 온이 되고, 제2의 독출용 트랜스퍼 게이트(107(M7)), (108(M8))는 기입 제어신호(

)의 반전 신호가 L이므로 온이 된다.Further, the first read transfer gates 103 (M3) and 104 (M4) are column select signals (

Since L is on, the second read transfer gates 107 (M7) and 108 (M8) are write control signals (

Since the inversion signal of) is L, the signal is turned on.

)에 나타난 전위차는 제1의 독출용 트랜스퍼 게이트(101(M1)), (102(M2)) 및 제2의 독출용 트랜스퍼 게이트(107(M7)), (108(M8))를 거쳐 공통 독출선(10)에 전달되어 독출된다.Therefore, the data line pair D,

The potential difference shown in Fig. 8) is passed through the first read transfer gates 101 (M1), 102 (M2) and the second read transfer gates 107 (M7), 108 (M8). It is delivered to the starting line 10 and read.

) 및 컬럼 선택신호(

)는 모두 L이다.On the other hand, during a data write operation, a write control signal (

) And column select signal (

) Are all L.

)의 반전신호는 H가 된다.Thereby, the output of the two-input NOR gate 3 receives the H write control signal (

), The inversion signal becomes H.

)에 전달되고, 메모리 셀(2)에 기입된다.Therefore, the write transfer gates 101 (M1) and 102 (M2) are on, and the first read transfer gates 103 (M3) and 104 (M4) are also turned on and the second read-out is used. The transfer gates 107 (M7) and 108 (M8) are turned off, and data written to the common write line 11 passes through the write transfer gates 101 (M1) and 102 (M2). Data line pair (D,

) Is written to the memory cell 2.

)에 기입된 데이터가 공통 독출선(10)에 전달되는 일이 없다.That is, at the time of writing, the second read transfer gate provided in series with the first read transfer gates 103 (M3) and 104 (M4) can be forcibly turned off, and the data line pair ( D,

The data written in) is not transmitted to the common read line 10.

As described above, according to the present embodiment, the first read transfer gates 103 (M3) and 104 (M4) and the second read transfer gates 107 (M7) and 108 (M8). Are connected in series, so that the read delay time is longer than that of the previous embodiment, but the load of data written to the memory cell via the data line is similar to the previous embodiment with simple and easy control. Delivery to large doses of common reader can be ruled out.

That is, since the potential of the common read line does not change due to data writing, the total capacity of the load to be charged and discharged is reduced at the time of writing, thereby increasing the writing time. In the recovery at which the data line or the like is returned from the potential immediately after writing to the position where the data can be read, the potential of the common read line does not change from the potential at the time of data reading. There is an effect that can speed up the time.

Here, a case where the read circuit and the data write circuit shown in the embodiment of FIG. 17 is used for the entire structure of the semiconductor memory using the read circuit and the data write circuit according to the above embodiment will be described.

19 shows the overall configuration of a semiconductor memory according to the present embodiment.

는 칩 셀렉트신호,

는 라이트 인에이블신호 101은 X계의 어드레스 버퍼, 105는 Y계의 어드레스 버퍼, 102는 출력버퍼, 103은 입력버퍼, 104는 칩 셀렉트신호(

)와 라이트 인에이블신호(

)로부터 기입 제어신호(

및

)를 발생하는 컨트롤 회로, 105는 메모리 셀로부터 독출된 미소 전압을 증폭하는 센스증폭기, 150 내지 15m는 X계 어드레스버퍼출력(130)을 디코드하는 디코더회로, 160 내지 16m는 워드선 드라이버, WL_o내지 WL_m은 워드선, 115는 입력버퍼 출력을 반전하는 인버터 회로, 116, 117은 입력 버퍼출력과 기입 제어신호(

)를 입력으로하는 2입력 NOR 회로, 118, 119는 기입 드라이버, 170으로부터 17n은 Y계 어드레스 버퍼출력(131)을 디코드하는 디코더회로, 1은 데이터선 부하회로, -Do,

내지 Dn,

은 데이터선 쌍, 2는 메모리 셀, 1010(M1), 1020(M2) 내지 101n(M1), 102n(M2)은 기입용 트랜스퍼 게이트, 1030(M3), 1040(M4) 내지 103n(M3), 104n(M4)은 독출용 트랜스퍼 게이트, 18 내지 18n은 컬럼 선택신호(

내지

)를 반전 출력하는 인버터회로, VCC는 전원전압, 1050(M5), 105n(M5)은 기입 제어신호(

)가 L일때독출용 트랜스퍼 게이트 1030(M3), 1040(M4) 내지 103n(M3), 104n(M4)의 게이트 전압을 H레벨로 올리는 풀업 MOS, 1060(M6) 내지 106n(M6)은 기입 제어신호(W1)가 H일 때, 컬럼 선택신호(

내지

)의 신호를 독출용 트랜스퍼 게이트1030(M3), 1040(M4) 내지 103n(M3), 104n(M4))에 전하는 트랜스퍼 게이트, CD(R), VD(R)는 공통 독출선 쌍, CD(W),

는 공통기입 선 쌍이다.In the figure, A _X is the address signal of the X system, A _Y is the address signal of the Y system, Dout is the output signal, Din is the input signal,

Is the chip select signal,

The write enable signal 101 is an X-based address buffer, 105 is an Y-based address buffer, 102 is an output buffer, 103 is an input buffer, 104 is a chip select signal (

) And light enable signal (

From the write control signal (

And

Is a sense amplifier for amplifying the minute voltage read from the memory cell, 150-15m is a decoder circuit for decoding the X-based address buffer output 130, 160-16m is a word line driver, WL _o WL _m is a word line, 115 is an inverter circuit for inverting the input buffer output, 116, 117 is an input buffer output and a write control signal (

Is a two-input NOR circuit for inputting (), 118 and 119 are write drivers, 170 to 17n are decoder circuits for decoding the Y-based address buffer output 131, 1 is a data line load circuit, -Do,

To Dn,

Is a data line pair, 2 is a memory cell, 1010 (M1), 1020 (M2) to 101n (M1), 102n (M2) is a write transfer gate, 1030 (M3), 1040 (M4) to 103n (M3), 104n (M4) is a read transfer gate, and 18 to 18n are column select signals (

To

Inverter circuit for inverting output, VCC is the power supply voltage, 1050 (M5), 105n (M5) is the write control signal (

) Is L, the pull-up MOS for raising the gate voltages of the read transfer gates 1030 (M3), 1040 (M4) to 103n (M3), and 104n (M4) to H level, and write control for 1060 (M6) to 106n (M6). When the signal W1 is H, the column select signal (

To

) Transfer gates to the read transfer gates 1030 (M3), 1040 (M4) to 103n (M3), and 104n (M4), and CD (R) and VD (R) are common readout pairs and CD ( W),

Is the common fill line pair.

Hereinafter, the operation of the semiconductor memory will be described with reference to FIG. 20 showing transitions between the input / output signals and the internal signals of the semiconductor memory.

신호가 H,

신호가 L의 기입 사이클에 있어서, 기입 제어신호(

,

)는 모두 L가 된다. 입력버퍼(103)로부터 입력된 데이터는 116 및 117의 2입력 NOR 회로를 거쳐 기입 드라이버(118, 119)에 의하여 공통 기입선 쌍(CD(W),

)에 기입된다.

The signal is H,

In the write cycle of L, the write control signal (

,

) Becomes L. The data input from the input buffer 103 is passed through the two input NOR circuits of 116 and 117 by the write drivers 118 and 119 to form a common pair of write lines (CD (W),

).

)에 기입된 데이터는 워드선(WL_o∼WL_n) 및 컬럼 선택신호(

∼

)에 의하여 선택된 1개의 메모리 셀에, 기입용 트랜스퍼 게이트(1010(M1), 1020(M2)∼101n(M1), 102n(M2))를 거쳐 기입된다.Common write line pair (CD (W),

Data written on the word lines WL _{o to} WL _n and the column select signal (

To

The memory cell is written to one memory cell selected by?) Via the write transfer gates 1010 (M1), 1020 (M2) to 101n (M1), and 102n (M2).

)를 받은 풀업(MOS 1050(M5)∼105n(M5))에 의하여 H레벨로 풀업되어 있기 때문에 모두 오프가 되어, 공통 독출선 쌍(CD(R),

)에는 데이터는 기입되지 않는다.At this time, the read transfer gates 1030 (M3), 1040 (M4) to 103n (M3), and 104n (M4) have their gate voltages corresponding to the write control signal (

Are pulled up to the H level by the pull-ups (MOS 1050 (M5) to 105n (M5)) which are then turned off to all the common read line pairs (CD (R),

) Is not written.

신호가 L,

신호가 H의 독출 사이클에 있어서는 기입 제어신호(

∼

)는 모두 H가 된다.Meanwhile,

The signal is L,

When the signal reads H, the write control signal (

To

) Becomes H.

∼

)는 트랜스퍼 게이트(1060(M6)∼106n(M6))를 거쳐 독출용 트랜스퍼 게이트의 게이트에 전달되고, 공통기입 선 쌍(CD(W),

)은 강제적으로 H레벨이 된다.That is, the column select signal (

To

) Is transmitted to the gate of the read transfer gate via the transfer gates 1060 (M6) to 106n (M6), and the common write line pair (CD (W),

) Is forced to H level.

∼

)에 의하여 선택된 1개의 메모리 셀의 데이터는 독출용 트랜스퍼 게이트(1030(M3), 1040(M4)∼103n(M3), 104n(M4))를 거쳐 공통 독출선(CD(R),

)에 독출되고, 센스업(106)에 의하여 증폭되어 출력된다.Therefore, the word lines WL _{o to} WL _m and the column select signal (

To

The data of one memory cell selected by?) Is passed through the read transfer gates 1030 (M3), 1040 (M4) to 103n (M3), and 104n (M4) to the common read line (CD (R),

) Is amplified and output by the sense-up 106.

In this case, the write transfer gates 1010 (M1), 1020 (M2) to 101n (M1), and 102n (M2) are all turned off because the bias voltage is not applied as long as the NMOS is turned on between the gate and the source. Next, FIG. 21 shows an example of the configuration of the data line load circuit 1.

는 데이터 선 쌍이다.In the figure, VCC is a power supply voltage, GND is a ground potential, 501 and 504 are PMOSFETs, W3 is a write control signal, D,

Is a data line pair.

In the data line load circuit, in the read cycle, the write control signal W3 becomes L level, the PMOSFETs 501, 502, 503, 504 are all turned on, and the data line pairs D, D are strongly pulled up. .

)은 상시 온하고 있는 PMOSFET(501, 502)에 의하여 약하게 풀업된다.In the write cycle, the write control signal W3 becomes H level, and the PMOSFETs 504 and 504 are turned off. Therefore, the data line pair (D,

) Is weakly pulled up by the PMOSFETs 501 and 502 which are always on.

Next, a configuration example of the memory cell 2 is shown in FIG.

는 데이터선 쌍, VCC는 전원전압, GND는 접지전위, R1, R2는 고저항 601∼604는 NMOSFET이다.In the figure, WL denotes a word line, D,

Is the data line pair, VCC is the power supply voltage, GND is the ground potential, and R1 and R2 are the high resistances 601-604 for the NMOSFET.

Reading of data from this memory cell and writing of data to the memory cell are performed when the word line WL is at the H level and the NMOSFETs 601 and 602 are turned on.

As described above, in the semiconductor memory according to the present embodiment, data written to the memory cell via the data line is not transmitted to the common read line having a large load capacity. That is, since the potential of the common read line does not change due to data writing, the total capacity of the load to be charged and discharged decreases at the time of writing, so that the writing time can be increased, and data lines and the like can be read from the potential immediately after writing. In the recovery to return to the potential, the potential of the common read line does not change from the potential at the time of reading data, so that recovering is only the data line, and as a result, the recovery time can be increased.

As described above, according to the present invention, it is possible to provide a semiconductor memory capable of speeding up the writing time of data into a memory cell, and to provide a semiconductor memory capable of speeding up the data line recovery time.

Claims (112)

(delete) (delete) (delete) (delete) (delete) (delete) (delete) (delete) (delete) (New) A first including a plurality of logic gates including a first input terminal, an output terminal, and a common connection terminal for receiving one of the first input signals, and a transistor having first and second electrodes and a control electrode. A second switching element including a switching element, another transistor having first and second electrodes and a control electrode, and commonly connected to control electrodes of the transistors of the first and second switching elements to receive a second input signal And a second input terminal provided at a common connection portion of the second electrodes of the transistors of the first and second switching elements. The second output terminal is coupled to the common connection terminal of all the logic gates to form a common node; And the first and second switching elements operate complementarily to each other in response to the second input signal. (New) The transistor of claim 10, wherein the transistor of the first switching element is an NMOS transistor having a gate, a source, and a drain, and the transistor of the second switching element is a PMOS transistor having a gate, a source, and a drain. And a gate of a transistor and the gate of the PM0S transistor are coupled to the second input terminal, and the drain of the NMOS and the PMOS transistor is coupled to the common node. (Newly formed) The logic circuit of claim 10, wherein each logic gate comprises a first M0S transistor having a gate coupled to a corresponding first input terminal and a source-drain path coupled between the output terminal and the common node. A semiconductor integrated circuit comprising a logic gate characterized by. (New) A first input terminal for receiving a first input signal, each of the plurality of logic gates coupled to the common node, the first switching element coupled to the common node, and the second switching coupled to the common node An element; The first and second switching elements are coupled to a second input terminal for receiving a second input signal common to the plurality of logic gates; The first and second switching elements operate complementary to each other in response to the second input signal; Each of the logic gates has a conductivity type channel opposite to the conductivity type of the first M0S transistor having a gate coupled to the first input terminal and a source-drain path coupled to the common node, and the channel region of the first M0S transistor. A second MOS transistor comprising a region having a region, wherein the second MOS transistor is supplied with a source-drain path and a predetermined reference potential coupled in series with the source-drain path of the first MOS transistor between a power supply terminal and the common node. A semiconductor integrated circuit comprising a logic gate, characterized in that it has a gate. (New) The semiconductor integrated circuit according to claim 13, wherein the predetermined reference potential is set to a value which keeps the second MOS transistor always on. (New) The semiconductor integrated circuit according to claim 13, wherein the first MOS transistor is an NMOS transistor, and the second MOS transistor is a PM0S transistor. (New) The semiconductor integrated circuit according to claim 15, wherein the predetermined reference potential is set to ground which keeps the second MOS transistor always on. (New) The method of claim 15, wherein the first switching device comprises a second NMOS transistor, the second switching device comprises a second PMOS transistor, and the gates of the second NMOS transistor and the second PMOS transistor are respectively formed in the first switching device. And a logic gate coupled to a second input terminal, wherein source-drain paths of the second NMOS and second PMOS transistors are coupled to the common node, respectively. (New) The semiconductor integrated circuit according to claim 17, wherein the predetermined reference potential is set to ground which keeps the second MOS transistor always on. (New) The semiconductor integrated circuit according to claim 13, wherein the output terminal for each logic gate is provided between the source and drain paths of the first and second MOS transistors. (New) The semiconductor integrated circuit according to claim 17, wherein the output terminal for each logic gate is provided between the source and drain paths of the first and second MOS transistors. (New) A first input terminal for receiving a first input signal, each of the plurality of logic gates coupled to a common node, the first switching element coupled to the common node, the second switching element coupled to the common node And a switching circuit coupled to the common node; The first and second switching elements are coupled to a second input terminal for receiving a second input signal common to the plurality of logic gates; The first and second switching elements operate complementary to each other in response to the second input signal; And the switching circuit is coupled to a third input terminal for receiving a third input signal. (New) A first input terminal for receiving a first input signal, each of the plurality of logic gates coupled to a common node, the first switching element coupled to the common node, the second switching element coupled to the common node And a switching circuit coupled to the common node; The first switching device includes an NMOS transistor, the second switching device includes a PMOS transistor, and gates of the NMOS transistor and the PM0S transistor receive a second input signal common to the plurality of logic gates. Coupled to a second input terminal, the source-drain paths of the NMOS transistor and the PM0S transistor coupled to the common node; The switching circuit is connected to the common node through the source-drain path of the NMOS transistor of the first switching device, the switching circuit is coupled to a third input terminal for receiving a third input signal. A semiconductor integrated circuit comprising a logic gate. (New) The semiconductor integrated circuit according to claim 21, wherein the switching circuit comprises at least one field effect transistor and at least one bipolar transistor. (Newly formed) The semiconductor integrated circuit comprising a logic gate according to claim 22, wherein the switching circuit comprises at least one electrical effect transistor and at least one bipolar transistor. (Newly established) a plurality of logic gates each including a first input terminal for receiving a first input signal, coupled to a common node, a first switching element coupled to the common node, and all the logic gates provided to the common node It comprises a plurality of second switching elements coupled to; The first switching element and the second switching element are coupled to a second input terminal receiving a second input signal common to the plurality of logic gates, and the second switching element responds to the second input signal when coupled. And a logic gate to operate in a manner complementary to that of the first switching element. (Newly formed) The channel of claim 1, wherein each logic gate has a first M0S transistor having a gate coupled to the corresponding first input terminal and a source-drain path coupled to the common node. The second MOS transistor includes a second MOS transistor having a channel region of a conductivity type opposite to that of a region, wherein the second MOS transistor includes a source-drain path and a logic gate connected in series between a source-drain path and a power potential of the first MOS transistor. And a logic gate coupled to the first input terminal of the semiconductor integrated circuit. (Newly formed) The device of claim 26, wherein the first switching device comprises an NMOS transistor, the second switching device comprises at least one PM0S transistor, and the gate and the first gate of the NMOS transistor of the first switching device. A gate of the PM0S transistor of the second switching element is coupled to the second input terminal, and a source-drain path of the NMOS transistor of the first switching element is coupled to the common node, the NMOS transistor and the second switching The device is a semiconductor integrated circuit comprising a logic gate, characterized in that coupled to provide a pull-down and pull-up level action to the common node in response to the second input signal. . (New) The semiconductor integrated circuit according to claim 27, wherein the first MOS transistor is an NMOS transistor and the second MOS transistor is a PM0S transistor. (Newly formed) further comprising a third switching circuit coupled to the common node via the source-drain path of the NMOS transistor of the first switching element; And the third switching circuit is coupled to a third input terminal for receiving a third input signal. (New) The semiconductor integrated circuit according to claim 29, wherein the third switching circuit includes at least one field effect transistor and at least one bipolar transistor. (New) The semiconductor integrated circuit according to claim 10, wherein the logic gate is a decoder logic gate that decodes input signals applied to the first and second input terminals. (New) The semiconductor integrated circuit according to claim 22, wherein the logic gate is a decoder logic gate that decodes an input signal applied to the first, second and third input terminals. (New) The semiconductor integrated circuit according to claim 25, wherein the logic gate is a decoder logic gate that decodes input signals applied to the first and second input terminals. (New) The semiconductor integrated circuit according to claim 30, wherein the logic gate is a decoder logic gate that decodes an input signal applied to the first, second and third input terminals. (New) The NMOS transistor according to claim 11, wherein the NMOS and PMOS transistors are coupled together as a CMOS inverter, and in the CMOS inverter, the PMOS transistor has a source coupled to receive an operating voltage of the logic circuit, and the NMOS transistor Has a source coupled to receive a logic signal output by another CMOS inverter or a predetermined reference potential, wherein the PMOS and NMOS transistors have a drain commonly connected to the common node and a gate commonly connected to the second input terminal. A semiconductor integrated circuit comprising a logic gate, characterized in that it comprises a. (Newly formed) The apparatus according to claim 10, further comprising a third switching element coupled to the common node; And the third switching element is coupled to a third input terminal for receiving a third input signal. (New) A first input terminal for receiving a first input signal, each of the plurality of logic gates coupled to a common node, the first switching element coupled to the common node, the second switching element coupled to the common node And a third switching device coupled to the common node; The first switching device includes an NMOS transistor, the second switching device includes a PMOS transistor, and gates of the NMOS transistor and the PM0S transistor receive a second input signal common to the plurality of logic gates. Coupled to a second input terminal, the source-drain paths of the NMOS transistor and the PMOS transistor coupled to the common node; The third switching device is connected to the common node through the source-drain path of the NMOS transistor of the first switching device, and the third switching device is coupled to a third input terminal for receiving a third input signal. A semiconductor integrated circuit comprising a logic gate, characterized in that. (Newly formed) further comprising: a third switching element coupled to the common node via the source-drain path of the NMOS transistor of the first switching element; And the third switching element is coupled to a third input terminal for receiving a third input signal. (New) The semiconductor integrated circuit according to claim 18, wherein the output terminal for each logic gate is provided between the source-drain paths of the first and second MOS transistors. (Newly) 40. The apparatus according to claim 39, further comprising a third switching element and a fourth switching element; The third switching device comprises a third NMOS transistor and the fourth switching device comprises a third PMOS transistor, the third NMOS and PMOS transistors are gates coupled to a third input terminal for receiving a third input signal, and A source-drain path commonly coupled at the drain side to a second common node serving as an output for providing a logic conversion of the third input signal; The plurality of logic gates includes first and second groups of logic gates; Each NMOS transistor of the first group of logic gates has a source connected to the common node and a drain of the second NMOS and PMOS transistors, while the source of the second NMOS transistor is an output of the third NMOS and PMOS transistors. And a logic gate connected to said second common node which is commonly coupled to a second group of logic gates. (New) The semiconductor integrated circuit according to claim 21, wherein the switching circuit is a logic inverter for providing a logic conversion of the third input signal to the common node. (New) The semiconductor integrated circuit according to claim 42, wherein the logic inverter is a BiCMOS inverter. (New) The semiconductor integrated circuit according to claim 22, wherein the switching circuit is a logic inverter for providing a logic conversion of the third input signal to the common node. (New) The semiconductor integrated circuit according to claim 43, wherein the logic inverter is a BiCMOS inverter. (New) The semiconductor integrated circuit according to claim 37, wherein the logic gate is a decoder logic gate that decodes an input signal applied to the first, second and third input terminals. (New) The semiconductor integrated circuit according to claim 38, wherein the logic gate is a decoder logic gate that decodes an input signal applied to the first, second and third input terminals. (New) The semiconductor according to claim 25, wherein the first switching element and the plurality of second switching elements are coupled to provide a logic conversion of the second input signal at the common node. Integrated circuits. (New) The semiconductor integrated circuit according to claim 25, wherein the first switching element and the plurality of second switching elements comprise a BiCMOS inverter. (Newly formed) The method according to claim 25, wherein the first switching element comprises an NMOS transistor and the second switching element comprises a CMOS conversion circuit and a pull-up connected bipolar transistor, while the CMOS conversion circuit includes a gate of the NMOS transistor. And an input unit commonly coupled to the second input signal to receive the second input signal, and an output unit coupled to the pull-up connected bipolar transistor, wherein the bipolar transistor is commonly coupled to the NMOS transistor to operate as a pull-down transistor. A logic integrated circuit comprising a logic gate, characterized by providing an output to the common node operating as another common input terminal of the logic gate. (New) The semiconductor integrated circuit according to claim 49, wherein the bipolar transistor and the NMOS transistor are connected in series across a voltage potential corresponding to an operating potential of the logic circuit. (Newly formed) The method of claim 26, wherein the first switching element comprises an NMOS transistor and the second switching element comprises a CM0S conversion circuit and a pull-up connected bipolar transistor, while the CMOS conversion circuit is a gate of the NMOS transistor. And an input coupled to the second input signal to receive the second input signal, and an output coupled to the pull-up connected bipolar transistor, wherein the bipolar transistor is commonly coupled to the NMOS transistor to operate as a pull-down transistor. A logic integrated circuit comprising a logic gate, characterized by providing an output to the common node operating as another common input terminal of the logic gate. (New) The semiconductor integrated circuit according to claim 51, wherein the bipolar transistor and the NMOS transistor are connected in series across a voltage potential that corresponds to an operating potential of the logic circuit. (Newly formed) a plurality of memory cells; Selecting means for selecting a predetermined memory cell of the memory cells for reading and writing operations; Data lines respectively coupled to the memory cells; A common write line coupled to the data line through a write transfer gate; A common read line coupled to the data line through a read transfer gate; And a predetermined data line of the data lines coupled to the write transfer gate and the read transfer gate to electrically connect the common read line to the common write line during a write operation. And control means for separating from the predetermined data line. (Newly formed) 53. The write transfer gate according to claim 53, wherein the write transfer gate includes a MOS transistor having a channel of a first conductivity type, and the read transfer gate is a channel of a second conductivity type opposite to the first conductivity type. And a MOS transistor having a semiconductor memory. (Newly formed) a plurality of memory cells; Means for selecting a predetermined memory cell among the memory cells; A write line for writing data into the selected memory cell; A readout line for reading data from the selected memory cell; A memory cell connected to the memory cell, the selected memory cell being connected to the read line when reading data from the selected memory cell, and the selected memory cell being connected to the writing line through a second switch when writing data; A data line connected to the read line through one switch; And means for operating the first switch to separate the data line from the read line when writing data. (Newly formed) a plurality of memory cells; Means for selecting a predetermined memory cell among the memory cells; A write line for writing data into the selected memory cell; A readout line for reading data from the selected memory cell; And a first switch connected to the memory cell, the first switch forming a closed circuit when reading data from the memory cell and writing data into the memory cell, and a second switch forming an open circuit when writing data to the memory cell. And a data line connected to the read line through a third switch which forms a closed circuit when writing data into the memory cell. (Newly formed) a memory cell array consisting of memory cells arranged in a matrix; An address decoder for selecting a predetermined memory cell among the memory cells; A common write line for writing data into each of the selected memory cells; A common read line reading data from each of the selected memory cells; The data line of the memory cell selected when reading data from the memory cell is connected to the common read line, and the data line and the common read line of the memory cell selected when writing data to the memory cell. Means for breaking a connection; And means for connecting the data line of the memory cell selected when writing data to the memory cell to the common write line. (Newly formed) 55. The memory cell of claim 54, wherein the plurality of memory cells are arranged in rows and columns, while a row of each memory cell is associated with a respective word line and each column of memory cells is at least A semiconductor memory characterized by being associated with one data line. (Newly formed) The data line according to claim 58, wherein the data line is selectively electrically connected to the common write line via the source-drain path of the MOS transistor of the corresponding transfer gate in response to the column select signal in the write mode, wherein And the rows are selected in response to corresponding word line selection signals, wherein said selection means includes an address decoding circuit for outputting row and column selection signals. (New) The semiconductor memory according to claim 59, wherein the address decoding circuit includes a row and column decoder coupled to receive input signals corresponding to X addresses and Y addresses, respectively. (New) The apparatus of claim 60, wherein the at least one row and column decoder comprises: a plurality of logic gates comprising a first input terminal, an output terminal and a common connection terminal for receiving one of the first input signals; A first switching element comprising a transistor having a second electrode and a control electrode, a second switching element comprising another transistor having first and second electrodes and a control electrode, and controlling the transistors of the first and second switching elements A second input terminal commonly connected to the electrode to receive the second input signal, and a second output terminal provided to the common connection portion of the second electrode of the transistors of the first and second switching elements; The first input signal and the second input signal represent an input address; The second output terminal is coupled to the common connection terminal of all the plurality of logic gates to form a common node; And the first and second switching elements operate complementarily to each other in response to the second input signal. (New) The transistor of claim 61, wherein the transistor of the first switching element is an NMOS transistor having a gate, a source, and a drain, and the transistor of the second switching element is a PMOS transistor having a gate, a source, and a drain. And a gate of the PMOS transistor is coupled to the second input terminal, and a drain of the NMOS transistor and the PMOS transistor is coupled to the common node. (Newly formed) The NMOS transistor according to claim 62, wherein the NMOS and PMOS transistors are coupled together with a CMOS inverter, wherein the PMOS transistor has a source coupled to receive an operating voltage of the memory, and the NMOS transistor is And a source coupled to receive a logic signal output or a predetermined reference potential output by another CMOS inverter having an input to which a control signal is fed, wherein the PMOS and NMOS transistors are connected to the common node and the drain and the first source. A semiconductor memory comprising a gate connected to two input terminals in common. (Newly formed) 63. The logic circuit of claim 61, wherein each logic gate comprises a first MOS transistor having a gate coupled to a corresponding first input terminal, and a source-drain path coupled between the output terminal and the common node. A semiconductor memory, characterized in that. (Newly constructed) 60. The method of claim 60, wherein at least one of said row and column decoders comprises: a plurality of logic gates, each coupled to a common node, comprising a first input terminal for receiving a first input signal; A first switching element, and a second switching element coupled to the common node; The first and second switching elements are common to the plurality of logic gates. A second input terminal for receiving a second input signal; The first and second switching elements operate complementarily to each other in response to the second input signal; The first input signal and the second input signal represent an input address; Each of the logic gates may include a first MOS transistor having a gate coupled to the first input terminal and a source-drain path coupled to the common node, and a conductive channel opposite to the conductivity type of the channel region of the first MOS transistor. The second MOS transistor includes a region having a region, wherein the second MOS transistor is supplied with a source-drain path and a predetermined reference potential coupled in series with the source-drain path of the first MOS transistor between a power supply terminal and the common node. A semiconductor memory having a gate. (New) The semiconductor memory according to claim 65, wherein the predetermined reference potential is set to a value which keeps the second MOS transistor always on. (New) The semiconductor memory according to claim 65, wherein the first MOS transistor is an NMOS transistor, and the second MOS transistor is a PMOS transistor. (Newly formed) The method of claim 67, wherein the first switching element comprises a second NMOS transistor and the second switching element comprises a second PMOS transistor, while the second NMOS transistor and the second PMOS transistor are respectively the second input. And a gate coupled to the terminal and a source-drain path coupled to the common node, respectively. (New) The semiconductor memory according to claim 68, wherein the predetermined reference potential is set to ground which keeps the second MOS transistor always on. (New) The semiconductor memory according to claim 69, wherein the output terminal for each logic gate is provided between the source-drain paths of the first and second MOS transistors. (Newly formed) according to claim 70, further comprising a third switching element and a fourth switching element; The third switching device comprises a third NMOS transistor and the fourth switching device comprises a PMOS transistor, while the third NMOS and PMOS transistors are gate coupled to a third input terminal for receiving a third input signal, and A source-drain path commonly coupled at the drain side to a second common node serving as an output for providing a logic conversion of the third input signal; The plurality of logic gates includes first and second groups of logic gates; Each NMOS transistor of the first group of logic gates has a source connected to the common node and a drain of the second NMOS and PMOS transistors, while the source of the second NMOS transistor is an output of the third NMOS and PMOS transistors. And a second common node which is commonly coupled to a second group of logic gates. (Newly constructed) 60. The method of claim 60, wherein at least one of said row and column decoders comprises: a plurality of logic gates, each coupled to a common node, comprising a first input terminal for receiving a first input signal; A first switching device, a second switching device coupled to the common node, and a switching circuit coupled to the common node; The first and second switching elements are coupled to a second input terminal for receiving a second input signal common to the plurality of logic gates; The first and second switching elements operate complementary to each other in response to the second input signal; And the switching circuit is coupled to a third input terminal for receiving a third input signal, wherein the third input signal indicates an input address together with the first input signal and the second input signal. (New) The semiconductor memory according to claim 72, wherein said switching circuit comprises at least one field effect transistor and at least one bipolar transistor. (Newly constructed) 60. The method of claim 60, wherein at least one of said row and column decoders comprises: a plurality of logic gates, each coupled to a common node, comprising a first input terminal for receiving a first input signal; A first switching element, a second switching element coupled to the common node, and a switching circuit coupled to the common node; The first switching device includes an NMOS transistor, the second switching device includes a PMOS transistor, and gates of the NMOS transistor and the PM0S transistor receive a second input signal common to the plurality of logic gates. Coupled to a second input terminal, the source-drain paths of the NMOS transistor and the PMOS transistor coupled to the common node; The switching circuit is connected to the common node through the source-drain path of the NMOS transistor of the first switching device, and the switching circuit is coupled to a third input terminal for receiving a third input signal. And an input signal indicates an input address together with the first input signal and the second input signal. (New) The semiconductor memory according to claim 74, wherein said switching circuit comprises at least one field effect transistor and at least one bipolar transistor. (Newly constructed) 60. The at least one row and column decoder of claim 60, further comprising: a plurality of logic gates coupled to a common node, each of the plurality of logic gates comprising a first input terminal for receiving a first input signal; A first switching element, and a plurality of second switching elements provided to all of the logic gates and coupled to the common node; The first switching element and the second switching element are coupled to a second input terminal receiving a second input signal common to the plurality of logic gates, and the second switching element responds to the second input signal when coupled. Operating in a manner complementary to that of the first switching element, wherein the first input signal and the second input signal represent an input address. 77. The channel of claim 76, wherein each logic gate has a gate coupled to the corresponding first input terminal and a source-drain path coupled to the common node, and a channel of the first MOS transistor. The second MOS transistor includes a second MOS transistor having a channel region of a conductivity type opposite to that of a region, wherein the second MOS transistor includes a source-drain path and a logic gate connected in series between a power supply potential and a source-drain path of the first MOS transistor. And a gate coupled to the first input terminal of the semiconductor memory. (Newly formed) wherein the first switching element comprises an NMOS transistor, the second switching element comprises at least one PMOS transistor, the gate of the NMOS transistor of the first switching element and the Gates of the PMOS transistors of the second switching device are respectively coupled to the second input terminal, source-drain paths of the NMOS transistors of the first switching device are coupled to the common node, and the NMOS transistors and the second And a switching device is coupled to provide a pulldown and a pullup level action to the common node in response to the second input signal. (New) The semiconductor memory according to claim 78, wherein the first MOS transistor is an NMOS transistor, and the second MOS transistor is a PMOS transistor. (Newly formed) further comprising a switching circuit coupled to the common node via the source-drain path of the NMOS transistor of the first switching element; And the switching circuit is coupled to a third input terminal for receiving a third input signal. (New) The semiconductor memory according to claim 80, wherein the third switching circuit includes at least one field effect transistor and at least one bipolar transistor. (Newly formed) 77. The gate switching circuit of claim 77, wherein the first switching device comprises an NMOS transistor and the second switching device comprises a CMOS conversion circuit and a pull-up connected bipolar transistor, while the CMOS conversion circuit includes a gate of the NMOS transistor. And an input coupled to receive the second input signal, the output coupled to the pull-up connected bipolar transistor, wherein the bipolar transistor and the NMOS transistor cross a voltage potential corresponding to an operating potential of the memory. And a common coupling of the NMOS transistor and the bipolar transistor connected in series, and acting as a pull-down transistor to provide an output to the common node operating as another common input terminal of the plurality of logic gates. 77. The semiconductor memory according to claim 76, wherein said first switching element and said plurality of second switching elements are coupled to provide a logic conversion of said second input signal at said common node. (New) The semiconductor memory according to claim 76, wherein the first switching element and the plurality of second switching elements constitute a BiCMOS inverter. (Newly formed) The circuit of claim 76, wherein the first switching element comprises an NMOS transistor and the second switching element comprises a CM0S conversion circuit and a pull-up connected bipolar transistor, while the CMOS conversion circuit includes a gate of the NMOS transistor. And an input coupled to receive the second input signal, the output coupled to the pull-up connected bipolar transistor, wherein the bipolar transistor and the NMOS transistor cross a voltage potential corresponding to an operating potential of the memory. And a common coupling of the NMOS transistor and the bipolar transistor connected in series, and acting as a pull-down transistor to provide an output to the common node operating as another common input terminal of the plurality of logic gates. (Newly constructed) 60. The method of claim 60, wherein the at least one row and column decoder comprises: a plurality of logic gates coupled to a common node, the plurality of logic gates coupled to a common node, the first input terminal receiving a first input signal; A first switching element, a second switching element coupled to the common node, and a third switching element coupled to the common node; The first switching device includes an NMOS transistor, the second switching device includes a PMOS transistor, and gates of the NMOS transistor and the PM0S transistor receive a second input signal common to the plurality of logic gates. Coupled to a second input terminal, the source-drain paths of the NMOS transistor and the PM0S transistor coupled to the common node; The third switching device is connected to the common node through the source-drain path of the NMOS transistor of the first switching device, and the third switching device is coupled to a third input terminal for receiving a third input signal. And the first to third input signals respectively indicate input addresses for the second and third signals to function as control signals. (Newly established) a plurality of memory cells for storing data, an input buffer providing an address signal in response to an input address, a decoder coupled to the input buffer to decode the address signal and selecting the memory cell in response to the address signal A sense amplifier coupled to receive data from the selected memory cell, and an output buffer coupled to the sense amplifier to provide an output data signal; The decoder comprises: a plurality of logic gates including a first input terminal, an output terminal, and a common connection terminal for receiving one of a first input signal, and a first transistor including a first and second electrodes and a control electrode. A second switching element including a first switching element, another transistor having first and second electrodes and a control electrode, and a second input signal connected in common to the control electrodes of the transistors of the first and second switching elements A second input terminal configured to receive a second input terminal and a second output terminal provided to a common connection of the second electrodes of the transistors of the first and second switching elements; The second output terminal is coupled to the common connection terminal of all the logic gates to form a common node; The first and second switching elements operate complementary to each other in response to the second input signal; And the first input signal and the second input signal correspond to the address signal for which the second input signal functions as a control signal. (New) The transistor of claim 87, wherein the transistor of the first switching element is an NMOS transistor having a gate, a source, and a drain, and the transistor of the second switching element is a PMOS transistor having a gate, a source, and a drain. And a gate of a transistor and the PM0S transistor is coupled to the second input terminal, and the drain of the NMOS and the PMOS transistor is coupled to the common node. (Newly) 89. The NMOS transistor of claim 88, wherein the NMOS and PMOS transistors are coupled together with a CMOS inverter, and in the CM0S inverter, the PM0S transistor has a source coupled to receive an operating voltage of the memory, and the NMOS transistor is And a source coupled to receive a predetermined reference potential or a logic signal output by another CMOS inverter having an input to which another control signal is fed, wherein the PMOS and NMOS transistors are connected to the common node and the drain and the first source; And a gate connected to the two input terminals in common. (Newly formed) 87. The transistor of claim 87, wherein each logic gate includes a first M0S transistor having a gate coupled to a corresponding first input terminal, and a source-drain path coupled between the output terminal and the common node. Memory device, characterized in that. (Newly established) a plurality of memory cells for storing data, an input buffer providing an address signal in response to an input address, a decoder coupled to the input buffer to decode the address signal and selecting the memory cell in response to the address signal A sense amplifier coupled to receive data from the selected memory cell, and an output buffer coupled to the sense amplifier to provide an output data signal; The decoder includes a first input terminal for receiving a first input signal, each of the plurality of logic gates coupled to a common node, the first switching element coupled to the common node, and the second coupled to the common node. It comprises a switching element; The first and second switching elements are coupled to a second input terminal for receiving a second input signal common to the plurality of logic gates, and the first and second switching elements are responsive to the second input signal. Work complementary to each other; The first input signal and the second input signal correspond to the address signal for which the second input signal functions as a control signal; Each of the logic gates has a conductivity type channel opposite to the conductivity type of the first M0S transistor having a gate coupled to the first input terminal and a source-drain path coupled to the common node, and the channel region of the first M0S transistor. Including a second MOS transistor having an area, the second M0S transistor is supplied with a source-drain path and a predetermined reference potential coupled in series with the source-drain path of the first M0S transistor between a power supply terminal and the common node. And a gate, wherein each output terminal for the logic gate is provided between the source-drain paths of the first and second MOS transistors. (New) The memory device according to claim 91, wherein the predetermined reference potential is set to a value which keeps the second MOS transistor always on. (Newly formed) 93. The apparatus of claim 92, further comprising a third switching element coupled to the common node via a main current path of the first switching element; wherein the third switching element receives a third input signal; Coupled to a third input terminal, wherein the third input signal is another control signal of the decoder corresponding to the address signal. (New) The memory device according to claim 91, wherein the first MOS transistor is an NMOS transistor, and the second MOS transistor is a PMOS transistor. 94. The gate of claim 94, wherein the first switching device comprises a second NMOS transistor, the second switching device comprises a second PMOS transistor, and the gates of the second NMOS transistor and the second PMOS transistor are respectively formed in the second switching device. And a source-drain paths of the second NMOS and the second PMOS transistor are coupled to the common node. (New) The memory device according to claim 95, wherein the predetermined reference potential is set to a value which keeps the second MOS transistor always on. (Newly constructed) 96. The apparatus according to claim 96, further comprising a third switching element and a fourth switching element; The third switching device comprises a third NMOS transistor and the fourth switching device comprises a third PMOS transistor, while the third NMOS and PMOS transistors are gate coupled to a third input terminal for receiving a third input signal, and A source-drain path commonly coupled at the drain side to a second common node serving as an output for providing a logic conversion of the third input signal; The plurality of logic gates includes first and second groups of logic gates; Each NMOS transistor of the first group of logic gates has a source connected to the common node and a drain of the second NMOS and PMOS transistors, while the source of the second NMOS transistor is an output of the third NMOS and PMOS transistors. And a second common node which is commonly coupled to a second group of logic gates. (Newly established) a plurality of memory cells for storing data, an input buffer providing an address signal in response to an input address, a decoder coupled to the input buffer to decode the address signal and selecting the memory cell in response to the address signal A sense amplifier coupled to receive data from the selected memory cell, and an output buffer coupled to the sense amplifier to provide an output data signal; The decoder may include: a first input terminal configured to receive a first input signal, each of a plurality of logic gates coupled to a common node, a first switching element coupled to the common node, and a second switching coupled to the common node An element, and a switching circuit coupled to the common node; The first and second switching elements are coupled to a second input terminal for receiving a second input signal common to the plurality of logic gates; The first and second switching elements operate complementary to each other in response to the second input signal; The switching circuit is coupled to a third input terminal for receiving a third input signal, while the third input signal together with the first input signal and the second input signal corresponds to the address signal. Device. 99. The memory device of claim 98, wherein the switching circuit comprises at least one field effect transistor and at least one bipolar transistor. (Newly established) a plurality of memory cells for storing data, an input buffer providing an address signal in response to an input address, a decoder coupled to the input buffer to decode the address signal and selecting the memory cell in response to the address signal A sense amplifier coupled to receive data from the selected memory cell, and an output buffer coupled to the sense amplifier to provide an output data signal; The decoder may include: a first input terminal configured to receive a first input signal, each of a plurality of logic gates coupled to a common node, a first switching element coupled to the common node, and a second switching coupled to the common node An element, and a switching circuit coupled to the common node; The first switching device includes an NMOS transistor, the second switching device includes a PMOS transistor, and the gates of the NMOS transistor and the PMOS transistor receive a second input signal common to the plurality of logic gates. Coupled to a second input terminal, the source-drain paths of the NMOS transistor and the PM0S transistor coupled to the common node; The switching circuit is connected to the common node through the source-drain path of the NMOS transistor of the first switching device, and the switching circuit is coupled to a third input terminal for receiving a third input signal. And the third input signal together with the input signal and the second input signal correspond to the address signal. (New) The memory device according to claim 100, wherein the switching circuit comprises at least one field effect transistor and at least one bipolar transistor. (Newly established) a plurality of memory cells for storing data, an input buffer providing an address signal in response to an input address, a decoder coupled to the input buffer to decode the address signal and selecting the memory cell in response to the address signal A sense amplifier coupled to receive data from the selected memory cell, and an output buffer coupled to the sense amplifier to provide an output data signal; The decoder includes: a plurality of logic gates each coupled to a common node, a first input terminal receiving a first input signal, a first switching element coupled to the common node, and all the logic gates provided to the common gate; A plurality of second switching elements coupled to the node; The first switching element and the second switching element are coupled to a second input terminal receiving a second input signal common to the plurality of logic gates, and the second switching element responds to the second input signal when coupled. Operating in a manner complementary to that of the first switching element, wherein the first input signal and the second input signal correspond to the address signal at which the second input signal functions as a control signal. Memory device. (Newly formed) 102. The channel of claim 1, wherein each logic gate has a first M0S transistor having a gate coupled to the corresponding first input terminal and a source-drain path coupled to the common node. A second MOS transistor having a channel region of a conductivity type opposite to that of a region, wherein the second MOS transistor has a source-drain path and a logic gate connected in series between a source-drain path and a power potential of the first MOS transistor; And a gate coupled to the first input terminal of the memory device. 104. The gate of claim 103, wherein the first switching device comprises an NMOS transistor, the second switching device comprises at least one PMOS transistor, and the gate and the first gate of the NMOS transistor of the first switching device. A gate of the PMOS transistor of the second switching element is respectively coupled to the second input terminal, a source-drain path of the NMOS transistor of the first switching element is coupled to the common node, the NMOS transistor and the second switching And a device is coupled to provide pull-down and pull-up level action to the common node in response to the second input signal. (New) The memory device of claim 104, wherein the first MOS transistor is an NMOS transistor and the second MOS transistor is a PMOS transistor. (Newly) 107. The circuit according to claim 105, further comprising a switching circuit coupled to the common node through the source-drain path of the NMOS transistor of the first switching element; And the switching circuit is coupled to a third input terminal for receiving a third input signal. (New) The memory device according to claim 106, wherein the third switching circuit includes at least one field effect transistor and at least one bipolar transistor. (Newly formed) 102. The method of claim 103, wherein the first switching element comprises an NMOS transistor and the second switching element comprises a CMOS conversion circuit and a pull-up connected bipolar transistor, while the CMOS conversion circuit includes a gate of the NMOS transistor. And an input coupled to receive the second input signal, and an output coupled to the pull-up connected bipolar transistor, wherein the bipolar transistor and the NMOS transistor cross a voltage potential corresponding to an operational potential of the decoder. And a common connection of the NMOS transistor and the bipolar transistor connected in series, and acting as a pull-down transistor to provide an output to the common node operating as another common input terminal of the plurality of logic gates. (New) The memory device according to claim 102, wherein the first switching element and the plurality of second switching elements are combined to provide a logic conversion of the second input signal at the common node. (New) The memory device according to claim 102, wherein the first switching element and the plurality of second switching elements constitute a BiCMOS inverter. (Newly formed) 102. The method of claim 102, wherein the first switching element comprises an NMOS transistor and the second switching element comprises a CMOS conversion circuit and a pull-up connected bipolar transistor, while the CMOS conversion circuit is a gate of the NMOS transistor. And an input coupled to receive the second input signal, the output coupled to the pull-up connected bipolar transistor, wherein the bipolar transistor and the NMOS transistor cross a voltage potential corresponding to an operating potential of the memory. And a common connection of the NMOS transistor and the bipolar transistor connected in series, and acting as a pull-down transistor to provide an output to the common node operating as another common input terminal of the plurality of logic gates. (Newly established) a plurality of memory cells for storing data, an input buffer providing an address signal in response to an input address, a decoder coupled to the input buffer to decode the address signal and selecting the memory cell in response to the address signal A sense amplifier coupled to receive data from the selected memory cell, and an output buffer coupled to the sense amplifier to provide an output data signal; The decoder may include: a first input terminal configured to receive a first input signal, each of a plurality of logic gates coupled to a common node, a first switching element coupled to the common node, and a second switching coupled to the common node An element, and a third switching element coupled to the common node; The first switching device includes an NMOS transistor, the second switching device includes a PMOS transistor, and the gates of the NMOS transistor and the PMOS transistor receive a second input signal common to the plurality of logic gates. Coupled to a second input terminal, the source-drain paths of the NMOS transistor and the PMOS transistor coupled to the common node; The third switching device is connected to the common node through the source-drain path of the NMOS transistor of the first switching device, and the third switching device is coupled to a third input terminal for receiving a third input signal. And the first to third input signals correspond to input addresses through which the second and third signals function as control signals.