WO1996027883A1

WO1996027883A1 - Dynamic ram

Info

Publication number: WO1996027883A1
Application number: PCT/JP1995/000343
Authority: WO
Inventors: Binhaku Taruishi; Kanji Oishi
Original assignee: Hitachi, Ltd.; Hitachi Device Engineering Co., Ltd.
Priority date: 1995-03-03
Filing date: 1995-03-03
Publication date: 1996-09-12
Also published as: JP3466200B2

Abstract

A block write function is added to a synchronous dynamic RAM, and a unit decoder circuit is used for its column decoder. This unit decoder circuit includes a plurality of CMOS inverter circuits for receiving a plurality of first pre-decode signals and forming column select signals, and a CMOS circuit for receiving one of a plurality of second pre-decode signals and supplying its output signals to the common source of N-channel MOSFETs in the CMOS inverter circuits described above. The second pre-decode signal is generated by using lower order address signals. Therefore, only a P-channel MOSFET and an N-channel MOSFET are connected to the address line which is simultaneously changed at the time of block write, and power consumption can be reduced. Since one decoder of each unit forms the select signal, the current flowing through the CMOS inverter circuits can be dispersed to the MOSFETs receiving the second pre-decode signal. Therefore, it is not necessary to enlarge the size of such MOSFETs for the block write operation, and high integration becomes possible.

Description

Description Dynamic RAM Technical Field

The present invention relates to a semiconductor memory device having a block write function of simultaneously selecting a plurality of data lines of a memory array in which memory cells are arranged in a matrix and writing the same data, and particularly to a high speed block write operation. This is related to a dynamic RAM that achieves high power consumption and low power consumption. Background art

The synchronous DRAM is described in, for example, “521 6800: HM 54 16800 Series Data Book” issued by Hitachi, Ltd. on January 18, 1999, for example. Synchronous DRAM has two memory banks. Since the two memory banks are not selected at the same time, a common column address decoder is used to simplify the circuit.

Prior to the present invention, a column decoder as shown in FIG. 12 was developed. This column decoder has a function of selecting 256 pairs of complementary data lines. In order to select 256 pairs of addresses, 8-bit column address signals such as CA0 to CA7 are used. Among these 8-bit address signals, the lower three bits of address signals CA0 to CA2, the middle three bits of address signals CA3 to CA5, and the upper two bits of address signals CA6 and CA7. AY 00 corresponding to bank 0 (Bank O) as shown in the figure Eight predecode signals (lower order) of AY01K to AY71K corresponding to K to 7 OK and bank 1 (Bank 1) are formed and used in common for both banks. Eight predecode signals (middle) consisting of 37 37 are formed, and four predecode signals (higher) consisting of {60} to 63Κ are formed.

The lower predecode signals AYO 0K to 7OK corresponding to bank 0 are supplied to the input terminals of a CMOS inverter circuit composed of a P-channel MOSFET Q1 and an N-channel MOSFET Q2, which are shown as a representative example. The output signal is supplied to the output unit as a column selection signal YS00K through an inverter circuit acting as an output buffer. The other predecode signals AY10K to 7OK are also input to a similar CMOS inverter circuit. The sources of these eight CMOS inverter circuits and the N-channel MOSFETs of the same eight CMOS inverter circuits corresponding to the predecode signals A Y01 K to 7 IK corresponding to bank 1 are connected in common. Is done. This common node n 1 has P-channel MOSFETs Q3, Q4 and N-channel MOS, which are supplied with one of the middle predecode signals AY30K and one of the high predecode signals AY60K, respectively. The output terminal of the NAND gate circuit consisting of FETQ5 and Q6 is connected. In other words, the P-channel MOSFETs Q3 and Q4 are connected in parallel to the power supply voltage VCC, and the N-channel MOSFETs Q5 and Q6 are connected in series to the ground potential side of the circuit, and the P-channel MOSFETs Q3 and Q4 are shared. And the drain of the N-channel type MOSFET Q5 are connected to the common connection node n1. As a result, when both the middle and upper predecode signals AY30 and AY60 are at the high selection level, the output of the NAND gate circuit becomes the high level, and the 8X2 CMO Since the N-channel MOS FET constituting the S-inverter circuit sets the common source potential (node n1) to low level, the operation of these CMOS inverter circuits becomes effective, and A selection signal is formed corresponding to a selected one of the input signals AY 001-701 ^ or 801 K-71 ^. In this configuration, the unit decoder can use the middle and upper predecode signals in common, so that the circuit can be simplified.

By the way, in the block write operation, the lower address signals CA0 to CA2 are invalidated, in other words, the eight predecode signals AYO0K to 7OK or AY01K to 71 formed by the lower predecoder. This is done by forcing Κ to the selected level. That is, as shown in FIG. 13, eight complementary data lines specified by the higher-order predecode signal {60} and the middle-level predecode signal {30} are simultaneously selected.

In the first place, since the synchronous DRAM function does not have a block write function, no particular problem occurs in the above-described decoded circuit. However, the inventor of the present application has been able to read or write a large amount of data at high speed in a synchronous manner with a clock signal supplied from an external terminal, such as in a burst read mode, etc. Considering that it has a bank and can be accessed alternately, we considered adding a function as an image memory. In other words, by adding a function as an image memory to a synchronous DRAM as a general-purpose memory, cost reductions can be expected due to the further mass production of synchronous DRAMs accompanying the expansion of applications. In other words, conventionally, a two-port memory having a random access part and a serial access part is used as an image memory. Such a two-port memory is, for example, an image memory. There are only special applications like this, so the division height is increased.

In such an image memory, it is convenient to provide a block write function that is effective for clearing the screen or changing the background of a figure. In other words, by providing a synchronous DRAM with a block write function and a color register that has a mask function, the usability as an image memory can be further improved.

It has been found that the following problems occur when the block write function is provided as described above. The current consumed by the column decoder is determined by the charge / discharge cycle of the capacity and gate capacity of each address and the applied voltage. In the above block write, eight predecode signals AY00K to AY70K or AY01K to AY71K need to be selected at the same time and switched to Z non-selection. Such predecode signals AYO0K to AY7OK or AY01K Since {7} is shared with the input terminals of the CMOS inverter circuit of as many as eight unit decoders including the remaining seven unit decoders that form the non-selection signal, the gate capacitance is greatly consumed. The flow will increase. Also, as described above, the eight CMOS inverter circuits are simultaneously in the operating state, and the current is turned on by the high level of the middle and upper predecode signals AY30K and AY60K. In order to achieve high-speed operation, the conductance of MOSFETs Q 5 and Q 6 must be made large assuming the above-mentioned block light, in other words, It is necessary to increase its size, which requires a large occupied area.

Therefore, the present invention provides a block write function of simultaneously selecting a plurality of column switches and supplying the same write signal to a plurality of complementary data lines, while reducing the current consumption of the column address decoder and improving the efficiency. With the aim of providing a dynamic RAM that achieves integration I have.

Also, the present invention provides a synchronous dynamic RAM, which is a general-purpose memory, with a function suitable for image processing, and enables the use of a synchronous DRAM, which is a general-purpose memory, as an image memory. The purpose is to reduce it. Disclosure of the invention

A plurality of CMOS inverter circuits each receiving a plurality of first predecode signals to form a column selection signal, and receiving one predecode signal of a plurality of second predecode signals And a CMOS circuit that supplies the output signal to a common source of the N-channel MOSFET in the plurality of CMOS inverter circuits. By using this address signal, only two P-channel MOS FETs and N-channel M0 SFETs are touched to the address lines that change simultaneously during block writing. Become mosquito. Further, since one decoder forms a selection signal in each unit, the current flowing through the CMOS inverter circuit can be distributed to the MOS FET receiving the second predecode signal, and thus the size of the MOS FET can be reduced. It is not necessary to increase the size for the block light operation, and high integration is possible. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing an embodiment of a preferred dynamic RAM according to the present invention, FIG. 2 is a diagram showing a chip layout of a main part thereof, and FIG. It takes the above dynamic RAM FIG. 4 is a diagram showing a circuit of an embodiment of a preferred unit decoder. FIG. 4 is a diagram for explaining a column address selecting operation at the time of block write of a dynamic RAM according to the present invention. FIG. 5 is a diagram showing a circuit of an embodiment of a preferred lower address predecoder of the dynamic RAM, and FIG. 6 is a circuit of an embodiment of a preferred middle address predecoder of the dynamic RAM. FIG. 7 is a diagram showing a circuit of a preferred embodiment of the upper address pre-decoder of the dynamic RAM, and FIG. 8 is a diagram of a dynamic RAM according to the present invention. FIG. 9 is a diagram showing a circuit of a preferred write system, FIG. 9 is a diagram for explaining the timing of a damaging operation of the dynamic RAM according to the present invention, and FIG. Decor FIG. 11 is a diagram for explaining the timing of the operation of FIG. 11, and FIG. 11 is a diagram for explaining a block of an embodiment of a data processing device using a dynamic RAM according to the present invention. FIG. 12 is a diagram for explaining a circuit of a unit decoder developed prior to the present invention, and FIG. 13 is a diagram for explaining a selecting operation at the time of block writing. BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a preferred synchronous D RAM (hereinafter simply referred to as SDRAM) according to the present invention. The SDRAM shown in the figure is formed on one semiconductor substrate such as a single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The SDRAM of this embodiment includes a memory mat that constitutes memory banks 0 and 1. Each memory mat has a matrix The select terminals of a plurality of memory cells arranged correspondingly are connected to a diode provided with a dynamic memory cell and arranged so as to extend in the vertical direction in FIG. The data input / output terminals of a plurality of memory cells arranged correspondingly are connected to the complementary data line arranged to extend in the horizontal direction.

One of the plurality of memory mats is driven to a selected level in accordance with a result of decoding a row address signal by a row decoder. The plurality of complementary data Di of the memory mats are coupled to a sense amplifier and a column selection circuit. The sense amplifier is a amplification circuit that detects and amplifies a minute difference appearing on each complementary data line by reading data from a memory cell. The column switch circuit in this case is for selecting complementary data lines individually and connecting them to the complementary common data line IZO bus, and it should be understood that the column switch circuit is included in the I / O bus in FIG.

The common 10 corresponding to the above IZO bus is connected to the output terminal of the write buffer WB as a write circuit and the input terminal of the main amplifier MA as a read circuit. The write buffer WB is enabled during a write operation, and transmits a damage signal to the common IZO. At the time of block write operation, it is necessary to turn on a plurality of column switch circuits for the common I / O and to transmit write signals to a plurality of complementary data lines. For this reason, the write buffer WB has a relatively large driving current output capability so that the above-described large load can be driven at high speed.

The mask register is used to perform a masking operation by specifying an arbitrary bit of the write data to be written in units of a plurality of bits, invalidating the write signal, and retaining the original data. This mask register is also enabled during a block write operation, and , Except for the bits masked by the mask register, each of which is written to a plurality of memory cells via a plurality of complementary data lines.

The output signal of the main amplifier MA is connected to the input terminal of the output buffer, and the input terminal of the write buffer is connected to the output terminal of the input buffer. The output terminal of the output buffer and the input terminal of the input buffer are connected to a common input / output terminal 1-0. Although not particularly limited, the input / output terminal IZ0 is composed of 16 input / output terminals in units of 16 bits of data D0 to D15.

The write data is transmitted to the write buffer WB through the input buffer, and is also supplied to a color register according to an operation mode. The color register stores color pixel data preset through the input buffer. Then, by selecting a color register according to input data in a specific write mode, a write operation is performed by transmitting storage information written in the color register to the harm buffer. With this configuration, color pixel change correction can be easily performed by combining data and a color register.

The address signals (A 0 to A 11) are fetched in an address multiplex format by a row address buffer and a column address buffer. Of the address signals supplied in the multipletus format, the row address signal is held by the address latch circuit. In the refresh operation mode, the row address buffer has a function of taking in a refresh address signal output from a refresh counter (not shown) as a row address signal.

The address signal taken into the column address buffer is supplied as preset data of the column address counter and is held here. The column address counter sends a column address signal as the preset data or a value obtained by sequentially incrementing the power address signal to the power decoder in accordance with an operation mode specified by a command described later. Output. The column address counter also generates a bank select signal according to the column address of the most significant bit.

Although the bank control circuit and the timing control circuit are not particularly limited, the clock signal CLK, the clock enable signal CKE, and the chip select signal CS (symbols indicate that the signal attached thereto is a low enable signal. The same), external control signals such as the column address strobe signal ZCAS, the row address strobe signal ZRAS, and the write enable signal WE, and control data passed through the above address buffer, and the level change and timing of those signals It forms an internal timing signal for controlling the operation mode of the SDRAM and the operation of the above-described circuit block based on the above-mentioned conditions. The control circuit includes a control logic and a mode register (not shown) for this purpose. In addition, signals DSF and DQM are newly added to provide a function as an image memory. In this embodiment, such control terminals are provided in order to match the interface with the conventional image memory, in other words, to facilitate replacement of the conventional two-port memory.

The clock signal CLK is input using a system clock of an external microprocessor or the like. The chip select signal ZCS instructs the start of a command input cycle by its mouth level. When the chip select signal / CS is high (chip is not selected) and other inputs have no meaning. However, internal operations such as the memory bank selection state and burst operation described later are not affected by the change to the chip non-selection state. The / RAS, / CAS, and ZWE signals are the corresponding signals in a normal DRAM. The function is different from that of the command cycle, and is used as a significant signal when defining a command cycle described later.

The clock enable signal CKE is a signal indicating the validity of the clock signal CLK. When the signal CKE is at a high level, the rising edge of the clock signal CLK is valid, and when it is at a low level, it is invalid. Further, although not shown, in the read mode, an external control signal for controlling the output enable of the output buffer is also supplied to the controller. When the signal is at a high level, for example, the output buffer is set to a high output impedance state.

The row address signal is defined by the levels of A0 to A10 in a later-described row address strobe / bank active command cycle synchronized with the rising edge of the clock signal CLK. The input from A11 is regarded as a bank selection signal in the above described row strobe / bank active command cycle. 'In other words, memory bank 0 is selected when the input of A11 is at the low level, and memory bank 1 is selected when the input is at the high level. The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the non-selected memory bank are deselected, and the input buffer and the output buffer of only the selected memory bank are controlled. It can be performed by processing such as connection.

The input of A 10 in the precharge command cycle described later indicates the precharge operation mode for the complementary data line, and the high level indicates that the precharge target is both memory banks. The low level indicates that one of the memory banks indicated by A11 is to be precharged.

The column address signal is the rising edge of the clock signal CLK. Read or write command (column address, read command, column address, write command, which will be described later), which is defined by the levels of A0 to A7 in the cycle. The dynamic address defined in this way is used as a start address for burst access.

Next, the main operation modes of the SDRAM specified by the command are explained.

(1) Mode register evening set command (Mo)

This command is used to set the above mode register. The command is specified by the level of CS, ZRAS, / CAS, and ZWE, and the data to be set (register set data) is given via A0 to A9. . The register set data is not particularly limited, but includes burst length, CAS latency, and write mode. Although not particularly limited, the burst length that can be set is 1, 2, 4, 8, full-page (256), the CAS latency that can be set is 1, 2, 3, and the write mode that can be set. Are referred to as burst write and single write.

The above CAS latency indicates how many cycles of the clock signal CLK are spent from the fall of ZCAS to the output operation of the output buffer in the read operation indicated by the column address read command described later. is there. Until the read data is determined, an internal operation time for data read is required, and this is set in accordance with the operating frequency of the internal clock signal. In other words, when using an internal clock signal with a high frequency, set the CAS latency to a relatively large value, and when using an internal clock signal, set the CAS latency to a relatively small value. Set to a value.

(2) Row address strobe 'bank active command (Ac) This is a command to enable the instruction of the row address strobe and the selection of the memory bank by A11, and is instructed by ZCS, ZRAS = high level, / CAS, ZWE = high level. The supplied address is fetched as a row address signal, and the signal supplied to Al 1 is fetched as a memory bank selection signal. The fetch operation is performed in synchronization with the rising edge of the internal clock signal as described above. For example, when the command is specified, a memory cell in the specified memory bank is selected, and the memory cells connected to the memory cell are connected to the corresponding complementary data lines.

(3) Column address · Read command (Re)

This command is a command necessary for starting the burst read operation, and is a command for giving an instruction of the column address strobe, and is instructed by ZCS, CAS = low level, NO RAS, ZWE = high level. When the column address signal supplied to AO to A7 is taken in as a column address signal. Thus, the captured signal is supplied as a burst start address to the column address signal. In the burst read operation instructed by this, a memory bank and a lead line in the memory bank are selected by a loadless strobe and a functional command cycle before the burst read operation. The memory cells of the selected word line are sequentially selected according to the address signal output from the column address counter in synchronization with the internal clock signal, and are continuously read. The number of data read continuously is the number specified by the burst length. Data reading from the output buffer is started after waiting for the number of cycles of the internal clock signal specified by the CAS latency.

(4) Column address write command (W r) When burst write is set in the mode register as the mode of write operation, it is a command necessary to start the burst write operation, and when single write is set in the mode register as the mode of write operation, This command is required to start the single write operation. Further, the command gives an instruction of a column address strobe in single write and burst write. This command is specified by ZCS, / CAS, ZWE = low level and ZRAS-high level. At this time, the address supplied to A0 to A7 is captured as a column address signal. The captured column address signal is supplied to the column address counter as a burst start address in burst write. The procedure of the burst write operation instructed thereby is performed in the same manner as the burst read operation. However, the write operation has no CAS latency, and the capture of write data is started from the column address write command cycle.

(5) Precharge command (Pr)

This is a command to start the recharge operation for the memory bank selected by A10, A11, and is instructed by / CS, ZRAS, ZWE = high level and ZCAS = high level.

(6) Auto refresh command

This command is required to initiate autorefresh and is indicated by ZCS, / RAS, / AS = t3 high and ZWE, CKE = high.

(7) Burst stop 'in full page command

This command is necessary to stop the burst operation for the full page for all memory banks, and is ignored for burst operations other than full page. This command is called ZCS. ZWE = Mouth level, ZRA Indicated by S, ZCAS = high level.

(8) No operation command (Nop)

This is a command that indicates that no substantial operation is performed, and is indicated by ZCS = low level and ZRAS, / CAS, and ZWE high levels.

In the case of SDRAM, when one memory bank is performing a burst operation, another memory bank is designated in the middle of the operation, and if a row address strobe. The operation of the row address system in the other memory bank is enabled without affecting the operation in the other memory bank. For example, an SDRAM has means for internally holding data, addresses, and control signals supplied from the outside, and the held contents, particularly addresses and control signals, are not particularly limited, but are held for each memory bank. It has become. Alternatively, the data of one word Di in the memory block selected by the row address strobe 'bank active command cycle may be latched in advance to a latch circuit (not shown) for a read operation before the memory system operation. It has become.

Therefore, as long as data does not collide at the data input / output terminal I0, during execution of a command whose processing has not been completed, a precharge command or a row address for a memory bank different from the memory bank to be processed by the command being executed is not executed. It is possible to start the internal operation in advance by issuing a strobe active command.

Since the SDRAM of this embodiment can input and output data, addresses, and control signals in synchronization with the clock signal CLK, it is possible to operate a large-capacity memory similar to DRAM at a high speed comparable to that of SRAM. The number of data to be accessed for one selected line is It will be understood that by specifying the length, a plurality of data can be read or written continuously by sequentially switching the selection state of the column system in the internal column address count.

In addition to such a high-speed serial access function, the color register and mask register used in the conventional image memory are provided, and the block write function is added, so that the image processing capability can be further improved. .

The block write mode provided in the SRAM of this embodiment includes two special mode register set cycles for setting color data in the color register and mask data in the mask register, respectively, and the write target. A row active command cycle for designating the row address of the memory cell and starting the selection operation of the lead line is premised on the assumption that the column address of the memory cell to be damaged is specified and a substantial block * Block write is performed by the write command cycle for executing the write operation.

Although not particularly limited, the row address strobe signal ZRAS is set to the high level at the rising edge of the clock signal CLK, and the chip select signal ZCS, the column address strobe signal ZCAS, and the write enable signal ZWE are set to the low level. A write command cycle is performed, and the block write mode is designated by setting the special function signal DSF to a high level at the rising edge of the clock signal CLK. Prior to the rise of the clock signal CLK, the Y address signals AY3 to AY7 excluding the lower three bits are supplied to the address input terminals AO to A7 in a combination that specifies the first block of the complementary data line.

Signal D QM is a control that controls the input and output buffers. Signal. This signal is publicly known in the SDRAM, and is not directly related to the present invention.

FIG. 2 is a chip layout diagram of a main part of the SDRAM according to the present invention. With the column decoders (Column-Decoder 0 and Column-Decoder 1) as the center, the left side of the figure is described as the upper part. The memory array of memory bank 0 is arranged on the left side, and the memory array of memory bank 1 is on the right side. Be placed. The memory array is divided into upper and lower parts, with the upper half (Upper) by column decoder 0 (Column-Decoder 0) and the lower half (Lower) by columns by coder 1 (Column-D ecoder 1). A column selection operation is performed.

Column decoders 0 and 1 are lower address predecoders for decoding column address signals CA0 to CA2, middle address predecoders corresponding to banks 0 and 1 for decoding column address signals CA3 to CA5, and columns. Receiving each decode signal from the upper address pre-decoder that decodes the address signals CA 6 and CA 7, it forms a pair of column select signals YS corresponding to bank 0 or bank 1, respectively. The middle address predecoder is supplied with YSE 0 and YSE 1 signals for pulse control, and is provided with two systems because of bank control. The decode signals of these predecoders are separated by a driver and supplied to upper and lower column decoders 0 and 1.

The memory array configuration will be described with reference to Nok 0 as an example. A unit memory array is composed of 1,024 (1K) word lines and 246 pairs of complementary data lines. Sixteen such memory arrays are provided from 0-0 to 0-15. Since a memory array having the same configuration is provided on the left side, the storage capacity of bank 0 is set to about 256Kx16X2 = 8M (bits). The complementary data lines of the two memory arrays are selectively connected to the sense amplifier SA and the 10 line (column switch). In other words, the shield sense amplifier system is used. In this embodiment, the memory cells are divided into odd columns and even columns, and are alternately connected to two sense amplifiers provided with a memory array interposed therebetween. As a result, on the left side, 16 memory arrays 0—0 to 0—15 are effectively divided into two memory mats, and 8 memory arrays are selected from 16 memory arrays. Memory access is performed in bit units. Similarly, memory access is performed on the right side in 8-bit units. As a result, memory access is performed on the 0 and 0 links (banks) in 16-bit units as a whole.

In the block write as described above, the output of the lower address predecoder is invalidated, and eight memory cells are selected at the same time. Therefore, the total S × 16 = 128 bits in units of 128 bits Injection is possible. FIG. 3 is a diagram showing a circuit of one embodiment of the unit decoder. In the column decoders 0 and 1 shown in FIG. 2, 32 such unit decoders are provided. In other words, one unit decoder forms eight types of column selection signals, so that a total of 256 column selection signals are formed.

The same circuit as the circuit shown in FIG. 12 is used for the unit decoder of this embodiment. Therefore, among the MOSFETs that constitute the circuit, the same circuit symbols are given as representatively shown MOS FETQ 1 to Q 6. However, the circuit operation itself of each MOSFET is different from that of the predecoder supplied to the gate, which is an important point of the present invention.

In other words, the P-channel MOSFET Q1 and the N-channel MOSFET Q1, which have the CMOS inverter configuration shown The gate of Q2 is supplied with AY 300K, one of the middle address predecode signals corresponding to bank 0, instead of the lower address predecode signal as in the conventional case. The middle address predecode signals AY310K to AY370K corresponding to bank 0 are supplied to the inputs of the remaining seven CMOS inverter circuits, respectively. Similarly, the inputs of the eight CMOS inverter circuits corresponding to bank 1 are supplied with eight intermediate address predecode signals AY30 1K to AY37 1K corresponding to bank 1, respectively. You. .

The sources of the N-channel MOSFETs constituting the 16 CMOS inverter circuits in total are connected to the common node n1. The output terminal of the CMOS gate circuit is connected to the common node n1. In other words, parallel P-channel MOSFETs Q3 and Q4 are provided between the common node n1 and the power supply voltage terminal VCC. Between the common node n1 and the ground potential of the circuit, N-channel type MOSFETs Q5 and Q6 in series are provided. The gates of the MOSFETs Q3 and Q5 are connected in common, and one of the eight decoded signals AYOK-7K formed by the lower address predecode circuit is supplied with a decoded signal AY0K. You. The gates of the MOSFETs Q4 and Q6 are connected in common, and one of the four high-order predecode signals AY60K-63K is supplied with a decode signal AY60K.

The unit decoder consists of the eight lower predecoder signals AY 0 K to 7 K formed by the lower predecoder as shown in FIG. 4 and the four upper predecoders formed by the upper predecoder. 32 decoding signals AY6OK-63K are provided so as to correspond to 32 combinations.

During normal operation, the lower, middle and upper predecoders Since one decode signal is formed, one column select signal YS corresponding to bank 0 or bank 1 is formed. Then, during the block write operation, the lower predecode signals AY0K-7K are both set to the high level. Therefore, as shown in FIG. 4, one column select signal YS 0 to YS 7 is simultaneously selected from each unit decoder corresponding to the select signal Y 0 K to Y 7 の of the lower predecode circuit. You.

The current consumed by the column decoder is determined by the wiring capacity of each address, the gate capacity of the MOSFET to which it is connected, the charge / discharge cycle and the applied voltage as described above. In the configuration in which the predecoded signal is supplied to the gates of the MOSFETs TQ3 and Q5 provided at the common node in the unit decoding circuit, only 16 MOSFETs are required as a whole, so that it can be reduced to 1Z8 compared to the conventional case. In addition, the common node n1 only flows through the selected pre-decoded signal AY 300K-370K, which flows through one of the CMOS inverter circuits. The size of the common MOSFETs Q5, Q6 has to be made particularly large for block lights. Conversely, if the MOSFET size is the same, high-speed operation can be achieved.

FIG. 5 shows a circuit diagram of an embodiment of the preferred U of the lower order bridge decoder. Eight combinations of signals are supplied to the NAND gate circuit by the column address signals CA0 to CA2 and the inverted signal formed by the inverter circuit, and the output signal of the NAND gate circuit is passed through the inverter circuit to AYO0. 8 kinds of decoded signals from AY07 to AY07 are formed.

The signal AY00 and the redundant signal YRB, which are exemplarily shown as representatives of the eight types, are supplied to a NAND gate circuit, and a column of a normal path is provided. It is output as a selection signal. In other words, in the normal path, the signal AY00 is inverted and output as an inverted selection signal Y 0 DB through an NAND gate circuit and an inverter circuit on the condition that there is no defect repair. It is output as the lower column select signal Y 0 D through two inverter circuits as drivers.

On the other hand, the block write (BW) pass uses the block write enable signal BWDD and the mask data input from the data terminals D0 to D16 at the time of block write to the NAND gate circuit and the inverter circuit. Through the NAND gate circuit on condition that there is no redundant signal YRD 00 B, YRD 10 B for block write. Such a BW path is similarly supplied to the other seven predecoder circuits, so that the predecode signals AY00 to AY07 formed by the address signals CA0 to CA2 are substantially invalidated, and The column predecode signals Y0D to Y7D on the side and the column predecode signals YOU and Y7U on the lower side are simultaneously set to the selected level.

FIG. 6 is a circuit diagram of a preferred embodiment of the medium-level Bridecoda and an embodiment of the present invention. Eight combinations of signals are supplied to the NAND gate circuit by the column address signals CA3 to CA5 and the inverted signal formed by the inverter circuit, and the output signal of the NAND gate circuit is output by the signal YSE0. Through the activated clocked inverter circuit, the signal is taken into the through latch circuit, and the selection signal AY30B is formed by the NAND gate circuit and the inverter circuit in synchronization with the above-mentioned signal YES 0 corresponding to the bank 0. Then, the upper and lower predecode signals AY 3011 and 8030D are output through an inverter circuit as a driver. It is provided corresponding to the same circuit power bank 1.

FIG. 7 shows a circuit diagram of a preferred embodiment of the upper predecoder. ing. Four combinations of signals are supplied to the NAND gate circuit by the column address signals CA6 and CA7 and the inverted signal formed by the inverter circuit, and the output signal of the NAND gate circuit is passed through the inverter circuit. Output, the inverter circuit at the end of ft acts as a driver, forming the upper and lower predecode signals AY60U and AY60D.

FIG. 8 is a circuit diagram of a preferred write system of the dynamic RAM according to the present invention. Each of the complementary data lines DL0T, DL0B, DL7T, DL7B illustratively shown in the memory array is coupled to a sense amplifier (Sense Amp). In the figure, the switch MOSFET of the shared sense amplifier type as described above is omitted. The MOSFETs M1, M2 and Ml5, Ml6 shown as examples are column switches, and the gates thereof are supplied with column select signals YS0, YS7. A word line WL is arranged orthogonally to the complementary data Di DLOT, DL0B, DL7T, DL7B, and an address selection MOSFET and a storage capacitor are provided at the intersection of the complementary data line and the lead line. Such a dynamic memory cell is provided.

The column switch MOSFETs M1 and M2 and Ml5 and Ml6 are connected to the input / output lines MIOT and OB in the mat. The I / O lines MIOT and MIOB in MAT are provided with a half precharge circuit consisting of MOSFETs N2 and N3 that supply the precharge voltage of the short-circuit MOSFET Nl and VccZ2. The input / output lines MI〇T and MI〇Β in the mat are N-channel MOSFETs N4 and N5, which are switch-controlled by the mat select signal MS0, and the mat select signal MS0 is inverted by the inverter circuit. Input from outside the MAT through a CMOS switch consisting of P-channel type MOS FETs P1 and P2 Connected to output lines CI OB and CI OT.

The input / output Di CIOB and CIOT outside the mat are connected to the input terminals of a main amplifier (Main Amp) used in a read operation. In addition, for the write operation, Ν-channel MOSFETs N 11 and Ν 12 are provided between the input / output Di CI OB and CI〇T outside the MAT and the ground potential of the circuit. P-channel MOSFETs P5 and P6 are provided between cc and cc. A short-circuit MOSFET P7 is provided between both input and output Di C IOB and C IOT.

The write buffer decodes the write signal (pulse), the mask signal MK, the input data DI and the read signal (pulse) by a NAND gate circuit to form the signals A to E, and the write MOSFET and the write MOSFET. Control the amplifier.

FIG. 9 is a timing chart for explaining the δ writing operation, in which the mat select signal MSη and the lead line WL are selected by row-related address selection. When the damage signal DI is at a high level, the column selection signals YS and A to C go to a high level in synchronization with the high level of the write pulse W 、, D and E are fixed at a low level, and the input / output lines CI OB goes low, I / O di CIOT goes high. One of the I / O lines MIOTZB in the mat corresponds to the low level correspondingly, and the complementary data line DLOTZB in the memory array is switched according to the write data.

FIG. 10 is a timing chart for explaining the operation of the unit decoder.

The lower predecode signals Y0K to 7K and the higher predecode signals AY60K to 63K have one period relatively long such as 10 η (nanosecond), but are now compatible with unit decoders. Medium predecode signal 信号 30 i K to AY 37 i K (i is bank 0 or 1), the pulse width is shortened to 5 n corresponding to YSE for pulse control. In other words, the intermediate predecode signals 30 iK to AY37 iK need to be switched at twice the frequency of other bridging signals. In this embodiment, since the lower-order predecode signal simultaneously selected at the time of block write may be a pulse having a relatively long cycle as described above, the load on the driver for driving it can be reduced.

FIG. 11 shows a functional block diagram of an embodiment in which the dynamic RAM according to the present invention is applied to a computer system. Bus and central processing unit CPU, peripheral device controller, DRAM (dynamic memory) as main memory and its controller, SRAM (static memory) as knock-up memory, backup parity and controller The computer system is composed of a ROM (read 'only' memory) in which programs are stored, and a display system.

The peripheral device control unit is connected to an external storage device, a keyboard KB, and the like. The display system is constituted by a VRAM or the like using an SDRAM as in the above-described embodiment, and displays stored information by being connected to a display as an output device. Also, a power supply unit for supplying power to the internal circuit of the computer system is provided. The central processing unit CPU controls the operation timing of each memory by forming a signal for controlling each memory.

The SDRAM according to the present invention can also be used for a main memory. Even when used for main memory, the block write function is useful when writing the same data at high speed, such as when clearing the memory contents.

The dynamic RAM according to the present invention includes the above-described synchronous RAM. You are not required to be DRAM. In other words, in the dynamic RAM in which the operation timing of the internal circuit is controlled in synchronization with the row address strobe signal / RAS and the column address strobe signal CAS and the write enable signal ZWE, the unit decoder shown in FIG. This is because, when the above-described block write function is realized by using, the same effect as in the above-described embodiment can be obtained.

The predecoder may be divided into two parts, upper and lower. When divided into two in this way, the upper predecoder corresponds to the middle predecoder. That is, a predecoder that forms a predecode signal that is all set to the selective state during the block write operation may be supplied to the common CM 0 S circuit of the unit decoder as described above. .

In the above description, the dynamic RAM (Randam Access Memory) has been described in detail, but the present invention is not limited to this. For example, SRAM (Static Randam Access Memory), EPR OMCEras-abel Programmable Read The present invention can be similarly applied to semiconductor memory devices such as Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), and FRAM (Ferroelectrically Random Access Memory).

Industrial applicability

As described above, the dynamic RAM according to the present invention is useful as an image memory, a main memory, or an extended memory in a computer system, and is particularly effective when a synchronous DRAM can be used as an image memory. Suitable for those who have block lights.

Claims

The scope of the claims

1. A memory array in which memory cells are arranged in a matrix at intersections of a plurality of code lines and a plurality of complementary data lines;

A power switch circuit for receiving the column selection signal and connecting the complementary data line to the input / output line;

A first predecoder that decodes a plurality of bit address signals excluding lower bits of the column address signal to form a plurality of first predecode signals;

A second predecoder for decoding a lower bit address signal of the column address signal to form a plurality of second predecode signals; and a plurality of first predecode signals each of which receives the plurality of first predecode signals. Receiving a predecode signal of a plurality of second predecode signals, and outputting an output signal of the plurality of CMOs to form a column selection signal. Supply to the common source of N-channel type MO SFET in S inverter circuit C

A unit decoder including a MOS circuit;

A write operation for forcibly setting the second predecode signal formed by the second predecoder to a selected level and transmitting the same write signal to a plurality of complementary data lines by setting a predetermined operation mode Dynamic RA characterized by comprising a evening control circuit for performing

M.

2. The unit decoder constitutes a column decoder by a plurality, and memory banks 0 and 1 in which a memory array is arranged symmetrically around the column decoder and each is selectively accessed. And the first predecoder corresponds to the memory banks 0 and 1, A CMOS circuit to which a second predecode signal formed by the second predecoder is supplied is used in common for the unit decoders corresponding to the memory banks 0 and 1. The dynamic RAM according to claim 1, wherein:

3. The setting of the write operation for transmitting the same write signal to the plurality of complementary data di is performed by a control signal supplied from a special function terminal provided for the operation. The dynamic RAM according to claim 1, wherein the dynamic RAM is characterized in that:

4. As the write data, a write signal set in a built-in register is used, and data supplied from a data input / output terminal is used as mask information, and a write signal formed by the second predecoder is used. 2. The dynamic RAM according to claim 1, wherein the two predecoded signals are deselected according to the mask information.

5. The dynamic RAM according to claim 1, wherein the dynamic RAM is a synchronous dynamic RAM including input / output interface control performed in synchronization with a clock terminal input from an external terminal. Dynamic RAM as described.

6. (1) Multiple word lines,

(2) a plurality of complementary data lines including a first complementary data line, a second complementary data line, a third complementary data line, and a fourth complementary data line;

(3) a plurality of memory cells arranged at intersections of the plurality of ground lines and the plurality of complementary data lines;

(4) a common complementary data line;

(5) (a) a first column switch having a control terminal, and a current path joined between the common complementary data line and the first complementary data line;

(b) a control terminal, the common complementary data line and the second complementary data line; A second column switch having a flow path joined to the overnight line,

(c) a third column switch having a control terminal, and a current path joined between the common complementary data line and the third complementary data line;

(d) a fourth column switch having a control terminal, and a current path joined between the common complementary data line and the fourth complementary data line;

(6) a first predecoder that receives a plurality of first column address signals and outputs a plurality of first predecode signals;

(7) a first predecoder that receives a plurality of second column end signals and outputs a plurality of second predecode signals;

(8) (a) a gate that receives one of the plurality of first predecode signals, a source that is coupled to receive a first source voltage, and a control terminal that is coupled to the control terminal of the first power switch. A first P-channel MOSFET having a drain

(b) a first N-channel MOSFET having a gate coupled to the gate of the first P-channel MOSFET and a drain coupled to the drain of the first P-channel MOSFET;

(c) The gate receiving the other one of the plurality of first predecode signals, the source coupled to receive the first supply voltage, and the control terminal of the second column switch. A second P-channel MOSFET having a coupled drain; and

(d) a second N-channel MOSFET having a gate coupled to the gate of the second P-channel MOSFET and a drain coupled to the drain of the second P-channel MOSFET;

(e) the drain coupled to the source of the first N-channel MOSFET and the source of the second N-channel MOSFET and the

A gate for receiving one of the two predecode signals and a second power supply voltage A first decoder having a third N-channel MOSFET having a source coupled to

(9) (a) A gate receiving the one of the plurality of first predecode signals, a first source, a source coupled to receive a negative voltage, and a control terminal of the third column switch. With drain drained

P-channel MOSFET,

(b) a fourth N-channel MOSFET having a gate coupled to the gate of the third P-channel MOSFET and a drain coupled to the drain of the third P-channel MOSFET;

(c) a source coupled to receive the other of the plurality of first predecode signals, a source coupled to receive the first power supply voltage, and coupled to the control terminal of the fourth column switch. A fourth P-channel MOSFET having a drain and

(d) a fifth N-channel MOSFET having a gate coupled to the gate of the fourth P-channel MOSFET and a drain coupled to the drain of the fourth P-channel MOSFET;

(e) a drain coupled to the source of the fourth N-channel MOSFET and the source of the fifth N-channel MOSFET, a gate receiving another one of the second predecode signals, and the second power supply voltage. A second decoder having a sixth N-channel M〇SFET having a source coupled to receive the control signal, the second predecoder receiving a control signal, and receiving the control signal according to the control signal. A dynamic RAM characterized in that the second predecode signal is set to a logic high level.