KR100187721B1 - Esd protection circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge (ESD) protection circuit formed on an input / output pad of a high-speed semiconductor device such as a media RAM, In the conventional protection circuit, when a voltage according to the electrostatic discharge pulse is applied, the buffer transistor having a gate length smaller than the field transistor and the transistor in the terminator circuit operate as a parasitic element first due to a low snapback voltage, This is to solve the problem that the field transistor does not function properly as a protection element and defects due to electrostatic discharge stress easily occur because current is consumed.

That is, according to the present invention, a gate grounding transistor having a gate length smaller than that of a transistor in a terminator circuit is configured as a protection element instead of a conventional field transistor, so that the gate grounding transistor operates as a parasitic element before the transistor of the terminator circuit, And exhibits good characteristics for electrostatic discharge stress.

Description

Electrostatic Discharge (ESD) Protection Circuits in Semiconductor Devices

The present invention relates to an electrostatic discharge protection circuit of a semiconductor device, and more particularly to an electrostatic discharge protection circuit formed on an input / output pad of a high-speed semiconductor device such as a Media RAM.

In general, when an electrostatic discharge (ESD) pulse is applied to the inside of a semiconductor device from the outside, a high current flows into the device, causing a failure of the semiconductor device. Therefore, a protection circuit for preventing defects due to electrostatic discharge is required at the input or output end of the semiconductor device.

1 is a circuit diagram showing an embodiment of an electrostatic discharge protection circuit according to the prior art.

1, in the case of a high speed semiconductor device such as a media RAM, the electrostatic discharge protection circuit 10 includes a buffer NMOS transistor 13 in the form of a finger transistor, And a field transistor 14 (Field Tr.) Having a thick field oxide (Thick Field Oxide) are connected in parallel. In order to improve the speed, a terminator circuit 12 (including a NMOS transistor) is connected to the input / output pad 11. That is, the NMOS transistor, the buffer NMOS transistor 13 and the field transistor 14 in the terminator circuit 12 are connected to the input / output pad 11 through the resistors 15a and 15b, respectively, Is connected to the internal circuit of the semiconductor device.

When the electrostatic discharge pulse flows into the semiconductor device through the input / output pad 11, the field transistor 14 operates as a parasitic device and consumes the applied electrostatic discharge current to serve as a protective device , It actually does not work properly.

When a voltage corresponding to the electrostatic discharge pulse is applied, a breakdown phenomenon occurs at the drain of the buffer transistor 13 having a gate length smaller than that of the field transistor 14, and the buffer transistor 13 First, it operates as a parasitic element and consumes the electrostatic discharge current. When the field transistor 14, which is a protection element, reaches a voltage at which the field transistor 14 can operate, that is, a junction breakdown voltage, the field transistor 14 operates as a parasitic element so that most of the electrostatic discharge current The NMOS transistor elements in the terminator circuit 12 having a gate length smaller than that of the field transistor 14 operate as parasitic elements first due to a low snapback voltage, thereby consuming almost all of the electrostatic discharge current.

Therefore, the field transistor 14, which is an electrostatic discharge protection element, can not operate at all because of the breakdown voltage, failing to function as a protective circuit, and failures due to electrostatic discharge stress can be easily caused.

FIG. 2 is a graph showing a current distribution of each device in the electrostatic discharge protection circuit according to the prior art shown in FIG.

Referring to FIG. 2, it is a current distribution according to time of each device when an electrostatic discharge voltage of 800 V is applied. That is, it can be seen that the smallest current flows in the field transistor (?), Which has to serve as a protection element over time. That is, the current due to the electrostatic discharge can not be distributed to each device.

3 to 5 are diagrams showing temperature distributions of respective elements of the electrostatic discharge protection circuit according to the prior art shown in FIG.

3 to 5, a terminator circuit (FIG. 3), a buffer transistor (FIG. 4), and a drain terminal (FIG. 5) constituting a protection circuit when an electrostatic discharge voltage of 800 V is applied, . Referring to Fig. 3, a temperature distribution in the terminator circuit is shown in which the melting point of the gate poly exceeds 600K. In other words, it can be seen that an excessive electrostatic discharge current flows in the terminator circuit and defects easily occur. As shown in FIG. 5, the field transistor, which is a protection device, exhibits a temperature distribution of 300K, which means that almost no electrostatic discharge current is consumed.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a structure of an electrostatic discharge protection circuit formed on an input / output pad of a high-speed semiconductor device, in which a gate ground transistor having a gate length smaller than that of a transistor in a terminator circuit The circuit configuration is to provide an electrostatic discharge protection circuit that acts as a parasitic element prior to the transistor of the terminator circuit, plays a role as a protective element, and exhibits good characteristics against electrostatic discharge stress.

1 is a circuit diagram showing an embodiment of an electrostatic discharge protection circuit according to the prior art;

FIG. 2 is a graph showing a current distribution of each element of the electrostatic discharge protection circuit according to the prior art shown in FIG. 1; FIG.

FIGS. 3 to 5 are diagrams showing temperature distributions of respective elements of the electrostatic discharge protection circuit according to the prior art shown in FIG. 1;

6 is a circuit diagram showing an embodiment of an electrostatic discharge protection circuit according to the present invention.

FIG. 7 is a diagram showing a snapback voltage distribution of each element of the electrostatic discharge protection circuit according to the present invention shown in FIG. 6; FIG.

FIG. 8 is a graph showing the current distribution of each element of the electrostatic discharge protection circuit according to the present invention shown in FIG. 6; FIG.

Figs. 9 to 11 are diagrams showing temperature distributions of respective elements of the electrostatic discharge protection circuit according to the present invention shown in Fig. 6; Fig.

DESCRIPTION OF THE REFERENCE NUMERALS

10, 20: Electrostatic discharge protection circuit (ESD Protection Circuit)

11, 21: Input / Output Pad

12, 22: Terminator Circuit

13, 23: Buffer Tr.

14: Field transistor (Field Tr.)

24: Grounded Gate Tr.

15a, 15b, 25a, and 25b:

According to an aspect of the present invention, there is provided a semiconductor device comprising: an input / output pad; A terminator circuit including a transistor connected to the input / output pad through a resistor; A gate grounding transistor connected in parallel with the terminator circuit; And a buffer transistor which is connected in parallel with the terminator circuit and the gate grounding transistor and whose gate is connected to the internal circuit of the semiconductor element, characterized in that a gate length of the gate grounding transistor is smaller than that of the transistor in the terminator circuit A high-speed semiconductor device.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

6 is a circuit diagram showing an embodiment of an electrostatic discharge protection circuit according to the present invention.

6, the electrostatic discharge protection circuit 20 of the present embodiment has a gate length smaller than that of the NMOS transistor in the terminator circuit 22, instead of the field transistor operating as a protection element in the conventional electrostatic discharge protection circuit structure, For example, a gate ground NMOS transistor 24 having a gate length of 0.6 to 0.8 times is configured in parallel with the terminator circuit 22. [

That is, the gate ground NMOS transistor 24 is connected in parallel with the high-speed device terminator circuit 22 connected to the input / output pad 21. The gate-grounded NMOS transistor 24 has a smaller gate length than the NMOS transistor of the terminator circuit 22 and is not suitable as an electrostatic discharge protection element if the gate length of the transistor is long. This is because a high voltage is required to operate as a parasitic element, and a high electric field of the drain junction is required to withstand a snapback that generates a lot of heat in the junction.

When an electrostatic discharge pulse is introduced into the semiconductor chip through the pad 21, avalanche by an electrostatic discharge pulse at the drain end of the gate ground NMOS transistor 24 having a gate length smaller than that of the NMOS transistor in the terminator circuit 22 Avalanche) Breakdown occurs and acts as a parasitic element so that high electrostatic discharge current is consumed thermally sufficiently. On the other hand, the NMOS transistor in the terminator circuit 22 also exhibits good characteristics against electrostatic discharge by partially consuming the electrostatic discharge current.

The simulation results of the circuit 20 constituting the gate ground NMOS transistor 24, which is a new electrostatic discharge element, for the high-speed semiconductor device product in which the terminator circuit 22 is connected to the input / output pad 21 is shown in FIGS. 7 to 11 . The simulation was directed to the gate length of the gate ground NMOS transistor 24 being 0.8 times the gate length of the NMOS transistor in the terminator circuit 22 and the applied electrostatic discharge voltage was 800 V as in the conventional case.

FIG. 7 is a diagram illustrating a snapback voltage distribution of each element of the electrostatic discharge protection circuit according to the present invention shown in FIG.

Referring to FIG. 7, the snapback voltage of the gate ground NMOS transistor (?), Which is a protection element, is lower than the snapback voltage of the NMOS transistor (?) Of the terminator circuit. Therefore, when an electrostatic voltage is applied, the gate ground NMOS transistor (?) First operates as a parasitic element.

FIG. 8 is a graph showing a current distribution of each device in the electrostatic discharge protection circuit according to the present invention shown in FIG.

Referring to FIG. 8, it can be seen that the most current flows in the gate-grounded NMOS transistor (?) Which serves as a protective element. That is, the current due to the electrostatic discharge is sufficiently consumed in the gate-grounded NMOS transistor (?), Which is a protection element. On the other hand, the NMOS transistor (& squ &) in the terminator circuit also consumes a part of the electrostatic discharge current.

9 is a diagram showing the temperature distribution of each element of the electrostatic discharge protection circuit according to the present invention shown in Fig. 6, Fig. 9 is an NMOS transistor in a terminator circuit, Fig. 10 is a buffer NMOS transistor, And the temperature distribution of the ground NMOS transistor, respectively.

Referring to FIG. 9, when the electrostatic discharge voltage of 800 V is applied, the temperature at the drain end of each device shows a temperature distribution that is less than 600 K, which is the melting point of each gate poly. That is, as shown in Fig. 9, the current consumption in the terminator circuit is reduced more than before, and in Fig. 11, current consumption is increased in the gate grounded transistor. This shows that the electrostatic discharging current is uniformly distributed among the respective elements to sufficiently consume the electrostatic discharge current, and the gate grounding transistor sufficiently plays the role of the protection element.

Although the case where each transistor constituting the electrostatic discharge protection circuit is an NMOS transistor has been described above, it is obvious that the present invention can be applied to the case where each transistor is a PMOS, and a description thereof will be omitted.

As described above, according to the structure of the present invention, in constructing the electrostatic discharge protection circuit formed on the input / output pad of the high-speed semiconductor device, a gate grounded transistor having a gate length smaller than that of the transistor in the terminator circuit is used as a protection element Thus, there is an advantage that the gate grounding transistor acts as a parasitic element before the transistor of the terminator circuit, plays a role as a protection element, and exhibits good characteristics against electrostatic discharge stress.

Claims (5)

An input / output pad; A terminator circuit including a transistor connected to the input / output pad through a resistor; A gate grounding transistor connected in parallel with the terminator circuit; A buffer transistor connected in parallel with the terminator circuit and the gate grounding transistor, the gate circuit being connected to an internal circuit of the semiconductor device; / RTI > Wherein a gate length of the gate grounding transistor is smaller than that of the transistor in the terminator circuit. 2. The electrostatic discharge protection circuit of claim 1, wherein the gate grounding transistor has a gate length of 0.6 to 0.8 times the gate length of the transistor in the terminator circuit. 3. The electrostatic discharge protection circuit of claim 2, wherein the snapback voltage of the gate grounding transistor is lower than the snapback voltage of the transistor in the terminator circuit. 2. The electrostatic discharge protection circuit of claim 1, wherein the transistor, the gate ground transistor and the buffer transistor in the terminator circuit are NMOS transistors, respectively. 2. The electrostatic discharge protection circuit of claim 1, wherein the transistor, the gate ground transistor and the buffer transistor in the terminator circuit are PMOS transistors, respectively.