KR0184553B1 - Current control circuit of output driver - Google Patents

Abstract

The present invention relates to a current control circuit of a semiconductor memory device for providing a supply current of an output driver for driving a low voltage swing, and a driving method thereof.

2. A technical problem to be solved by the present invention is to provide a current control circuit for providing a stable driving current to an output driver circuit even with changes in ambient temperature and voltage.

3. Summary of the Invention A process for charging the charge line and the supply current of the current mirror circuit and the storage current of a single capacitor in response to an input signal, and the voltage and the reference voltage of the charge line. Comparing and outputting a voltage of the feedback signal; and feeding back the feedback voltage in response to a signal counting signal from which the time of the charge line is charged to the level of the reference voltage is calculated. Through this process, a process for outputting a current when the charge voltage of the charge line and the reference voltage coincide.

4. Significant use of the invention: Suitable for current control circuits.

Description

Current control circuit of output driver and its driving method

1 shows a current control circuit of an output driver according to the prior art.

2 is a view showing a current control circuit of the output driver according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an interface for high speed signal transmission, and more particularly, to a current control circuit of a semiconductor memory device for providing a supply current of an output driver for driving a low voltage swing, and a driving method thereof.

In general, interface systems such as Rambus signal logic (RSL) and gunnlng transistor logic (GTL) proposed by Billinging use low voltage swings (about 2.5V to 1.6V) for high-speed signal transmission. This low voltage swing drives the output driver, which consists of an open-drain and MOS transistor whose drain is connected to the bus. Thus, the output driver transfers data to the input / output port by deriving the current of the precharged busline. The amount of this induced current is converted into a voltage by the terminal resistance Rs of the output driver, and the converted voltage determines the swing width of the voltage. Voh is a high level output voltage, Vterm is a voltage of the precharged bus line, Ioh is a high level current, Rs is a terminal resistance, and Voh and Vol are determined by Equations 1 and 2 below.

Voh = Vterm-Ioh x Rs... … Equation 1

Vol = Vterm-Iol x Rs... … Equation 2

However, the amount of current in the output driver using the low voltage swing changes with temperature and / or applied voltage during operation.

This causes a change in the voltage swing width of the transmitted signal, causing a malfunction of the system. In order to solve this problem, the above problem is solved through the current control circuit of the output driver according to the related art shown in FIG. Referring to FIG. 1, the switching transistor 6 is connected to a charge line 62 of the current mirror circuit 58 as a drain and a charge of the current mirror circuit 58 according to an input signal applied to a gate by being connected to a ground voltage as a source. Discharge or charge the current on line 62. At this time, the current mirror circuit 58 is composed of the morph transistors 2, 4, the gate is coupled to each other, the source voltage is applied to each source. If it is assumed that the size ratio of the type MOS transistors 2 and 4 is M, then the current flowing through the type MOS transistor 4 becomes i / M. Circuit 60 is a charge current control circuit for providing a preset current to the charge line 62 of the current mirror circuit 58 to determine the final charge current value of that charge line 62. The charge current control circuit 60 is composed of transfer gates 16, 18, 20, 22, 24, and 26, each of which is formed of a p-type and en-type MOS transistor having one end connected to the charge line 62. The other end of the respective transmission gates is connected to the capacitors 28, 30, 32, 34, 36, 38. Inverters 40, 42, 44, 46, 48 and 50 are connected to the gates of the shaped and en-type MOS transistors of the transfer gate, respectively. At this time, one end of the capacitor, 28, 30, 32, 34, 36, 38 is connected to the ground voltage and the charging capacity is different. If the capacity of the capacitor 38, which has the smallest capacity, is m, then the capacity is doubled to 2m, 4m, 8m, 16m, 32m in order. The comparison circuit 8 is first applied with a reference voltage and the other end is connected to the charge line 62 to compare and output the voltage of the charge line 62 with the reference voltage. The AND gate 10 receives the input signal and the comparison output voltage of the comparison circuit 8. The AND gate 12 receives a clock signal and an output voltage of the AND gate 10. The hex counter circuit 14 is connected to the AND gate 12 and its output terminal is commonly connected to the transmission gates of the charge current control circuit 60 and the inverters through the inverter 54 so that the charge line 62 is differentiated to the level of the reference voltage. Calculate the time you are aji. The output driver circuit 56 is composed of an expandable open drain en type MOS transistor and outputs data of the bus line precharged to a predetermined level in response to the output voltage from the counter circuit 14.

To describe the operation according to the above structure, since the ratio of the magnitude of the PMOS transistors 2 and 4 constituting the current mirror of the current mirror circuit 58 is M, when the current flowing in the PMOS transistor 2 is I, the PMOS transistor 4 flows i / M. Therefore, when the input signal at the beginning of the start is at the "high" level, the N-type transistor 6 is turned on so that the charge line 62 discharges to the "low" level, and the first output line 66 of the comparison circuit 8 is initially "low". Level, the second output line 64 is initially at the “high” level. As a result, the source PMOS transistor 52 connected to the power supply voltage is turned off to discharge the charge line to the “low” state. Therefore, when the input signal is initially at the "high" level, the counter is in the standby mode in which the operation is stopped. When the input signal is now converted from the "high" level to the "low" level, the N-type transistor 6 is turned off so that the current i / M through the current mirror circuit 58 is charged on the charge line 62 and the current is charged. It is counted by the hex counter circuit 14 until the level of the reference voltage is reached.

Accordingly, the input signal is charged from the "high" level to the "low" level and charged to charge from the moment when the current of the charge line 62 starts charging until the current of the charge line 62 becomes the reference voltage level. The calculated value of the hex counter of the cycle counter circuit 14 over time is applied in parallel to the capacitors 28 to 38 of the charge current circuit 60 to determine the total charge current value of the charge line 62. However, the current I flowing through the current mirror circuit 58 changes according to the temperature of the element and the applied voltage, so that if the current I increases, the charging time T and the hex counter circuit 14 charging the charge line 62 are increased. The calculated value of is inversely reduced, increasing the value of the capacitor connected to the charge line 62 by increasing the value of the capacitor connected to the charge line 62 by increasing the 6-bit data of the node 70, which takes a complementary form, to the 6-bit calculated value of the counter 14 output. do. As a result, the output current value of the counter circuit 14 increases again. The current control circuit of the output driver by the negative feedback method can provide a constant current for the total current flowing in the output driver circuit 56 regardless of the change in temperature and applied voltage, and always transmit a signal having a constant voltage swing width. Can be.

Charge amount charged in charge line 62 Q = (i / M) x T = Total x Vref... … … In Equation 3, the time taken to charge the charge line 62 to the Vref level is T = (Ctotal × Vref) / (i / M) = n <0: 5> × Tcycle. … … Equation 4 Where i / M is the current flowing in the drain of the shaped transistor 4, Ctotal is the sum of the effective capacitances of the charge line 62, Vref is the reference voltage applied to the comparison circuit 8. n <0: 5> is the counter. The output 6-bit data value of circuit 14. nB &lt; 0: 5 &gt; is 6-bit data having the complementary state of the counter circuit 14 inverted by the inverter 54.

The total current used by the output driver circuit 56 during the cycle time Tcycle is I = n <5: 5> × i = M × Ctotal × Vref / Tcycle = M × nb <0: 5> × Cleg × Vref / Tcycle... … … Equation 5 is obtained. Where Ctotal = nB &lt; 0: 5 &gt; … … Equation 6 indicates that Cleg is the size of the smallest capacitor 38 of the capacitors 28-38, which are doubled in size. In this way, the current control structure of the charge current control circuit 60 using the capacitors 28 to 38, which are doubled in size, takes the time T = n &lt; 0: 5 &gt; … … In Equation 7, n <0: 5> may have 64 levels. Therefore, the amount of current that can be driven by the output driver circuit 56 can be controlled through the current control circuit of the output driver of the above-described structure. In order to realize this, in the related art, the capacitors 28 to 38, which are doubled in size, are used so that the total capacitance C total of the charge line 62 may be 64.

However, the size of the capacitors 28 to 38 should be made to increase by exactly 2 times regardless of the process change, but there is a problem that its implementation is difficult.

That is, in design, the size of the capacitor 28 can be realized by using 32 times the size of the capacitor 38 or by designing the capacitor 38 into 32 arrays, but the actual process change such as the undercut of the photo mask is difficult to predict. Due to the elements, it is not easy to implement the capacitor array, which is exactly doubled in size, thereby reducing the accuracy of the circuit operation.

An object of the present invention for the above problem is to provide a current control circuit for providing a drive current of the output driver circuit for driving in a low voltage swing.

Another object of the present invention is to provide a current control circuit for providing a stable driving current to an output driver circuit even with changes in ambient temperature and voltage.

It is still another object of the present invention to provide a current generator circuit and a driving method thereof for stably providing a preset current level to an output driver.

It is still another object of the present invention to provide a current control circuit and a driving method thereof for providing a signal having a constant voltage swing width to an output driver circuit.

Another object of the present invention is to provide a current control circuit having a simple circuit structure and a driving method thereof.

According to the technical idea of the present invention for achieving the above-mentioned group, in the current control circuit of the semiconductor memory device for adjusting the supply current of the output driver, one end of the reference voltage is applied and the other end is connected to the charge line And a comparison circuit section for comparing and outputting the voltage of the charge line and the reference voltage, the gates of the respective circuits are coupled to each other, and the source voltage is applied to the respective sources, Is connected between the current mirror circuit unit for providing different preset currents, and each of the drain and the charge line, and in response to a counting signal and a counting compensation signal, supplies the different preset currents to the charge line. A charge current control circuit unit for determining a final charge current value including transmission gates transmitted to It is commonly connected to the transmission gates and inverters of the charge current control circuit, and connected to the input terminal of the output driver, and outputs the counting signal by calculating the time that the charge line is charged to the level of the voltage voltage. It is characterized by consisting of a counter circuit for.

Also, a process for charging the charge line and the supply current of the current mirror circuit and the storage current of the single capacitor in response to the input signal, and for comparing and outputting the voltage between the charge line voltage and the reference voltage The feedback of the charge line through the process; and the process of feeding back the feedback voltage in response to a counting signal that is a signal from which the voltage of the charge line is charged to the level of the reference voltage. And a process for outputting a current when the aji voltage and the reference voltage coincide.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a view showing a current control circuit of the output driver according to an embodiment of the present invention. Referring to FIG. 2, one end of the comparison circuit 112 is applied with a reference voltage and the other end is connected to the charge line 124 to compare and output the voltage of the charge line 124 with the reference voltage.

The current mirror circuit 134 consists of a plurality of shaped MOS transistors 72, 76, 78, 80, 82, 84, 86. At this time, a source voltage is human and a gate and a drain are commonly connected to the source of the MOS transistor 72. In addition, the gates of the MOS transistors 76, 78, 80, 82, 84, and 86 are coupled to each other with the gates of the MOS transistor 72, and a source voltage is applied to each of the sources, and each of the drains is different in advance. The set current is provided to the transfer gates 88 to 98 of the charge current control circuit 136, which will be described below. The ratios of the sizes m of the plurality of type MOS transistors 72 to 86 are different. That is, if the magnitude of the current flowing in the drain of the Morse transistor 72 is I, the magnitude of the current flowing in the drains of the remaining transistors 76 to 86 of the Morse transistor 72 is i / m, i / 2m, and i /, respectively. The size is changed twice by 4m, i / 8m, i / 16m, i / 32m. Then, when combining these currents, 64 current levels can be charged to the charge line. The current control circuit 136 is composed of transmission gates 88, 90, 92, 94, 96, 98 and inverters 100, 102, 104, 106, 108 and 110. The transfer gates 88 to 98 are connected between the drain of the current mirror circuit and the charge line, and are connected to a counting signal which is an output signal of the counter circuit 118 and a counting compensation signal inverted by the inverters 100 to 110. In response, the different preset currents i / m to i / 32m are transmitted to the charge line 124. The charge line 124 is connected to a single capacitor 122 and is commonly connected to a drain of an N-type mus transistor 74 to which an input signal is applied to a gate, and the single capacitor 122 is responsive to the level of an output line of the comparison circuit 112. And a drain of the switching transistor 130 for transferring the power supply voltage of the drain. Thus, the charge line 124 begins to charge the current when the input signal transitions from the "high" level to the "low" level and charges to the final dodge current level. The output line 132 of the counter circuit 118 is commonly connected to the transfer gates 88 to 98 and the inverters 100 to 110 of the charge current control circuit 136 and to the input terminal of the output driver circuit 120. Accordingly, the time for which the charge line 124 is charged to the level of the air voltage is calculated and outputs a counting signal to the output line 132.

To briefly explain the operation according to this configuration, when the input signal is initially "high", the charge line 124 discharges to the "low" level, and the level of the first output line 128 of the comparison circuit 112 becomes the "low" level. 2 The level of output line 126 becomes the "high" level. Thus, the Morse Morse Transmitter 130 is turned off to discharge the charge line 7 to a "low" level. When the input signal is initially in the "high" state, the counter circuit 118 is in a standby mode to stop operation. At this time, when the input signal is converted from the "high" level to the "low" level, the N-type transistor 74 is turned off, and the transfer gates 88 to 98 are operated according to the counter cycle n <0: 5> value of the counter circuit 118 initially set up. On or off, the charging circuit 118 starts charging the charge line 124 through some or all of the type Morse transistors 72 to 86 of the current mirror circuit 134 and the counter circuit 118 starts mounting. The counter circuit 118 continues to operate while the charge line 124 is charged until the charge line 124 reaches the reference level voltage. The level of the output line 128 becomes "high", the level of the second output line 126 becomes "low" and the counter circuit 118 stops operating. The size of the modulated MOS transistors 72 to 86 is reduced by two times, and the six-bit cycle counter n &lt; 0: 5 &gt;, which is the output of the counter circuit 118, is positively fed back to supply 64 current levels to the charge line 124. Can be. If the current I of the current mirror circuit 134 increases as the temperature of the device and the applied voltage change, the charging time T and the cycle counter n <0: 5> which charge the charge line 124 decrease inversely. The reduction of n <0: 5> increases the charging time T and the cycle caranter n <0: 5> to charge the charge line 124 by reducing the current path that charges 124.

The total current flowing in the current control circuit 136 by this positive feed back method is I = n &lt; 0: 5 &gt; … … It can be kept constant as shown in Equation 8.

Therefore, it is possible to maintain a constant value regardless of changes in temperature, applied voltage, etc., and always provide a signal having a constant voltage swing width.

Charge amount Q = Itotal x T = C x Vref ... charged to the charge line 124. … … It is represented by Equation 9. Where C is the capacitance value of the single capacitor 122, and Itotal is the sum of the amount of current that can flow through the MOS transistors 76-86, where Itotal = n &lt; 0: 5 &gt; … … Expressed in Equation 10, Ileg is the amount of current flowing through MOS transistor 86, corresponding to i / 32m. Thus, Itotal can have 64 current levels.

Further, the time taken to charge the charge line 124 to the voltage level T = C × Vref / Itotal = n <0: 5> × Tcycle. … … It is represented by Equation 11.

Total current that output driver circuit 120 flows during cycle time Tcycle

total current I = n <0: 5> × I

C × Vref / Tcycle × (i / Itotal)

= C × Vref / Tcycle × ｛i / (n0: 5 × Ileg)｝

= C x Vref x 32 m / n0: 5 x Cycle x. … … Equation 12

As can be seen from the equation, when the cycle counter n <0: 5> is determined, the current amount of the output driver circuit 120 is the "current mirror ratio m", "the single capacitance C of the charge line 124", and the "reference voltage Vref". Can be adjusted as a function of

Therefore, according to the present invention as described above, in the prior art, the operational accuracy is reduced due to the unevenness of the capacitor ratio in the capacitor array process, requires a complicated configuration in layout, and also occupies a large area. By using a single capacitance 122 in the control circuit, it is possible to fundamentally eliminate the non-uniformity of the capacitor ratio, thereby increasing the operation accuracy and reducing the layout area.

In addition, in the conventional circuit, a circuit for generating a compensation value is added to implement a negative feedback in the conventional circuit. However, in the circuit of the present invention, a circuit for generating a compensation value by using a positive feedback is not required. There is an effect that can be achieved.

Claims (8)

A current control circuit of a semiconductor memory device for adjusting a supply current of an output driver, comprising: A comparison circuit unit, one end of which a reference voltage is applied and the other end of which is connected to a charge line for comparing and outputting the voltage of the charge line with the reference voltage; A current mirror circuit portion coupled to each gate to each other, a source voltage to each source, and providing different preset currents to the respective drains; A final charge current value including transmission gates connected between the respective drain and the charge line and transmitting the different preset currents to the charge line in response to a counting signal and a counting compensation signal; A charge current control circuit unit for determining a power supply; It is commonly connected to the transfer gates and inverters of the charge pre-fuel control circuit, and connected to the input terminal of the output driver, and outputs the counting signal by calculating the time that the charge line is charged to the level of the reference voltage A current control circuit of a semiconductor memory device, characterized by comprising a counter circuit section. The method of claim 1; The current mirror circuit portion is coupled to a first conductive main MOS transistor having a source voltage applied to a source, and a gate and a drain connected to each other, and a gate to the gate of the first conductive main MOS transistor. The source is a power supply voltage, and each of the drain is a current control circuit of the semiconductor memory device, characterized in that consisting of a plurality of first conductive sub-MOS transistors for providing different predetermined current to the transfer gates. The method of claim 2; And the main and sub-MOS transistors of the first conductive type have different size ratios and output the different preset currents. The method of claim 2 or 3; And the sub-mode transistors of the first conductive type have the size ratios that are increased by twice each. The method of claim 1; And the charge line is commonly connected to a second conductive MOS transistor enabled in response to the input signal, the comparison circuit, the transfer gate, and a single capacitor. The method of claim 2 or 5; And the first conductive type and the second conductive type are blood types and en-types, respectively. A current control method of a semiconductor memory device; Recharging the current provided by the current mirror circuit and the stored current of the single capacitor to the charge line in response to the input signal; Comparing and outputting a voltage between the voltage of the charge line and a reference voltage; and feeding back the feedback signal in response to a counting signal that is a time calculated from which the voltage of the difference line is charged to the level of the air voltage. Process of becoming; And a process for outputting a current when the charge voltage of the charge line and the reference voltage coincide with each other through the feedback process. The method of claim 7; The current control circuit of the current mirror circuit is provided from the drain of the plurality of current mirror type transistors, the current supply circuit characterized in that the current is reduced by two times each.