KR0183765B1 - Inverse-t type lightly doped drain forming method - Google Patents
Inverse-t type lightly doped drain forming method Download PDFInfo
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- KR0183765B1 KR0183765B1 KR1019950049686A KR19950049686A KR0183765B1 KR 0183765 B1 KR0183765 B1 KR 0183765B1 KR 1019950049686 A KR1019950049686 A KR 1019950049686A KR 19950049686 A KR19950049686 A KR 19950049686A KR 0183765 B1 KR0183765 B1 KR 0183765B1
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 46
- 229920005591 polysilicon Polymers 0.000 claims abstract description 46
- 239000012535 impurity Substances 0.000 claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 238000001039 wet etching Methods 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 238000000206 photolithography Methods 0.000 claims abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 5
- 239000011574 phosphorus Substances 0.000 claims abstract description 5
- 238000009413 insulation Methods 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 5
- 239000010410 layer Substances 0.000 abstract description 46
- 239000011229 interlayer Substances 0.000 abstract description 4
- 239000004020 conductor Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 241001014925 Epiglia Species 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
Abstract
반도체 기판에 절연막을 증착하고 불순물이 도핑된 폴리실리콘층/실리사이드층으로 이루어진 폴리사이드(Polycide)층을 형성하는 단계; 사진식각 공정으로 상기 폴리사이드층을 패터닝하는 단계; 습식 식각 공정으로 INVERSE-T(역T자형) 형태의 폴리사이드 게이트를 형성하는 단계; 상기 결과물에 인(P)을 이온 주입하여 반도체 기판에 n-불순물 영역을 형성하는 단계; 상기 폴리사이드 게이트 측면에 절연막 스페이서를 형성하는 단계; 및 상기 결과물에 비소(As)이온을 주입하여 상기 n-불순물 영역내에 n+불순물 영역을 형성하는 단계로 이루어진다.Depositing an insulating film on the semiconductor substrate and forming a polycide layer made of a polysilicon layer / silicide layer doped with impurities; Patterning the polyside layer by a photolithography process; Forming a polyside gate of INVERSE-T (inverse T-shape) form by a wet etching process; Implanting phosphorus (P) into the resultant to form an n-impurity region in a semiconductor substrate; Forming an insulation spacer on the side of the polyside gate; And implanting arsenic (As) ions into the resultant to form an n + impurity region in the n-impurity region.
본 발명으로 인한 반도체 메모리 장치의 ITLDD는 폴리실리콘과 실리사이드가 역T자형인 폴리사이드 게이트를 사용하여 배선이나 층간 도선간의 저항을 감소시키고, 종래의 포토 공정으로 인해 그 제조 공정이 복잡한 것을 습식 식각 공정을 이용함으로써 공정을 단순화하였다.The ITLDD of the semiconductor memory device according to the present invention uses polysilicon gates having polysilicon and silicide in an inverted T-shape to reduce resistance between wiring and interlayer conductors, and the wet etching process is complicated by the conventional photo process. The process was simplified by using.
Description
제1a도 내지 제1f도는 종래 기술에 의한 반도체 메모리 장치의 ITLDD(Invers e-T type Lightly Doped Drain)형성 방법을 순차적으로 도시한 단면도들이다.1A to 1F are cross-sectional views sequentially illustrating a method of forming an inverse e-T type lightly doped drain (ITLDD) of a semiconductor memory device according to the prior art.
제2a도 내지 제2e도는 본 발명에 의한 반도체 메모리 장치의 ITLDD 형성 방법을 순차적으로 도시한 단면도들이다.2A through 2E are cross-sectional views sequentially illustrating a method of forming an ITLDD of a semiconductor memory device according to the present invention.
본 발명은 반도체 메모리 장치에 관한 것으로, 특히 공정을 단순화할 수 있는 반도체 메모리 장치의 ITLDD(Inverse-T type Lightly Doped Drain)형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a method for forming an inverse-T type lightly doped drain (ITLDD) of a semiconductor memory device, which can simplify a process.
반도체 메모리 장치에 있어서 ITLDD의 게이트 구조는 기존의 LDD(Lightly Doped Drain) 구조에 비해 핫 캐리어 효과(HOT CARRIER EFFECT)를 억제시킴으로써 핫 캐리어에 의한 트랜지스터의 전기적 특성 열화 현상을 완화시킨 구조이다.In the semiconductor memory device, the gate structure of the ITLDD is a structure that mitigates the deterioration of the electrical characteristics of the transistor due to the hot carrier by suppressing the hot carrier effect (HOT CARRIER EFFECT) compared to the conventional LDD (Lightly Doped Drain) structure.
반도체 메모리 장치의 제조에 있어서 디바이스의 크기가 축소됨에 따라 디바이스 내부의 전계가 증가해서 소자의 신뢰성이 낮아지는 문제가 발생되고 있는데, 그 중에서도 핫 캐리어 주입에 의한 디바이스 특성의 변동은 서브미크론 디바이스의 신회성 한계를 결정하는 중요한 요소이다. 그래서 게이트의 구조적 측면에서 핫 캐리어 주입에 의한 디바이스 특성의 저하를 방지하기 위한 고내압구조를 위한 변형 게이트들 중에 하나가 바로 ITLDD구조이다.In the manufacture of semiconductor memory devices, as the size of a device decreases, there is a problem in that the reliability of the device decreases due to an increase in the electric field inside the device. It is an important factor in determining the limits of epiglia. Therefore, the ITLDD structure is one of the modified gates for the high breakdown voltage structure to prevent the deterioration of device characteristics by hot carrier injection in terms of the gate structure.
ITLDD 구조에서는 게이트 전극의 형태가 역T자형으로 되어있고 이 게이트 전극의 얇은 부분을 통해서 이온이 주입되어 반도체 기판에 불순물층을 형성한다.In the ITLDD structure, the gate electrode has an inverted T shape, and ions are implanted through the thin portion of the gate electrode to form an impurity layer on the semiconductor substrate.
따라서 상기 불순물층 표면의 캐리어 밀도를 게이트 전극에 의해 어느 정도 제어하고 그 결과 상기 불순물층의 불순물 농도를 낮게 할 수 있으므로 전계완화효과도 크게 된다. 또한 불순물층의 깊이도 작게할 수 있으므로 전계완화효과도 크게 된다. 또한 불순물층의 깊이도 작게할 수 있으므로 쇼트채널효과(Short Channel Effrct)나 펀치쓰루(Punchthrough) 현상도 잘 일어나지 않는다.Therefore, the carrier density on the surface of the impurity layer is controlled to some extent by the gate electrode, and as a result, the impurity concentration of the impurity layer can be lowered, so that the electric field relaxation effect is also increased. In addition, since the depth of the impurity layer can be reduced, the field relaxation effect is also increased. In addition, since the depth of the impurity layer can be reduced, a short channel effect or a punchthrough phenomenon is less likely to occur.
한편 게이트의 구성물질은 반도체 메모리 디바이스의 고집적화와 고온 열처리 공정으로 인하여 폴리실리콘으로 이루어진 워드 선이고 이러한 폴리 실리콘 게이트 전극의 많은 응용이 VLSI 제조 공정에 적용되어지고 있다.On the other hand, the gate material is a word line made of polysilicon due to the high integration and high temperature heat treatment process of the semiconductor memory device, and many applications of the polysilicon gate electrode have been applied to the VLSI manufacturing process.
그러나 반도체 메모리 장치가 더욱 더 고집적화 됨에 따라 그 제조공정의 복잡성 뿐만 아니라 상기 설명한 바와 같이 디바이스의 특성 열화가 나타나기 시작했다.However, as semiconductor memory devices become more highly integrated, not only the complexity of the manufacturing process but also the deterioration of the characteristics of the device as described above have started to appear.
그 중 하나로써 배선 간 및 층간 도선간의 저항 증가를 예로 들수 있다. 이에 대한 대책으로서 원드선 즉 게이트에 금속-실리사이드(Metal-Silicide)의 복합 구조가 대두되었는데 비트선에 폴리사이드 구조를 적용한 것은 이미 오래전의 일이다. 이러한 폴리사이드 구조에 대한 것은 B. L. Crowder과 S. Zirinsky가 1979년에 IEEE Trans.에 이미 발표한 바 있다.One example is an increase in resistance between wires and interlayer wires. As a countermeasure, a complex structure of metal-silicide has emerged at the gate, that is, the gate, and it has been a long time since the polyside structure has been applied to the bit line. This polycide structure was previously published by IEEE Trans. In 1979 by B. L. Crowder and S. Zirinsky.
이러한 폴리사이드 구조는 폴리실리콘/산화막 경계의 우수한 안정성과 실리사이드에 의한 낮은 저항을 제공한다는 장점이 있다.This polyside structure has the advantage of providing excellent stability of the polysilicon / oxide boundary and low resistance by silicide.
제1a도 내지 제1f도는 종래 기술에 의한 반도체 메모리 장치의 ITLDD (Inverse-T type Lightly Doped Drain)형성 방법을 순차적으로 도시한 단면도들이다.1A to 1F are cross-sectional views sequentially illustrating a method of forming an inverse-T type lightly doped drain (ITLDD) of a semiconductor memory device according to the prior art.
참조번호 11은 반도체 기판은, 13은 제1절연막을, 15는 불순물이 도핑된 폴리실리콘층을, 15a·15b는 폴리실리콘 게이트를, 17은 n-불순물 영역을, 19은 절연막 스페이서를, 21은 n+불순물 영역을 각각 나타낸다.Reference numeral 11 is a semiconductor substrate, 13 is a first insulating film, 15 is a polysilicon layer doped with impurities, 15a and 15b is a polysilicon gate, 17 is an n-impurity region, 19 is an insulating film spacer, 21 Represents n + impurity regions, respectively.
제1a도는 폴리실리콘 구조로 이루어진 도전층이 적층된 반도체기판(11)을 나타낸다.FIG. 1A shows a semiconductor substrate 11 in which a conductive layer made of a polysilicon structure is stacked.
반도체 기판(11)에 제1절연막(13)과 불순물이 도핑된 폴리실리콘층(15)을 차례로 형성한다.The first insulating layer 13 and the polysilicon layer 15 doped with impurities are sequentially formed on the semiconductor substrate 11.
상기 불순물이 도핑된 폴리실리콘층(15)은 폴리실리콘 증착후 POCL3분위기에서 열처리를 통한 불순물 확산 방법이나 도우핑된 폴리실리콘(In-situ doped polysililcon)을 바로 적층하는 방법을 사용한다.The impurity doped polysilicon layer 15 uses a method of impurity diffusion through heat treatment in a POCL 3 atmosphere after polysilicon deposition or a method of directly stacking doped polysilicon (In-situ doped polysililcon).
제1b도는 사진 식각 공정으로 상기 불순물이 도핑된 폴리실리콘층(15)을 패터닝하는 단계이다.FIG. 1B is a step of patterning the polysilicon layer 15 doped with the impurity by a photolithography process.
상기 불순물이 도핑된 폴리실리콘층(15)상에 포토 레지스트막(도시하지 않았음)을 증착한 후 폴리실리콘 게이트를 형성하기 위해 상기 포토 레지스트막을 패터닝한다. 이어서 상기 포토 레지스트막을 마스크로하여 상기 폴리실리콘(15)을 이 500~1000Å 정도 남기도록 식삭하여 폴리실리콘 게이트(15a)를 형성한다.After depositing a photoresist film (not shown) on the polysilicon layer 15 doped with impurities, the photoresist film is patterned to form a polysilicon gate. Subsequently, the polysilicon 15 is etched so that the polysilicon 15 is about 500 to 1000 GPa using the photoresist film as a mask to form a polysilicon gate 15a.
제1c도는 상기 결과물에 인(P)을 이온 주입하여 상기 반도체기판(11)에 n-불순물 영역(17)을 형성하는 단계를 나타낸다.FIG. 1C illustrates a step of forming an n-impurity region 17 in the semiconductor substrate 11 by implanting phosphorus (P) into the resultant product.
제1d도는 절연막 스페이스(19)를 형성하는 단계를 나타낸다.FIG. 1D shows the step of forming the insulating film space 19.
상기 결과물에 화학기상증착(CVD)에 의한 산화막등으로 제2절연막을 증착하고 이방성 식각하여 절연막 스페이서(19)를 형성한다.The insulating film spacer 19 is formed by depositing and anisotropically etching the second insulating film using an oxide film by chemical vapor deposition (CVD).
제1e도는 상기 절연막 스페이서(19)를 마스크로하여 상기 반도체기판(11)상에 남아있는 폴리실리콘을 식각하여 Inverse-T자형(역T자형)의 폴리실리콘 게이트(15b)를 형성하는 단계를 나타낸다.FIG. 1E illustrates a step of etching polysilicon remaining on the semiconductor substrate 11 using the insulating film spacer 19 as a mask to form an inverse-T-shaped polysilicon gate 15b. .
제1f도는 상기 결과물에 비소(As)이온을 주입하여 상기 n-불순물 영역(17)내에 n+불순물 영역(21)을 형성함으로써 ITLDD 구조를 완성하는 단계를 나타낸다.FIG. 1f illustrates the step of implanting arsenic (As) ions into the resultant to form an n + impurity region 21 in the n-impurity region 17 to complete the ITLDD structure.
상기와 같은 ITLDD의 게이트 구조는 그 제조 공정이 매우 복잡하며 고집적화에 따라 요구되어지는 게이트의 폭(Length)이 작아질수록 포토마스크를 이용한 게이트 패터닝시 각종 공정 변수 제어가 어려워진다.As described above, the gate structure of the ITLDD is very complicated in manufacturing process, and as the gate length required by the high integration becomes smaller, it becomes more difficult to control various process variables during gate patterning using a photomask.
따라서 본 발명의 목적은 상기의 문제점을 제거하기 위한 반도체 메모리 장치의 ITLDD(Inverse-T type Lightly Doped Drain)형성 방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a method for forming an inverse-T type lightly doped drain (ITLDD) of a semiconductor memory device to eliminate the above problems.
상기 목적을 달성하기 위하여 본 발명은, 반도체 기판에 절연막을 증착하고 불순물이 도핑된 폴리실리콘층/실리사이드층으로 이루어진 폴리사이드(Polycide)층을 형성하는 단계; 사진식각 공정으로 상기 폴리사이드층을 패터닝하는 단계; 습식 식각 공정으로 INVERSE-T(역T자형) 형태의 폴리사이드 게이트를 형성하는 단계; 상기 결과물에 인(P)을 이온 주입하여 반도체 기판에 n-불순물 영역을 형성하는 단계; 상기 폴리사이드 게이트 측면에 절연막 스페이서를 형성하는 단계; 및 상기 결과물에 비소(As)이온을 주입하여 상기 n-불순물 영역내에 n+불순물 영역을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 메모리 장치의 ITLDD(Inverse-T type Lightly Doped Drain) 제조 방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of depositing an insulating film on a semiconductor substrate and forming a polycide layer (Polycide) consisting of a polysilicon layer / silicide layer doped with impurities; Patterning the polyside layer by a photolithography process; Forming a polyside gate of INVERSE-T (inverse T-shape) form by a wet etching process; Implanting phosphorus (P) into the resultant to form an n-impurity region in a semiconductor substrate; Forming an insulation spacer on the side of the polyside gate; And injecting arsenic (As) ions into the resultant to form an n + impurity region in the n-impurity region, thereby providing an inverse-T type lightly doped drain (ITLDD) manufacturing method of a semiconductor memory device. do.
상기 불순물이 도핑된 폴리실리콘은 2000Å이하로, 상기 실리사이드는 1000~3000Å 증착하는 것이 바람직하다.The impurity doped polysilicon is less than 2000 GPa, the silicide is preferably deposited 1000 ~ 3000Å.
상기 습식 식각 공정시 화학 용액의 막질에 대한 선택비, 유속, 유압, 유랑과 식각온도 및 시간을 적절히 조정하여 이방성 식각하는 것이 바람직하다.In the wet etching process, anisotropic etching is preferably performed by appropriately adjusting the selectivity, flow rate, hydraulic pressure, flow rate, and etching temperature and time with respect to the film quality of the chemical solution.
또한 상기 절연막 스페이서는 상기 폴리사이드 게이트중 폴리실리콘층과 실리사이드층 모두를 감싸게 형성하거나 실리사이드층만을 감싸게 형성하는 것이 바람직하다.In addition, the insulating film spacer may be formed to surround both the polysilicon layer and the silicide layer of the polyside gate or to cover only the silicide layer.
본 발명으로 인한 반도체 메모리 장치의 ITLDD는 폴리실리콘과 실리사이드가 역T자형인 폴리사이드 게이트를 사용하여 배선간 및 층간도선간의 저항을 감소시킬 수 있고, 종래의 포토 공정으로 인해 그 제조 공정이 복잡한 것을 습식 식각 공정을 이용함으로써 공정을 단순화할 수 있다.The ITLDD of the semiconductor memory device according to the present invention can reduce the resistance between wires and interlayer conductors using polysilicon gates in which polysilicon and silicide are inverted T-shaped, and the manufacturing process is complicated by the conventional photo process. The process can be simplified by using a wet etching process.
이하 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2e도는 본 발명에 의한 반도체 메모리 장치의 ITLDD(Inverse-T type Lightly Doped Drain) 형성 방법을 순차적으로 도시한 단면도들이다.2A through 2E are cross-sectional views sequentially illustrating a method of forming an inverse-T type lightly doped drain (ITLDD) of a semiconductor memory device according to the present invention.
참조번호 31은 반도체 기판을, 33은 제1절연막을, 35는 폴리실리콘층을, 37·37a는 실리사이드층을, 39는 n-불순물 영역을, 41은 절연막 스페이서를, 43은 n+불순물 영역을 각각 나타낸다.Reference numeral 31 is a semiconductor substrate, 33 is a first insulating film, 35 is a polysilicon layer, 37.37a is a silicide layer, 39 is an n-impurity region, 41 is an insulating film spacer, 43 is an n + impurity region. Represent each.
제2a도는 반도체 기판에 형성된 폴리사이드층을 패터닝하는 단계를 나타낸다.2A illustrates patterning a polyside layer formed on a semiconductor substrate.
반도체 기판(31)에 제1절연막(33)과 불순물이 도핑된 폴리실리콘층을 차례로 적층한다.The first insulating layer 33 and the polysilicon layer doped with impurities are sequentially stacked on the semiconductor substrate 31.
상기 불순물이 도핑된 폴리실리콘층은 2000Å 이하로 형성하는데 폴리실리콘 증착후 POCL3분위기에서 열처리를 통한 불순물 확산 방법이나 도우핑된 폴리 실리폰(In-situ doped polysilicon)을 바로 적층하는 방법을 사용한다.The impurity doped polysilicon layer is formed to be 2000 Å or less, and the method of impurity diffusion through heat treatment in POCL 3 atmosphere after polysilicon deposition or a method of directly stacking doped polysilicon (In-situ doped polysilicon) is used. .
상기 불순물이 도핑된 폴리실리콘층상에 실리사이드층을 1000~3000Å 두게로 증착하는데, 이때 WF6와 SiH4Cl2등을 소오스로하여 PE-CVD(플라즈마 화학기상증착법)을 사용한다.The silicide layer is deposited on the impurity-doped polysilicon layer at a thickness of 1000 to 3000 kPa, using PE-CVD (Plasma Chemical Vapor Deposition) using WF 6 and SiH 4 Cl 2 as a source.
상기 실리사이드층상에 포토레지스막(도시하지 않았음)을 증착하고 사진식각 공정을 실시하여 상기 폴리실리콘층과 상기 실리사이드층을 패터닝하여 폴리실리콘층(35)과 실리사이드층(37)으로 이루어진 폴리사이드층을 형성한다.A photoresist film (not shown) is deposited on the silicide layer and a photolithography process is performed to pattern the polysilicon layer and the silicide layer to form a polysilicon layer 35 and a silicide layer 37. To form.
상기 사진 식각 공정은 ITLDD의 역T자형 게이트중 머리부분의 넓이를 패터닝하는 것으로 종래에 비해 공정 마진(Margin)이 훨씬 개선된다.The photolithography process is to pattern the width of the head portion of the inverted T-shaped gate of the ITLDD process margin is much improved compared to the prior art.
제2b도는 상기 폴리사이드를 습식식각하여 INVERSE-T(역T자형) 형태의 게이트를 형성하는 단계를 나타낸다.FIG. 2b illustrates the step of wet etching the polyside to form an INVERSE-T type gate.
상기 결과물에 화학 용액의 상기 폴리실리콘층(35)과 실리사이드층(37)에 대한 선택비, 유속, 유압, 유량과 식각온도 및 시간을 적절히 조정한 습식 식각(Wet Etch) 또는 습식 클리닝(Wet Cleaning)을 실시하여 폴리실리콘층(35)과 실리사이드층(37a)으로 이루어진 INVERSE-T(역T자형) 형태의 게이트를 형성한다.Wet cleaning or wet cleaning in which the selectivity, flow rate, hydraulic pressure, flow rate and etching temperature and time of the chemical solution of the polysilicon layer 35 and the silicide layer 37 of the chemical solution were properly adjusted. ) To form an INVERSE-T (inverted T-shaped) gate formed of the polysilicon layer 35 and the silicide layer 37a.
제2c도는 인(P)을 이온 주입하여 상기 반도체 기판에 n-불순물 영역(39)을 형성하는 단계를 나타낸다.FIG. 2C illustrates a step of ion implanting phosphorus (P) to form an n-impurity region 39 in the semiconductor substrate.
제2d도는 절연막 스페이서(41)를 형성하는 단계를 나타낸다.2d shows a step of forming the insulating film spacer 41.
상기 결과물에 제2절연막을 증착하고 화학 용액의 막질에 대한 선택비, 유속, 유압, 유량과 식각온도 및 시간을 적절히 조정한 습식 식각 방법으로 이방성 식각하여 절연막 스페이서(41)를 형성한다.The insulating film spacer 41 is formed by depositing a second insulating film on the resultant material and anisotropically etching by a wet etching method in which the selectivity, flow rate, hydraulic pressure, flow rate, and etching temperature and time for the film quality of the chemical solution are appropriately adjusted.
상기의 이방성 식각은 상기 폴리실리콘층(35)과 실리사이드층(37a)으로 이루어진 INVERSE-T(역T자형) 형태의 폴리사이드 게이트에서 상기 폴리실리콘층(35)측면까지 스페이서를 형성하여 변형된 ITLDD구조를 이루는 방법과 상기 폴리실리콘층(35)가 절연막에 대해 선택비가 높은 이방성 식각을 이용하여 상기 폴리실리콘층(35)의 측면에는 스페이서를 형성하지 않도록 하는 방법이 있다.The anisotropic etching is an ITLDD modified by forming a spacer from an INVERSE-T (inverse T-shaped) type polyside gate including the polysilicon layer 35 and the silicide layer 37a to the side of the polysilicon layer 35. There is a method of forming a structure and a method in which the polysilicon layer 35 does not form a spacer on the side surface of the polysilicon layer 35 by using anisotropic etching having a high selectivity with respect to the insulating film.
즉 상기 제2절연막의 습식 식각량을 조절함으로써 후속 공정에서 폴리사이드 게이트에 대한 n-/n+ 불순물 영역의 중첩 간격(Overlap Margin)이 결정된다.That is, the overlap margin of the n− / n + impurity region with respect to the polyside gate is determined in the subsequent process by adjusting the wet etching amount of the second insulating layer.
제2e도는 상기 결과물에 비소(As)이온을 주입하여 상기 n-불순물 영역(39) 내에 n+ 불순물 영역(43)을 형성함으로써 ITLDD 구조를 완성하는 단계를 나타낸다.FIG. 2E illustrates the step of implanting arsenic (As) ions into the resultant to form an n + impurity region 43 in the n-impurity region 39 to complete the ITLDD structure.
본 발명으로 인한 반도체 메모리 장치의 ITLDD는 폴리실리콘과 실리사이드가 역T자형인 폴리사이드 게이트를 이용하여 배선간 및 층간 도선간의 저항을 감소시킬 수 있고, 종래의 포토 공정으로 인해 그 제조공정이 복잡한 것을 습식 식각 공정을 이용함으로써 공정을 단순화할 수 있다.The ITLDD of the semiconductor memory device according to the present invention can reduce the resistance between wires and interlayer wires by using polysilicon gates in which polysilicon and silicide are inverse T-shaped, and the manufacturing process is complicated by the conventional photo process. The process can be simplified by using a wet etching process.
이상, 본 발명은 이에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당 분야에서 통상의 지식을 가진 자에 의하여 가능함은 명백하다.As described above, the present invention is not limited thereto, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.
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