KR0182698B1 - Matching apparatus between lower processor and telephony device - Google Patents
Matching apparatus between lower processor and telephony device Download PDFInfo
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- KR0182698B1 KR0182698B1 KR1019960017429A KR19960017429A KR0182698B1 KR 0182698 B1 KR0182698 B1 KR 0182698B1 KR 1019960017429 A KR1019960017429 A KR 1019960017429A KR 19960017429 A KR19960017429 A KR 19960017429A KR 0182698 B1 KR0182698 B1 KR 0182698B1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/54566—Intelligent peripherals, adjunct processors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M2201/00—Electronic components, circuits, software, systems or apparatus used in telephone systems
- H04M2201/30—PCM
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M2201/00—Electronic components, circuits, software, systems or apparatus used in telephone systems
- H04M2201/34—Microprocessors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/106—Microcomputer; Microprocessor
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13031—Pulse code modulation, PCM
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Abstract
본 정합장치는 교환기에 있어서 하위프로세서와 텔레포니장치간에 PCM방식을 이용하여 정합처리를 하기 위한 것으로서, 본 장치는 하위프로세서와 텔레포니장치간에 접속되어 텔레포니장치의 전송속도를 고려하여 할당된 채널을 통해 펄스폭변조신호를 전송하기 위한 전송라인; 펄스폭변조방식을 이용하여 하위프로세서와 전송라인간에 정합처리를 하기 위한 제1PCM정합부; 펄스폭변조방식을 이용하여 텔레포니장치와 전송라인간에 정합처리를 하기 위한 제2PCM정합부를 포함하도록 구성된다.This matching device is for matching processing by using PCM method between the lower processor and the telephony device in the exchange. The device is connected between the lower processor and the telephony device and pulsed through the assigned channel considering the transmission speed of the telephony device. A transmission line for transmitting the width modulated signal; A first PCM matching unit for performing matching processing between the lower processor and the transmission line using a pulse width modulation method; And a second PCM matching unit for matching processing between the telephony device and the transmission line using the pulse width modulation method.
Description
제1도는 교환기에 있어서 종래의 TD버스정합장치를 구비한 하위프로세서와 텔레포니장치간의 관계도.1 is a diagram showing a relationship between a subprocessor having a conventional TD bus matching device and a telephony device in an exchange.
제2도는 교환기에 있어서 본 발명에 따른 정합장치를 구비한 하위프로세서와 텔레포니장치간의 관계도.2 is a relationship diagram between a subprocessor and a telephony device having a matching device according to the present invention in an exchanger.
제3도는 제2도에 도시된 하위프로세서내에 구비된 PCM정합부의 상세도.3 is a detailed view of the PCM matching unit provided in the subprocessor shown in FIG.
제4도는 제2도에 도시된 텔레포니장치내에 구비된 PCM정합부의 상세도.4 is a detailed view of the PCM matching unit provided in the telephony device shown in FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
200 : 하위프로세서200: subprocessor
201 : PCM(Pulse Code Modulation)정합부201: pulse code modulation (PCM) matching unit
210 : 제1텔레포니장치 211 : 제1PCM정합부210: first telephony device 211: first PCM matching unit
220 : 제2텔레포니장치 221 : 제2PCM정합부220: second telephony device 221: second PCM matching unit
230 : 제3텔레포니장치 231 : 제3PCM정합부230: third telephony device 231: third PCM matching unit
240 : 제N텔레포니장치 241 : 제NPCM정합부240: N-telephony device 241: NPCM matching unit
301 : 메모리 302 : PCM신호 변/복조부301: memory 302: PCM signal modulation / demodulation unit
303, 401 : 물리적 정합부 304, 403 : 제어부303, 401: physical matching unit 304, 403: control unit
402 : PCM채널선택부402: PCM channel selector
본 발명은 교환기에 있어서 하위프로세서와 텔레포니장치(Telephony Device, 이하 TD라고 약함)간의 정합장치에 관한 것으로, 특히 펄스코드변조(Pulse Code Modulation, 이하 PCM이라 약함)방식을 이용한 정합장치에 관한 것이다.The present invention relates to a matching device between a lower processor and a telephony device (hereinafter referred to as TD) in an exchange, and more particularly to a matching device using a pulse code modulation (PCM) method.
교환기에 있어서 하위프로세서는 주로 PP(Peripheral Processor)라고도 하는데, 상위프로세서와 TD사이에 위치하여 신호처리를 한다. 이러한 하위프로세서에는 TD버스를 통해 TD와 데이터 송수신이 가능하도록 정합하는 정합장치가 구비되어 있다. 여기서 TD버스는 수행기능모드, 어드레스, 송신데이타, 수신데이타 및 TB-SEL 등의 각종 제어신호로 구성되며 하위프로세서와 TD간에는 2개의 TD버스로 연결되어 하위프로세서가 지정한 하나의 TD버스를 통해서 통신이 이루어지도록 구성되어 있다.In the exchange, the lower processor is often called a PP (Peripheral Processor), which is located between the upper processor and the TD to perform signal processing. The subprocessor includes a matching device for matching data transmission and reception with the TD via the TD bus. Here, the TD bus is composed of various control signals such as performance mode, address, transmission data, reception data, and TB-SEL, and is connected through two TD buses between the lower processor and the TD and communicates through one TD bus designated by the lower processor. It is configured to be done.
제1도는 이러한 TD버스를 통해 TD와 정합하기 위한 TD버스정합장치(101∼104)를 구비한 하위프로세서(100)와 N개의 TD(110∼113)간의 관계도를 도시한 것이다. 제1도를 통해 알 수 있듯이 하위프로세서(100)에 구비되어 있는 TD버스 정합장치(101∼104)로는 하나의 텔레포니장치(110∼140)만을 접속할 수 있도록 되어 있어 접속하고자 하는 텔레포니장치 수만큼 TD버스 케이블과 TD버스정합장치를 구비하여야 한다. 그러나 TD버스정합장치(101∼104)가 메모리 맵 I/O(Input/Output)방식으로 이루어져 하위프로세서(100)가 제어할 수 있는 TD의 수가 제한되어 많은 수의 TD를 수용하기 위해서는 상대적으로 많은 수의 하위프로세서가 필요한 문제가 있고, 사용가능한 대역폭이 정해져 있어 TD의 동작속도가 정해진 대역폭외의 영역에서 구동되는 경우에는 정합이 어려운 문제가 있었다.FIG. 1 shows a relationship diagram between N TDs 110 to 113 and the subprocessor 100 having the TD bus matching devices 101 to 104 for matching with the TDs through the TD buses. As can be seen from FIG. 1, only one telephony device (110 to 140) can be connected to the TD bus matching devices 101 to 104 provided in the lower processor 100, so that the number of TD devices as many as the number of telephony devices to be connected can be determined. Bus cables and TD bus matching devices are to be provided. However, since the TD bus matching devices 101 to 104 are configured using memory map input / output (I / O) methods, the number of TDs that can be controlled by the subprocessor 100 is limited, so that a large number of TDs can be accommodated. There is a problem that a number of subprocessors are required, and the usable bandwidth is determined, so that matching is difficult when the operating speed of the TD is driven outside the determined bandwidth.
따라서 본 발명의 목적은 상술한 문제점을 해결하기 위하여 교환기에 있어서 하위프로세서와 텔레포니장치간에 PCM방식을 이용하여 정합처리를 하기 위한 정합장치를 제공하는데 있다.Accordingly, an object of the present invention is to provide a matching device for performing a matching process using a PCM method between a subprocessor and a telephony device in an exchanger in order to solve the above problems.
본 발명에 따른 장치는, 교환기에 있어서 하위프로세서와 적어도 1개 이상의 텔레포니장치간을 정합하기 위한 정합장치에 있어서, 하위프로세서와 텔레포니장치간에 접속되어 텔레포니장치의 전송속도를 고려하여 할당된 채널을 통해 펄스폭변조신호를 전송하기 위한 전송라인; 펄스폭변조방식을 이용하여 하위프로세서와 전송라인간에 정합처리를 하기 위한 제1PCM정합부; 펄스폭변조방식을 이용하여 텔레포니장치와 전송라인간에 정합처리를 하기 위한 제2PCM정합부를 포함하는 것을 특징으로 한다.The apparatus according to the present invention is a matching apparatus for matching between a subprocessor and at least one or more telephony apparatuses in an exchanger, the apparatus being connected between the subprocessor and the telephony apparatuses through a channel allocated in consideration of the transmission speed of the telephony apparatuses. A transmission line for transmitting a pulse width modulated signal; A first PCM matching unit for performing matching processing between the lower processor and the transmission line using a pulse width modulation method; And a second PCM matching unit for performing a matching process between the telephony device and the transmission line by using the pulse width modulation method.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시예를 상세하게 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 따른 정합장치를 구비한 하위프로세서와 텔레포니장치간의 관계도로서, 본 발명에 따라 구현된 PCM(Pulse Code Modulation)정합부(201)를 구비한 하위프로세서(200), 본 발명에 따른 PCM정합부(211,221,231,241)를 구비한 제1∼N텔레포니장치(210∼240) 및 하위프로세서(200)와 제1∼N텔레포니장치(210∼240)간에 PCM신호를 전송하기 위한 전송라인(L1)으로 구성된다. 이때 PCM전송라인(L1)은 2.048MHz 속도의 32타임슬롯인 경우를 예를 들어 설명한다.2 is a diagram illustrating a relationship between a subprocessor having a matching device and a telephony device according to the present invention, wherein the subprocessor 200 having a PCM (Pulse Code Modulation) matching unit 201 is implemented according to the present invention. Transmission line for transmitting the PCM signal between the first to N-telephony device (210 to 240) and the lower processor 200 and the first to N-telephony device (210 to 240) having a PCM matching unit (211,221,231,241) according to L1). In this case, the PCM transmission line L1 will be described using an example of a 32 timeslot with a speed of 2.048 MHz.
그러면 제2도와 같이 정합장치를 구비한 하위프로세서와 TD간의 동작을 설명하기로 한다.Next, as shown in FIG. 2, the operation between the subprocessor having the matching device and the TD will be described.
우선, 하위프로세서(200)내의 PCM정합부(201)는 제3도에 도시된 바와 같이 메모리(301), PCM신호 변/복조부(302), 물리적 정합부(303) 및 제어부(304)로 구성되어 하위프로세서(200)와 PCM전송라인(L1)간의 정합처리를 한다. 즉, PCM정합부(201)는 정의된 통신 프로토콜을 기반으로 하위프로세서(200)에 접속되어 있는 각각의 텔레포니장치(210∼240)에 대한 채널과 대역폭을 할당하여 텔레포니장치(210∼240)로 전송할 PCM신호를 구성하고, 텔레포니장치(210∼240)로부터 전송되는 PCM신호를 하위프로세서(200)가 사용할 수 있도록 변환시켜 준다.First, the PCM matching unit 201 in the subprocessor 200 is connected to the memory 301, the PCM signal modulation / demodulation unit 302, the physical matching unit 303, and the control unit 304 as shown in FIG. It is configured to perform a matching process between the lower processor 200 and the PCM transmission line (L1). That is, the PCM matching unit 201 allocates a channel and a bandwidth to each of the telephony devices 210 to 240 connected to the subprocessor 200 based on the defined communication protocol to the telephony devices 210 to 240. A PCM signal to be transmitted is configured, and the PCM signal transmitted from the telephony devices 210 to 240 is converted to be used by the lower processor 200.
이와 같은 신호처리를 위하여, 메모리(301)는 하위프로세서(200)에서 제1∼N텔레포니장치(210∼240)로 전송될 데이터를 PCM신호 변/복조부(302)로 보내기 전에 저장하거나 PCM신호 변/복조부(302)에서 복조되어 출력되는 제1∼N텔레포니장치(210∼240)로부터 전송된 데이터를 하위프로세서(200)로 전달하기 전에 저장하는 역할을 한다.For such signal processing, the memory 301 stores the data to be transmitted from the lower processor 200 to the first to N-telephony devices 210 to 240 before sending the data to the PCM signal modulator / demodulator 302 or the PCM signal. The demodulator / demodulator 302 stores the data transmitted from the first to N-telephony devices 210 to 240, which are demodulated and output before being transmitted to the lower processor 200.
PCM신호 변/복조부(302)는 메모리(301)로부터 전송된 데이터를 하위프로세서(200)에 접속되어 있는 제1∼N텔레포니장치(210∼240)별로 할당된 채널과 대역폭에 맞게 구성한 PCM신호로 변조하여 출력한다. 이 때 제2도에 도시된 예에 의하면, 제1텔레포니장치(210)에 대해서는 128Kbps속도를 지원하기 위하여 32개의 타임슬롯중 0, 1채널을 할당하고, 제2텔레포니장치(220)에 대해서는 128Kbps속도를 지원하기 위하여 2, 3채널을 할당하고, 제3텔레포니장치(230)에 대해서는 768Kbps속도를 지원하기 위하여 4∼15채널을 할당하고, 제N텔레포니장치(240)에 대해서는 64*(31-m+1)속도를 지원하기 위하여 소정의 m타임슬롯에서 31채널까지 할당하여 변조처리를 한다. 여기서 각 텔레포니장치에 할당되는 타임슬롯은 다르게 설정될 수도 있다. 예를 들어 상술한 예에서는 제1텔레포니장치(21)에 0, 1 타임슬롯이 할당되어 있지만 접속되는 제1텔레포니장치(210)의 동작속도가 192Kbps인 경우에는 0∼2타임슬롯이 할당되도록 PCM변조처리가 이루어진다. 또한 PCM신호 변/복조부(302)는 제1∼N텔레포니장치(210∼240)로부터 전송된 PCM신호를 복조하여 메모리(301)로 전송한다.The PCM signal modulator / demodulator 302 configures the data transmitted from the memory 301 to the channel and bandwidth allocated to each of the first to N-telephony devices 210 to 240 connected to the subprocessor 200. Modulate with and output. In this case, according to the example shown in FIG. 2, 0 and 1 channels are allocated among 32 timeslots to support 128 Kbps speed for the first telephony device 210, and 128 Kbps for the second telephony device 220. Allocating 2 or 3 channels to support the speed, allocating 4 to 15 channels to support the 768 Kbps speed for the third telephony device 230, and 64 * (31-) for the N-th telephony device 240 In order to support the speed m + 1), up to 31 channels are allocated in a predetermined m timeslot and modulated. Here, the timeslots allocated to each telephony device may be set differently. For example, in the above-described example, when 0 and 1 timeslots are allocated to the first telephony device 21, but the operating speed of the connected first telephony device 210 is 192 Kbps, the PCM is allocated such that 0 to 2 timeslots are allocated. Modulation processing is performed. In addition, the PCM signal modulator / demodulator 302 demodulates the PCM signal transmitted from the first to N-telephony devices 210 to 240 and transmits the demodulated PCM signal to the memory 301.
물리적 정합부(303)는 PCM신호 변/복조부(302)와 PCM라인(L1)간의 물리적인 정합처리를 한다.The physical matching unit 303 performs a physical matching process between the PCM signal modulation / demodulation unit 302 and the PCM line L1.
제어부(304)는 상술한 메모리(301), PCM신호 변/복조부(302) 및 물리적 정합부(303)의 동작을 제어한다.The controller 304 controls the operations of the memory 301, the PCM signal modulator / demodulator 302, and the physical matcher 303 described above.
한편, 제1∼N텔레포니장치(210∼24)내에 구비되어 있는 제1∼N PCM정합부(211,221,231,241)는 제4도에 도시된 바와 같이 물리적 정합부(401), PCM채널선택부(402) 및 제어부(403)로 구성되어 자신에게 할당된 채널을 이용하여 PCM라인과 해당 텔레포니장치간의 정보를 송수신한다.On the other hand, the first to N PCM matching units 211, 221, 231 and 241 provided in the first to N telephony devices 210 to 24 have a physical matching unit 401 and a PCM channel selection unit 402 as shown in FIG. And a control unit 403, which transmits and receives information between the PCM line and the corresponding telephony device by using a channel assigned to the controller.
이와 같은 송수신처리를 위하여, PCM채널 선택부(402)는 제어부(403)에 의해 제어되어 자신에게 할당된 채널의 신호를 수신하고, 수신된 신호를 해당 텔레포니장치 내부로 전송하고, 해당 텔레포니장치로 부터의 출력되는 데이터를 자신에게 할당된 채널에 실어 송신하는 역할을 수행한다.For such transmission and reception processing, the PCM channel selection unit 402 is controlled by the control unit 403 to receive a signal of a channel assigned to itself, and transmits the received signal to the corresponding telephony device to the corresponding telephony device. It plays the role of transmitting the output data from the channel assigned to itself.
물리적 정합부(401)는 PCM전송라인(L1)과 PCM채널선택부(402)간의 물리적인 정합처리를 한다.The physical matching unit 401 performs a physical matching process between the PCM transmission line L1 and the PCM channel selector 402.
제어부(403)는 상술한 PCM채널선택부(402), 물리적 정합부(401)의 동작을 제어한다.The controller 403 controls the operations of the PCM channel selector 402 and the physical matcher 401 described above.
이상, 상술한 바와 같이 본 발명은 PCM방식을 이용하여 하위프로세서와 텔레포니장치간의 정합처리를 함으로써, 텔레포니장치의 추가 설치시 동작속도를 고려하여 채널을 할당해 주기만 하면 되므로 확장성이 뛰어날 뿐아니라 하나의 케이블을 이용하여 데이터를 송수신하므로 종전에 비해 상대적으로 케이블의 수를 줄일 수 있어 설비의 구성 및 설치가 용이하다. 또한 채널할당에 의하여 원하는 대역폭을 지원할 수 있으므로 동작속도가 다른 텔레포니장치들과의 정합이 용이한 효과 등이 있다.As described above, the present invention performs the matching process between the lower processor and the telephony device by using the PCM method, so that only the channel should be allocated in consideration of the operation speed when the telephony device is additionally installed. Since data is transmitted / received using cable, the number of cables can be relatively reduced compared to the past, so the configuration and installation of facilities is easy. In addition, since the desired bandwidth can be supported by channel assignment, it is easy to match with other telephony devices having different operating speeds.
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KR1019960017429A KR0182698B1 (en) | 1996-05-22 | 1996-05-22 | Matching apparatus between lower processor and telephony device |
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KR1019960017429A KR0182698B1 (en) | 1996-05-22 | 1996-05-22 | Matching apparatus between lower processor and telephony device |
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