KR0181754B1 - Data service unit - Google Patents

Abstract

An object of the present invention is to provide a data service apparatus including a circuit for detecting a polarity violation pulse of a bipolar digital signal to determine a line state.

The present invention receives data from a data terminal of a local station, converts the data into a bipolar digital signal, and transmits the data to the data transmission / reception unit 23, or converts the data from the counterpart data terminal received by the data reception unit 24 into a unipolar digital signal. A terminal connecting portion 22 for converting and transmitting the data to the data terminal of the local station, a data transmitting portion 23 for transmitting data to the data port apparatus 81 via the transmission line, and a data port apparatus 81 via the receiving line. A data processing unit 21 including a data receiving unit 24 for inputting data from the apparatus; A data service apparatus including a central processing unit (91) for controlling the operation of the data processing unit (21), wherein a pulse in violation of polarity is detected from a bipolar digital signal input from the data receiving unit (24) to the terminal connection unit (22). The control signal detector 51 detects a control signal from a bipolar digital signal input from the data receiver 24 to the terminal connection unit 22, and the violation pulse detector 41 detects the control signal. It is connected to the above-mentioned pulse masking unit 61 for removing the control pulse from the above-mentioned pulses, the above-mentioned pulse masking unit 61 and the central processing unit 91 and counted the number of the above-mentioned pulses excluding the control signal. It further comprises a violation pulse determination unit 31 composed of a violation pulse counting unit 71 for outputting the to the central processing unit (91).

Description

Data service apparatus provided with line state determination means

The present invention relates to a data communication device, and more particularly, to a data service unit (DSU) used for data communication through a data service network.

1 is a block diagram of a conventional data service apparatus.

Referring to FIG. 1, a conventional data service apparatus receives data from a data terminal of a local station, converts the data into a bipolar digital signal, and transmits the data to the data transmission / reception unit 3 or from a counterpart data terminal received by the data reception unit 4. A data port device 11 connected to the terminal connection part 2 for converting the data of the data into a unipolar digital signal and transmitting it to a data terminal of the local station, and connected to the terminal connection part 2 and the data port device 11 via a transmission line. A data transmitter (3) for transmitting data to the terminal, and a data receiver (4) for connecting data to the terminal connection unit (2) and the data port device (11) and inputting data from the data port device (11) via a receiving line. A data processing unit 1 including; The central processing unit 12 is connected to the data processing unit 1 and controls the operation of the data processing unit 21.

The operation of the data service device of FIG. 1 will be described.

First, in the transmission operation, the data input from the data terminal of the local station is converted into a bipolar digital signal at the terminal connection unit 2, and then the data transmission unit 3, the data port device 11 of the own station, and the data port device of the other station (not shown). (Not shown) is transmitted to the data receiving unit (not shown) of the transceiver circuit of the counterpart data service apparatus.

In the receiving operation, data from the counterpart data terminal inputted to the terminal connecting unit 2 via the data port device (not shown) of the other station, the data port device 11 of the local station and the data receiving unit 4 is unipolar digital. It is converted into a signal and transmitted to the local data terminal.

The conventional data service apparatus does not include a circuit that can determine whether there is an error in the line, so there is a problem in that the error of the line cannot be known.

An object of the present invention is to provide a data service apparatus including a circuit for detecting a polarity violation pulse of a bipolar digital signal to determine a line state.

1 is a block diagram of a conventional data service apparatus.

2 is a block diagram of a data service device according to the present invention.

3 is a diagram showing an embodiment of the violation pulse determining unit 31 shown in FIG.

4 is an operation timing diagram according to an embodiment of the violation pulse detection unit 41 shown in FIG.

* Explanation of symbols for main parts of the drawings

2,22 terminal connection unit 3,23 data transmission unit

4,24: data receiving unit 11,81: data port device

12,91: central processing unit 31: violation pulse determination unit

FF: Flip-Flip AND, NAND, OR, EXOR, INV: Logic Gate

2 is a block diagram of a data service device according to the present invention.

Referring to FIG. 2, the present invention receives data from a data terminal of a local station, converts it into a bipolar digital signal, and transmits the data to the data transmission / reception unit 23 or data from a counterpart data terminal received by the data reception unit 24. Is connected to the terminal connection section 22 and the data port device 81 via the transmission line to the data port device 81 via the transmission line. A data transmitter 23 for transmitting data, and a data receiver 24 for connecting the terminal connection 22 and the data port device 81 to input data from the data port device 81 via a receiving line; A data processor 21 for performing; A data service apparatus including a central processing unit (91) connected to the data processing unit (21) to control the operation of the data processing unit (21), wherein the data connection unit is connected to the terminal connection unit (22) and the data receiving unit (24). A violation pulse detection section 41 for detecting a pulse in violation of polarity from the bipolar digital signal inputted from the terminal connection section 22 to the terminal connection section 22 and a violation pulse detection section 41 are connected to the terminal to receive the data from the terminal. The control signal detector 51 detects a control signal from the bipolar digital signal inputted to the connection unit 22, and connects to the violation pulse detection unit 41 and the control signal detection unit 51 and detects the violation pulse detection unit 41. The number of violation pulses excluding the control signal is counted by connecting to the violation pulse masking unit 61 which removes the control pulse from one violation pulse, and the violation pulse masking unit 61 and the central processing unit 91. It further includes a violation pulse determination unit 31 composed of a violation pulse counting unit 71 for outputting the value to the central processing unit 91.

The data transmission process in the data service device according to the present invention is performed in the same manner as in the conventional case.

3 is a diagram showing an embodiment of the violation pulse determination unit 31 shown in FIG. 2, and FIG. 4 is an operation timing diagram of the embodiment of the violation pulse determination unit 31 shown in FIG.

Referring to FIG. 3, the violation pulse determining unit 31 according to the embodiment of the present invention connects to the positive signal line and latches the first signal according to the reception clock. A second di flip-flop (DFF) 43 which is connected to a signal line of L and latches a negative signal according to the reception clock, and is connected to the first di flip-flop 42 and the second di flip-flop 43 to receive a reception clock. JK flip-flop 44 and the D flip-flop 42 and the JK flip-flop 44 are operated according to the output of the first and second flip-flop 42 and 43 A second NAND gate 45 connected to a Q output terminal, an inverter INV 49 connected to a Q output terminal of the JK flip-flop 44, the inverter INV 49 and a second di flip-flop 43 A violation pulse detection unit (41) including a first NAND gate (46) connected to a Q output terminal of the gate, and an AND gate (45) connected to the first and second NAND gates (46); A second OR gate 52 connected to the first flip-flop 42 and the second flip-flop 43 of the violation pulse detection unit 41, the second OR gate 52 and the violation pulse detection unit 41; A control pulse judging unit 53 which is connected to an AND gate 47 and detects the presence or absence of a control pulse at the output of the second OR gate 52 using the output of the AND gate 47 as an enable signal, and A control signal detection unit 51 including a first OR gate 54 connected to the control pulse determination unit 53; An EXOR gate 61 connected to the first OR gate 54 of the control signal detector 51 and the AND gate 47 of the violation pulse detector 41; A counter 71 is connected to the EXOR gate 61 and the central processing unit 91.

The violation pulse determination operation of the violation pulse determination unit 31 according to the embodiment of the present invention will be described.

First, a violation pulse detection operation of the violation pulse detection unit 41 will be described with reference to FIG. 4, which is an operation timing diagram according to the embodiment of the violation pulse detection unit 41 shown in FIG. 3.

A in FIG. 4 shows the reception clocks input to the two de-flips 42 and 43 and the JK flip-flop 44.

B and c in FIG. 4 represent signals input to the two de-flips 42 and 43 from the positive signal line and the negative signal line, respectively, and two violation pulses (the seventh to b signal of FIG. 4th signal in c) is shown.

The output of the first di flip-flop 42 in FIG. 3 is d in FIG. 4, and the output of the second flip-flop 43 is e in FIG. 4.

The Q output terminal of the JK flip-flop 44 of FIG. 3 becomes f of FIG. 4, and the output of the inverter 49 of FIG. 3 becomes g of FIG.

The output of the second NAND gate 45 is h in FIG. 4, and the output of the first NAND gate 46 is i in FIG. 4.

The output of the AND gate 47 becomes j in FIG. 4 and coincides with two violation pulses input to the positive signal line and the negative signal line.

In the process of determining whether the violation pulse is a control signal, since the control pulse is coded to have the violation pulse in the data service device, the control signal determination unit 53 matches the control pulse in the signals appearing on the positive signal line and the negative signal line. The code can be detected to determine whether the violation pulse is a control signal.

In the process of excluding the control pulse from the violation pulse, when the output of the first OR gate 54 is high, the output of the AND gate 47 does not become low, and the violation is not a control pulse. When the output of the AND gate 47 indicating the presence of a pulse is high and the output of the first OR gate 54 goes low, the output of the EXOR gate 61 becomes high, so that the control pulse can be excluded from the violation pulse. .

The violation pulse counted by the counter 71 is transferred to the central processing unit to determine the track state based on the number of violation pulses.

As described above, in the data service device of the present invention, a circuit for detecting a violation pulse of a bipolar digital signal is further configured in the conventional data service device to count the number of violation pulses, so that the state of the line is changed according to the number of violation pulses. Can be determined.

Claims (2)

Receives data from the local station's data terminal and converts it into a bipolar digital signal for transmission to the data transmission / reception unit 23, or converts data from the counterpart data terminal received at the data receiving unit 24 into a unipolar digital signal A terminal connecting portion 22 for transmitting to the data terminal, a data transmitting portion 23 for connecting data to the terminal connecting portion 22 and the data port apparatus 81 and sending data to the data port apparatus 81 via the transmission line; A data processing unit 21 connected to the terminal connecting unit 22 and the data port device 81 and including a data receiving unit 24 for inputting data from the data port device 81 via a receiving line; A data service apparatus including a central processing unit (91) for connecting to the data processing unit (21) to control the operation of the data processing unit (21), wherein the data connection unit is connected to the terminal connection unit (22) and the data receiving unit (24). A violation pulse detection section 41 for detecting a pulse in violation of polarity from the bipolar digital signal inputted from the terminal connection section 22 to the terminal connection section 22 and a violation pulse detection section 41 are connected to the terminal to receive the data from the terminal. The control signal detector 51 detects a control signal from the bipolar digital signal inputted to the connection unit 22, and connects to the violation pulse detection unit 41 and the control signal detection unit 51 and detects the violation pulse detection unit 41. The number of violation pulses excluding the control signal is counted by being connected to the violation pulse masking unit 61 which removes the control pulse from one violation pulse, and the violation pulse masking unit 61 and the central processing unit 91. Data service unit to the value, characterized in that it further comprises a violation pulse determination unit (31) consisting of a violation of the pulse counting unit 71 is outputted to the central processing unit (91). 2. The false pulse determining unit (31) according to claim 1, wherein the violation pulse determining unit (31) is connected to a positive signal line and latches a positive signal according to a reception clock. A second di flip-flop (DFF) 43 for latching a negative signal in accordance with a clock and the first di flip-flop 42 and the second di flip-flop 43 are connected to the first di flip-flop according to a reception clock. JK flip-flop 44 which operates by using the outputs of the flip 42 and the 2D flip-flop 43, and a second NAND connected to the Q output terminals of the D flip-flop 42 and the JK flip-flop 44. An inverter INV 49 connected to the gate 45, a Q output terminal of the JK flip-flop 44, and a Q output terminal connected to the Q output terminal of the inverter INV 49 and the second di flip-flop 43; A violation pulse detection unit 41 including a 1NAND gate 46 and an AND gate 45 connected to the first NAND gate 46 and the second NAND gate 45; A second OR gate 52 connected to the first di flip-flop 42 and the second di flip-flop 43 of the violation pulse detection unit 41, the second OR gate 52 and the violation pulse detection unit 41; A control pulse judging unit 53 which is connected to an AND gate 47 and detects the presence or absence of a control pulse at the output of the second OR gate 52 using the output of the AND gate 47 as an enable signal, and A control signal detection unit 51 including a first OR gate 54 connected to the control pulse determination unit 53; An EXOR gate 61 connected to the first OR gate 54 of the control signal detector 51 and the AND gate 47 of the violation pulse detector 41; And a counter (71) connected to said EXOR gate (61) and a central processing unit (91).