KR0179179B1 - Method for selecting optimal order for atm processor - Google Patents

Abstract

The present invention relates to a method of selecting an optimal instruction sequence for selecting an optimal instruction sequence at the rear end of an optimized compiler for an Asynchronous Transfer Mode (ATM) processor. In order to provide an optimal instruction sequence selection method that can generate optimal code for conditional branching when developing, select an optimization pattern that can convert conditional branching to arithmetic function of the same function, and use super optimization to Selecting a command sequence having a minimum dynamic coefficient after retrieving the command sequence having the smallest coefficient; Converting the selected optimal instruction sequence into a form suitable for the machine description table format, combining the extended optimal machine description table to form an executable compiler rear end, and experimenting to determine whether interference between the instruction sequences has occurred; And a third step of repeating the second step from the second step as a result of the determination of the second step, and if the interference does not occur, storing the optimal instruction sequence in the machine description table. There is an effect that can increase the efficiency.

Description

How to Select Optimal Instruction Sequence for Asynchronous Processors

1 is a block diagram of hardware to which the present invention is applied.

2 is a flow diagram of one embodiment according to the present invention.

3 is a detailed flowchart of an optimization pattern selection process according to the present invention.

4 is a flowchart of an instruction sequence selection process using super optimization according to the present invention.

5 is a detailed flowchart of a procedure of selecting a procedure having a minimum dynamic coefficient according to the present invention.

6 is a detailed flowchart of a process for reflecting in a compiler machine description table according to the present invention.

* Explanation of symbols for main parts of the drawings

101: main memory board 102: central processing board

103: general purpose operating system 104: auxiliary storage device

105: input / output device 106: system bus

The present invention relates to a method for selecting an optimal instruction sequence to enable the selection of an optimal instruction sequence at the rear end of an optimized compiler for an Asynchronous Transfer Mode (ATM) processor.

ATM processors are superscalar processors that can execute multiple instructions simultaneously in one clock cycle. The ATM processor can theoretically execute up to three instructions at the same time, but it is often impossible to execute them simultaneously depending on the combination of instruction sequences, so in practice, 1.5 instructions per clock are averaged. Therefore, optimization for ATM processors should focus on reducing the number of clock cycles (dynamic coefficients) required to perform a given code sequence rather than the length of the code sequence listed (static coefficients).

The conditional branch instruction, which determines whether a particular task is performed according to the result of the comparison decision in the super color processor, creates a burden of increasing the execution time by two cycles by inhibiting the possibility of concurrent execution of the instruction sequence. Therefore, a compiler for an ATM processor essentially requires an optimization function for generating object code such that performance degradation due to conditional branching does not occur as much as possible.

Accordingly, an object of the present invention is to provide an optimal instruction sequence selection method for generating an optimal code for conditional branching when developing a CHILL compiler for an ATM superscalar processor.

In order to achieve the above object, the present invention, in the optimal instruction procedure method applied to an apparatus having an asynchronous transfer mode (ATM) processor, selects and optimizes the optimization pattern that can convert the conditional branch into arithmetic expression of the same function A first step of selecting an instruction sequence having a minimum dynamic coefficient after retrieving an instruction sequence having a minimum static coefficient using optimization; Converting the selected optimal instruction sequence into a form suitable for the machine description table format, combining the extended optimal machine description table to form an executable compiler rear end, and experimenting to determine whether interference between the instruction sequences has occurred; And a third step of repeating from the second step if the interference has occurred as a result of the determination of the second step, and storing the optimum instruction sequence in the machine description table if the interference has not occurred. .

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

1 is a configuration diagram of hardware to which the present invention is applied, 101 is a memory board of a system, 102 is a central processing board, 103 is a general-purpose operating system, 104 is an auxiliary memory device, 105 is an input / output device, 106 is a system bus Respectively.

Looking at the function of each block shown in the figure, the main memory board 101 of the system is a board on which an optimization compiler having a rear end capable of generating an optimal code for an ATM processor is mounted, and the central processing board 102 is The board is equipped with an ATM processor for executing a program mounted on the main memory board 101.

The auxiliary memory 104 is a device for storing intermediate files for storing temporary data during the compilation process and the compiler, and stores data that cannot be stored in the volatile main memory board 101.

The input / output device 105 is a device for inputting / outputting all data and error messages used or generated in the compilation process. The universal operating system 103 controls the boards and devices, and messages transmitted and received between the boards and the devices are transmitted through the system bus 106.

2 is an overall flowchart of an embodiment according to the present invention.

First, in order to enable the CHILL compiler for ATM processors to generate optimal instruction sequences, we select optimization patterns for cases where conditional branches can be transformed into arithmetic expressions of the same function using algebraic rules ( 201) The ATM processor retrieves all instruction sequences with the least static coefficients for the arithmetic expressions corresponding to the optimization pattern in the conditional branch using the Super Optimizer, one of the compiler automation tools, and takes into account the superscalar features of the ATM processor. Select from among the procedures with the least static coefficients, in particular the order with the least dynamic coefficient (203).

Subsequently, in order to reflect the selected optimal instruction sequence to the CHILL compiler, it is necessary to convert it into a form suitable for the machine description table format at the rear end of the compiler (204). Perform a simple optimization.

Thereafter, the extended machine description table is combined (205) to reflect the optimization pattern in a system capable of automatically generating the compiler rear end to form an executable compiler rear end. Experiment with the modified compiler (206) to determine if interference between the various instruction sequences in the machine description table has occurred (207). If interference occurs and the effect of the optimization is lost, go back to step 204 to explain After reordering the sequence of instructions in the table, proceed to step 207.

On the other hand, the interference between the instruction sequences does not occur, and the instruction sequence corresponding to the pattern in which the effect of optimization is confirmed is semi-permanently recorded in the machine description table (208). If the optimization pattern remains, the process returns to step 201 and the same process is repeated for the remaining optimization patterns.

3 is a detailed flowchart of the optimization pattern selection process according to the present invention, which examines various cases where conditional branches are simply not aimed at branches and may be combined with other functions to perform the same function using algebraic rules. Performs a function for finding a combination of arithmetic and shift operations.

The variable increase and decrease pattern is a pattern for increasing or decreasing the value of a specific variable when the result of the condition determination is true. The variable setting / erase pattern is a pattern for setting a specific variable to a true value or a false value according to the result of the condition determination. The special pattern is not a direct branch expression such as an absolute value or a maximum value, but a program pattern that can produce different results according to the result of the judgment of the condition.

First, select phrases with which the conditional branch is likely to be combined with other functions (301), parse them (302), record variable increment patterns if variable increments (303), and set variable / An erase pattern is recorded (304), and if it is a special pattern, a special pattern is recorded (305).

For each of these cases, it is determined whether or not it can be converted to an arithmetic expression using most of the conversion rules (306), and if possible, the corresponding arithmetic expression is obtained (307).

4 is a detailed flowchart of an instruction sequence selection process using super optimization according to the present invention.

First, the arithmetic expression for the conditional branch optimization pattern is converted into a form applicable to the super optimizer (401), and the reflected super optimizer is compiled to obtain an executable program (402). The target function is called to obtain an instruction sequence with the minimum static coefficient (403).

5 is a detailed flowchart of an instruction procedure selection process with minimum dynamic coefficients according to the present invention.

First, a command sequence is input (501) to check whether the pattern static coefficient is 5 or less.

In the case of an ATM processor, the execution effort for one branch instruction can be seen as similar to the effort for four integer operations. Is against. The super optimization technique on which the present invention is based is also practical only when the length of the instruction sequence is 5 or less. For this reason, in the example of the present invention, only the case where the static coefficient of the pattern is 5 or less is considered.

On the other hand, if the pattern static coefficient is less than or equal to 5, the dynamic coefficient of each instruction sequence is determined in consideration of the characteristics of the superscalar processor (504), and then the procedure having the minimum dynamic coefficient is selected among them (505). . If there are two or more procedures with the same dynamic coefficients, the procedure selects the minimum number of temporary registers required (506) and the procedure using less condition codes (507).

6 is a detailed flowchart of the conversion process to reflect the compiler machine description table according to the present invention.

First, the possibility of sharing a temporary register in an ATM processor instruction sequence with a minimum dynamic coefficient corresponding to a particular optimization pattern is examined (601) and if it is possible to share it, this is reflected in the instruction sequence (602), and the resulting instruction sequence is obtained. (603) is converted into a machine description table input format for generating the rear end of the CHILL compiler. The position of the instruction sequence in the machine description table has a significant impact on the applicability of the optimization, so that it is an appropriate position that does not interfere with other instruction sequences (where it is applied before any other pattern that might change the pattern you want to reflect). (604) and the procedure is arranged (605).

The present invention as described above has the effect that the compiler of the superscalar processor can increase the efficiency of conditional synchronization.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

Claims (5)

In the optimal instruction procedure selection method applied to a device having an asynchronous transfer mode (ATM) processor, an optimization pattern that can convert a conditional branch into an arithmetic function of the same function is selected, and super optimization is used to minimize the static coefficient. A first step of selecting an instruction sequence having a minimum dynamic coefficient after retrieving the instruction sequence; A second step of converting the selected optimal instruction sequence into a form suitable for the description table format, combining it with the extended machine description table to construct an executable compiler rear end, and then experimenting to determine whether interference between the instruction sequences has occurred; And a third step of repeating from the second step if the interference has occurred as a result of the determination of the second step, and storing the optimal command sequence at all times in the machine table if the interference has not occurred. The method of claim 1, wherein the selecting of an optimization pattern capable of converting the conditional branch of the first step into an arithmetic expression of the same function comprises: a fourth step of analyzing the syntax after selecting the conditional branch-related syntax; A fifth step of recording the variable increase / decrease pattern if the variable increases / decreases, records the variable set / erase pattern if the variable is set / erased, and records the special pattern if the special pattern; And determining whether the arithmetic expression can be converted to an arithmetic expression using the algebraic conversion rule for the number of cases performed in the fifth step, and obtaining a corresponding arithmetic expression if possible, and excluding the optimization target if not possible. A method for selecting an optimal instruction sequence comprising a step. The method of claim 1 or 2, wherein the searching of the instruction sequence having the minimum static coefficient by using the super optimization of the first step is a form in which an arithmetic expression for a conditional branch optimization pattern can be applied to the super optimizer. Converting to a seventh step; An eighth step of obtaining an executable program by compiling the extended super optimizer by reflecting the conversion result; And a ninth step of calling a target function for the optimization pattern to obtain an instruction sequence with a minimum static coefficient. The method of claim 1 or 2, wherein the step of selecting an instruction sequence having the minimum dynamic coefficient of the first step comprises: inputting the instruction sequence to investigate whether the pattern static coefficient is less than or equal to a predetermined value; step; An eighth step of excluding the target of optimization if the result of the seventh step is greater than a predetermined value; If the pattern static coefficient is less than or equal to the predetermined value as a result of the investigation in the seventh step, the dynamic coefficient of each instruction sequence is obtained, the procedure having the minimum dynamic coefficient is selected, and the minimum number of temporary registers and the minimum condition code sequence are determined. A method for selecting an optimal instruction sequence comprising a ninth step of selecting. 3. The process of claim 1 or 2, wherein the step of converting the selected optimal instruction sequence of the second step into a form suitable for a machine description table format is temporary in an ATM processor instruction sequence having a minimum dynamic coefficient corresponding to a particular optimization pattern. A seventh step of examining the shareability of the registers and reflecting them in the instruction sequence; An eighth step of converting the instruction sequence resulting from the reflection of the instruction sequence into a machine description table input format for generating a CHILL compiler rear end; And a ninth step of arranging an optimal instruction sequence by determining a position which does not cause interference with other explanation procedures.