KR0179139B1 - Method for forming polycrystalline silicon layer - Google Patents
Method for forming polycrystalline silicon layer Download PDFInfo
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- KR0179139B1 KR0179139B1 KR1019950027192A KR19950027192A KR0179139B1 KR 0179139 B1 KR0179139 B1 KR 0179139B1 KR 1019950027192 A KR1019950027192 A KR 1019950027192A KR 19950027192 A KR19950027192 A KR 19950027192A KR 0179139 B1 KR0179139 B1 KR 0179139B1
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- amorphous silicon
- silicon layer
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- polysilicon
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 24
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 42
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims 4
- 230000009977 dual effect Effects 0.000 abstract description 3
- 239000010409 thin film Substances 0.000 description 8
- 239000013078 crystal Substances 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 210000001787 dendrite Anatomy 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 다결정실리콘층 형성방법에 관한 것으로, 균일하고 우수한 특성을 갖는 다결정실리콘을 형성하기 위한 것이다.The present invention relates to a method for forming a polysilicon layer, to form a polysilicon having uniform and excellent characteristics.
본 발명은 기판상에 SiH4가스를 이용하여 제1비정질실리콘을 증착하는 단계와,상기 제1비정질실리콘층위에 Si2H6가스를 이용하여 제2비정질실리콘을 증착하는 단계, 및 상기 이중구조로 형성된 비정질실리콘층을 열처리하여 다결정실리콘층을 형성하는 단계로 이루어지는 다결정실리콘층 형성방법을 제공한다.The present invention comprises depositing a first amorphous silicon using a SiH 4 gas on a substrate, depositing a second amorphous silicon using a Si 2 H 6 gas on the first amorphous silicon layer, and the dual structure It provides a polysilicon layer forming method comprising the step of forming a polysilicon layer by heat-treating the amorphous silicon layer formed by the.
Description
제1도 및 제2도는 종래기술에 의한 다결정실리콘층 형성방법을 도시한 공정순서도.1 and 2 are process flowcharts showing a polysilicon layer forming method according to the prior art.
제3도는 본 발명의 일실시예에 의한 다결정실리콘층 형성방법을 도시한 공정순서도.3 is a process flowchart showing a polysilicon layer forming method according to an embodiment of the present invention.
제4도는 본 발명의 다른 실시예에 의한 다결정실리콘층 형성방법을 도시한 공정순서도.4 is a process flowchart showing a polysilicon layer forming method according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 기판 12 : SiH4-비정질실리콘층11 substrate 12 SiH 4 -amorphous silicon layer
13 : Si2H6-비정질실리콘층 14 : 다결정실리콘층13: Si 2 H 6 -amorphous silicon layer 14: polycrystalline silicon layer
본 발명은 다결정실리콘층 형성방법에 관한 것으로, 특히 다결정실리콘 박막트랜지스터에 사용되는 다결정실리콘을 균일한 막질 및 우수한 특성을 갖도록 형성하는 방법에 관한 것이다.The present invention relates to a method for forming a polysilicon layer, and more particularly, to a method for forming polycrystalline silicon used in a polysilicon thin film transistor to have a uniform film quality and excellent characteristics.
종래 다결정실리콘 박막트랜지스터에 사용되는 활성층인 다결정실리콘층을 형성하는 방법에는 여러가지가 있다. 이중 대표적인 몇가지 예를 들면 다음과 같다.There are various methods for forming a polysilicon layer, which is an active layer used in a conventional polysilicon thin film transistor. Some representative examples are as follows.
먼저, 제1도에 도시한 가장 일반적인 방법인 SPC(Solid Phase Crystallization)방법이 있다.First, there is a SPC (Solid Phase Crystallization) method, which is the most general method shown in FIG.
이 방법은 제1도(a)와 같이 석영 또는 유리와 같은 절연성 기판(1)상에 비정질실리콘(2)을 LPCVD(Low Pressure Chemical Vapor Deposition) 또는 PECVD(Plasma Enhanced Chemical Vapor Deposition)등의 장비를 이용하여 증착한 후, 제1도(b)라 같이 로(furnace)를 이용하여 550℃-800℃로 열처리를 행하여 비정질실리콘층을 다결정실리콘층(3)으로 변화시키는 것이다.In this method, as shown in FIG. 1 (a), an amorphous silicon (2) is deposited on an insulating substrate (1) such as quartz or glass, and equipment such as LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition) is used. After vapor deposition using a furnace, heat treatment is performed at 550 ° C.-800 ° C. using a furnace as shown in FIG. 1 (b) to change the amorphous silicon layer to the polycrystalline silicon layer 3.
제2도에 도시한 방법은 절연성 기판(1)상에 LPCVD나 PECVD에 의해 Si2H6가스나 SiH4가스를 사용하여 직접적으로 다결정실리콘을 증착하는 것이다.The method shown in FIG. 2 is to deposit polycrystalline silicon directly on the insulating substrate 1 using Si 2 H 6 gas or SiH 4 gas by LPCVD or PECVD.
상기한 종래 방법에 있어서, 제1도의 방법은 형성되는 다결정실리콘의 결정입자의 크기가 불균일하고, 그 모양이 덴드라이트(dendrite) 모양을 갖추고 있어 다결정실리콘 박막트랜지스터에 적용할 경우 트랜지스터의 특성(전계이동도, 문턱전압등)의 균일성이 떨어지게 된다.In the above-described conventional method, the method of FIG. 1 has a non-uniform size of the crystal grains of the polysilicon formed and has a dendrite shape, and when applied to a polysilicon thin film transistor, the characteristics of the transistor (electric field Uniformity of mobility, threshold voltage, etc.).
또한, 제2도의 방법은 다결정실리콘층을 형성할때 표면거칠기가 좋지 않아 소자에 적용할 경우 그 륵성이 저하되며, 결정입자의 크기가 작아서 소자의 특성이 나쁘다.In addition, the method of FIG. 2 has a poor surface roughness when forming the polysilicon layer, so that its properties are poor when applied to the device, and the device has poor characteristics due to the small size of crystal grains.
본 발명은 이와 같은 문제를 해결하기 위한 것으로, 막질이 균일하고 우수한 특성을 갖는 다결정실리콘층을 제조할 수 있는 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve such a problem, and an object thereof is to provide a method for producing a polysilicon layer having a uniform film quality and excellent characteristics.
상기 목적을 달성하기 위한 본 발명의 다결정실리콘층 형성방업은 기판상에 SiH4가스를 이용하여 제1비정질실리콘을 증착하는 단계와,상기 제1비정질실리콘층위에 Si2H6가스를 이용하여 제2비정질실리콘을 증착하는 단계, 및 상기 이중구조로 형성된 비정질실리콘층을 열처리하여 다결정실리콘층을 형성하는 단계로 이루어진다.Polycrystalline silicon layer formation of the present invention for achieving the above object is a step of depositing a first amorphous silicon using a SiH 4 gas on a substrate, and using a Si 2 H 6 gas on the first amorphous silicon layer Depositing amorphous silicon, and heat treating the amorphous silicon layer formed of the dual structure to form a polysilicon layer.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제3도에 본 발명의 일실시예에 의한 다결정실리콘층 형성방법을 공정순서에 따라 도시하였다.3 shows a method for forming a polysilicon layer according to an embodiment of the present invention according to the process sequence.
먼저, 제3도(a)와 같이 석영 또는 유리와 같은 절연성 기판(11)상에 SiH4가스를 이용하여 LPCVD에 의해 150Å-3OOÅ정도의 두께로 제1비정질실리콘(12)을 증착한다. 이때, 500℃-600℃에서 증착압력을 0.1Torr-0.5Torr로 하여 SiH4가스를 반응시키면 쉽게 비정질실리콘을 증착할 수 있다.First, as shown in FIG. 3A, the first amorphous silicon 12 is deposited on the insulating substrate 11 such as quartz or glass using a SiH 4 gas to a thickness of about 150 Pa to 300 Pa by LPCVD. At this time, when the SiH 4 gas is reacted at a deposition pressure of 0.1 Torr to 0.5 Torr at 500 ° C. to 600 ° C., amorphous silicon may be easily deposited.
다음에 제3도(b)와 같이 상기 제1비정질실리콘층(12)위에 Si2H6가스를 이용하여 증착온도 420℃-520℃, 반응압력 0.1Torp-0.4Torr의 조건으로 500Å-700Å정도의 두께로 제2비정질실리콘(13)을 증착하여 이중구조의 비정질실리콘층을 형성한다.Next, as shown in FIG. 3 (b), using Si 2 H 6 gas on the first amorphous silicon layer 12, the deposition temperature of about 420 ° C. to about 520 ° C. and the reaction pressure of about 0.1 Torp to 0.4 Torr is about 500 Pa to 700 Pa. The second amorphous silicon 13 is deposited to a thickness of to form an amorphous silicon layer having a dual structure.
이어서 제3도(c)와 같이 상기 이중구조로 형성된 비정질실리콘층을 로(furnace)를 사용하여 550℃-800℃에서 열처리를 행하여 비정질실리콘층을 다결정실리콘층(14)으로 만든다. 이렇게 하면 결정입자의 크기가 균일한 다결정실리콘층을 얻을 수 있으며, 이를 이용하여 다결정실리콘 박막트랜지스터를 제조할 경우, 특성이 균일하고 재현성이 우수한 소자를 형성할 수 있다.Subsequently, as shown in FIG. 3 (c), the amorphous silicon layer formed of the double structure is heat-treated at 550 ° C.-800 ° C. using a furnace to form the amorphous silicon layer 14 as a polysilicon layer 14. In this way, a polycrystalline silicon layer having a uniform crystal grain size can be obtained, and when a polysilicon thin film transistor is manufactured using the same, a device having uniform characteristics and excellent reproducibility can be formed.
다음에 제4도를 참조하여 본 발명의 다른 실시예에 의한 다결정실리콘층 형성방법을 설명한다.Next, a method of forming a polysilicon layer according to another embodiment of the present invention will be described with reference to FIG.
먼저, 제4도(a)와 같이 석영 또는 유리와 같은 절연성 기판(11)상에 Si2H6가스를 이용하여 LPCVD에 의해 증착온도 420℃-520℃, 반응압력 0.1Torr-0.4Torr의 조건으로 400Å-7OOÅ정도의 두께로 제1비정질실리콘(13)을 증착한다.First, as shown in FIG. 4 (a), a deposition temperature of 420 ° C. to 520 ° C. and a reaction pressure of 0.1 Torr to 0.4 Torr are performed by LPCVD on an insulating substrate 11 such as quartz or glass using Si 2 H 6 gas. The first amorphous silicon 13 is deposited to a thickness of about 400 k?
다음에 제4도 (b)와 같이 상기 제1비정질실리콘층(13)위에 SiH4가스를 이용하여 LPCVD에 의해 150Å-3OOÅ정도의 두께로 제2비정질실리콘(12)을 증착한다.Next, as shown in FIG. 4 (b), the second amorphous silicon 12 is deposited on the first amorphous silicon layer 13 with a thickness of about 150 Pa to 300 Pa by LPCVD using SiH 4 gas.
이때, 500℃-600℃에서 증착압력을 0.1Torr-0.5Torr로 하여 SiH4가스를 반응시키면 쉽게 비정질실리콘을 증착할 수 있다.At this time, when the SiH 4 gas is reacted at a deposition pressure of 0.1 Torr to 0.5 Torr at 500 ° C. to 600 ° C., amorphous silicon may be easily deposited.
이어서 제4도(c)와 같이 상기 이중구조로 형성된 비정질실리콘층을 로(furnace)를 사용하여 500℃-800℃에서 열처리를 행하여 비정질실리콘층을 다결정실리콘층(14)으로 만든다. 이렇게 하면 결정입자의 크기가 균일한 다결정실리콘층을 얻을 수 있으며, 이를 이용하며 다결정실리콘 박막트랜지스터를 제조할 경우, 특성이 균일하고 재현성이 우수한 소자를 형성할 수 있다.Subsequently, as shown in FIG. 4C, the amorphous silicon layer formed of the double structure is heat-treated at 500 ° C.-800 ° C. using a furnace to form the amorphous silicon layer 14 as a polysilicon layer 14. In this way, a polycrystalline silicon layer having a uniform crystal grain size can be obtained. When the polysilicon thin film transistor is manufactured using this, a device having uniform characteristics and excellent reproducibility can be formed.
상기와 같이 SiH4가스를 이용하여 형성한 비정질실리콘층과 Si2H6를 이용하여 형성한 비정질실리콘층의 이중구조의 비정질실리콘층을 형성한 후 열처리를 행하면 SiH4-비정질실리콘층에서 먼저 핵생성이 일어나 이 핵으로부터 결정입자가 성장하게 된다. 이렇게 되면 Si2H6가스만 이용하여 비정질실리콘을 증착하고 열처리를 행하여 형성한 다결정실리콘보다 훨씬 우수한 결정입자 크기의 균일성을 갖는 다결정실리콘층을 형성할 수 있다.As described above, after forming an amorphous silicon layer having a double structure of an amorphous silicon layer formed by using SiH 4 gas and an amorphous silicon layer formed by using Si 2 H 6 , and performing heat treatment, a nucleus is firstly formed in the SiH 4 -amorphous silicon layer. Formation occurs and crystal grains grow from this nucleus. In this case, it is possible to form a polysilicon layer having uniformity in crystal grain size that is much better than polysilicon formed by depositing amorphous silicon and heat treatment using only Si 2 H 6 gas.
따라서 본 발명에 의한 다결정실리콘을 이용하여 박막트랜지스터를 제작할 경우, 균일하고 안정된 특성의 소자가 얻어진다.Therefore, when the thin film transistor is fabricated using the polycrystalline silicon according to the present invention, a device having uniform and stable characteristics is obtained.
특히 다결정실리콘 박막트랜지스터-액정표시장치를 제작할 경우,소자특성의 균일성이 매우 중요한데, 본 발명을 적용하여 제작하게 되면 화질이 깨끗하고 신뢰성이 우수한 제품을 제조할 수 있다.In particular, when fabricating a polysilicon thin film transistor-liquid crystal display device, the uniformity of device characteristics is very important. According to the present invention, a product having a clean image quality and excellent reliability can be manufactured.
또한, 본 발명을 적용하여 다결정실리콘 박막트랜지스터를 제작할 경우, 기존방법에 의한 것보다 채널브레이크다운(channel breakdown)특성이 우수한 소자를 제조할 수 있다.In addition, when fabricating a polysilicon thin film transistor by applying the present invention, it is possible to manufacture a device having a better channel breakdown characteristics than the conventional method.
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| KR1019950027192A KR0179139B1 (en) | 1995-08-29 | 1995-08-29 | Method for forming polycrystalline silicon layer |
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| KR1019950027192A KR0179139B1 (en) | 1995-08-29 | 1995-08-29 | Method for forming polycrystalline silicon layer |
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| KR0179139B1 true KR0179139B1 (en) | 1999-04-15 |
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