KR0179035B1 - Thin film semiconductor device and method of producing the same - Google Patents

Abstract

The present invention relates to a method for producing a semiconductor device suitable for a silicon thin film adsorption method, a thin film semiconductor device, an SRAM, and the like at a low temperature of 600 ° C. or less, wherein the semiconductor layer has a refractive index of 4.06 or less with respect to wavelength of 589.3 nm in air And a film having a refractive index of 4.46 or higher for light of 308 nm wavelength in air or a silicon film having an absorption index of 0.81 or less at a wavelength of 404.7 nm.

Description

Thin Film Semiconductor Device and Manufacturing Method Thereof

1A to 1F are cross-sectional views illustrating steps of fabricating a silicon thin film semiconductor device according to an embodiment of the present invention.

2 is a view showing the effect of the present invention when the characteristics of the thin film transistor according to the embodiment of the present invention compared with the characteristics of the prior art.

Figure 3 shows the relationship between the pressure in the reactor and the actual mobility of the thin film transistor to show the effect of the present invention.

4 shows the relationship between the pressure in the reactor and the direction of the silicon film disposed to illustrate the effect of the present invention.

5 shows the relationship between the pressure in the reactor and the crystallinity of the placed silicon film (measured by two methods: Raman spectroscopy and multi-wavelength spectroscopy ellipsometry) to demonstrate the effect of the present invention.

* Explanation of symbols for main parts of the drawings

101 substrate 102 silicon dioxide underlayer film

103: silicon thin film containing impurity 104: source / drain region

105: channel silicon thin film 106: gate insulating film

107: gate electrode 108: source / drain electrode terminal

The present invention relates to a semiconductor device manufacturing method suitable for application to a high quality silicon thin film deposition method, a thin film semiconductor device, an active matrix liquid crystal display, an SRAM, and the like as an insulating material at a temperature lower than 600 ° C.

The screen size of the liquid crystal display and its resolution are increased with the system improvement for driving the liquid crystal display from a simple matrix system to an active matrix system so that a large amount of information is displayed. The active display system allows the formation of a liquid crystal display with thousands of hundreds of pixels and allows for switching transistors to be formed for each pixel. Projection insulating substrates such as, for example, molten quartz plates, glass plates, etc., all that allow projection display information are used as substrates for various liquid crystal displays.

However, when the screen size of the display portion is further increased or the display portion cost is further reduced, it is necessary to use it as a normal insulated substrate glass which is inexpensive. Therefore, there is a need for a technology that enables the formation of a thin film transistor for driving an active matrix system on an inexpensive glass substrate having economical stability and stable characteristics.

Although amorphous silicon or polycrystalline silicon is generally used as an active layer for thin film transistors, polycrystalline silicon showing high operating speed is useful for attempting to form thin film transistors having a driving circuit integrally formed therebetween.

Techniques for forming high quality silicon thin films on insulating materials that allow the use of ordinary glass substrates at temperatures below 600 ° C. are required for thin film semiconductor device formation. This technique is also very useful because it is provided for integration of SRAM and the like and formation of multilayer LSIs. However, the LPCVD polycrystalline thin film is inadequate for semiconductor devices when the conventional low pressure CVD process forms a poor quality silicon thin film having low crystallinity and a good orientation mainly of 220 when deposited below 600 ° C. Therefore, the quality of the silicon thin film is improved in various ways so that the active layer for the thin film semiconductor device can be formed.

Examples of such methods include increasing deposition temperatures for temperatures as close as possible to processing temperatures (610 ° C. to 640 ° C.) and deposition pressures of 40 mtorr to 750 mtorr (Appl. Phys. Lett. 50 (26), P1894 (1987)). Is a method of forming an active layer of a thin film semiconductor device including silicon thin film deposition. Another example includes depositing a silicon film on an insulating substrate by a low pressure CVD process at a temperature below 570 ° C. and heating the film at a temperature below 640 ° C. for 24 hours to change the orientation and crystallinity of the deposited film at that time. A method of improving thin film semiconductor device characteristics (Japanese Patent Application Laid-Open No. 63-307776). Another example of the method is a method of forming an active layer for a thin film semiconductor device comprising depositing an amorphous silicon thin film at a temperature of about 300 ° C. or lower by RF magnetron sputtering or plasma CVD treatment and supplying various laser beams to the film. (Jpn. J. Appl. Phys., 28, P1871 (1989) and Technical Research Report of the Electronic Telecommunications Society EID-88-58).

Problems solved by the present invention

However, the prior art described above has several problems.

The method for improving thin film semiconductor device characteristics by heating the deposited silicon thin film or by supplying a laser beam includes a complicated and tedious production process compared to the method of adopting a low pressure CVD process. This leads to problems of reduced productivity, the need to purchase expensive processing equipment and increased production costs. The silicon film deposition method provided as an active layer by using a conventional low pressure CVD process has a problem that the deposition temperature is considerably high. For example, when a thin film semiconductor device is formed on an inexpensive glass substrate, the highest temperature in production processing is approximately 600 ° C. and the holding time at the highest temperature is limited to several hours or less. When the thin film semiconductor device is supplied to a three-dimensional LSI, SRAM or the like, the thin film semiconductor device is preferably generated at the highest processing temperature of 600 ° C. or less from the viewpoint of protecting the lower layer transistor and the connection portion. In addition, since the conventional LP CVD process forms a silicon thin film having low crystallinity and a direction mainly limited to {220}, LP CVD forming a polycrystalline silicon thin film is not suitable for an active layer of a semiconductor device, NSI is not supplied to LSI, SRAM, or the like, nor used as a switching element for liquid crystal.

Accordingly, the present invention has been made in view of solving the above-described problems, and an object of the present invention is to provide a structure for improving the characteristics of a silicon thin film having properties that can be used as an active layer of a thin film semiconductor device.

It is still another object of the present invention to provide a method for forming a silicon film having good properties by a simple method including only low pressure CVD treatment at a low temperature of 600 ° C. or lower, and at 600 ° C. or lower which the device exhibits good characteristics. It is for manufacturing a thin film semiconductor device having an active layer produced by the LP CVD process.

The above-mentioned object is achieved by a thin film semiconductor device comprising a substrate having a minimum face covered with an insulating material to serve as an active layer for the transistor and a silicon film semiconductor layer formed on one of the sides of the substrate, whereas the semiconductor The layer is a silicon film having a refractive index of 4.06 or less for light of 589.3 nm wavelength in air and a silicon film having a refractive index of 4.46 or less for light of 308 nm wavelength in air or 0.81 or less for light of 404.7 nm wavelength. Silicon films having an extinction index and also silicon films having a crystalline grade of at least 40% as measured by Raman spectroscopy.

When such a silicon film is deposited by a low pressure CVD process, monosilane is used as the source gas, the total reactor pressure is 15 mtorr or less and the partial pressure of silane is 10 mtorr or less.

In the present invention, even when the silicon film is deposited by the LP CVD process at a low temperature of 600 ° C. or lower, the internal pressure of the reactor is 15 mtorr or less, or the partial pressure of the silane is 10 mtorr, so that the film properties such as crystallinity, good directionality, The optical properties and the like are improved, and the formed silicon film is used as an active layer for the thin film semiconductor device so that the properties of the thin film semiconductor device are improved.

Embodiments of the present invention are described below, and the present invention is not limited to the embodiments.

1A to 1F show a polycrystalline silicon thin film transistor production process for forming a MIS type field effect transistor.

In Example 1, (235 mm square) quartz glass is used as the substrate 101. However, any substrate that can withstand temperatures of 600 ° C. is used regardless of the shape and size of the substrate. For example, three-dimensional LSI formed on a silicon wafer is also used as the substrate. In other words, ceramic substrates such as sintered aluminum substrates (Al ₂ O ₃ ), aluminum nitride substrates (AlN), silicon carbide substrates (SiC), graphite substrates, or high melting point metal plates such as tungsten, molybdenum, etc. Is also used as the substrate.

The quartz glass substrate was first submerged in 60% nitric acid seen for 5 minutes and then washed in pure water bubbled by nitrogen gas. When a material such as a metal corroded or degraded with acid is used as the substrate, it is unnecessary to wash the substrate with nitric acid. Another effective method of washing the substrate is a method of washing with an organic solvent such as acetone or MEK (methyl ethyl ketone), followed by pure water depending on ethanol, followed by an aqueous solution containing an organic surfactant or a surfactant containing a silicone. Washing with pure water is included.

A 2000 micron silicon dioxide film (SiO ₂ film) 102 is deposited as a protective underlayer film on a washed quartz substrate by an atmospheric pressure chemical vapor phase deposition process (APCVD process). When one of the various materials is used as the substrate, the SiO ₂ underlayer 102 is required to stabilize the thin film transistor performance including the substrate or the characteristics of the silicon thin film deposited thereafter. In addition, the protective underlayer film 102 is added to the ceramic plate used as the substrate 101 from diffusion and mixing in portions of sodium ions or transistors contained in conventional glass used as the material for the substrate 101. It has the function of preventing flowable ions such as sintering aid material. When a metal plate is used as the substrate 101, the SiO ₂ underlayer film 102 is necessary to ensure insulating properties. Moreover, in the three-dimensional LSI element, the protective underlayer 102 corresponds to the inner layer insulating film between the transistor and the connecting portion. The substrate temperature during the deposition of the SiO ₂ underlayer film 102 is 300 ° C. The SiO ₂ film was deposited by an APCVD process using 20% silane diluted with nitrogen at 600 sccm with 840 sccm oxygen. The deposition ratio of the SiO ₂ film during this treatment is 3.9 s / sec.

The silicon thin film 103 containing the impurity provided as a donor or acceptor is then deposited by a low pressure CVD process. In Example 1, phosphorus is selected as an impurity for the purpose of forming an n-type transistor, but any of the components in Groups V and VI other than phosphorus may be added as an impurity in the case of n-type, Any of components such as boron may be added as impurities in the P-type case. The silicon thin film 103 containing the impurity is a portion forming the source and drain regions. The impurity addition method includes the CVD treatment provided in this Example 1, and forms a unique silicon film containing no impurities and adds impurities by diffusion from a solid phase in contact with the vapor phase or the silicon film, the inherent formed Impurity ion implantation into a silicon film. The use of an impurity addition method, including a method of forming a pure silicon film and diffusing impurities or implanting ionic impurities in the silicon film, allows the impurity to be implanted only in the required portion of the pure silicon film. For example, this enables the production of self-aligned transistors having a gate electrode terminal and a source terminal or a drain terminal of self alignment. It also has parts containing impurities at different concentrations, which makes it possible to form silicon films having different current densities and specific resistances, thereby making it possible to flow only the parts where current is required in the silicon film. In this embodiment 1, phosphorus is selected as an impurity, and the silicon thin film 103 containing the impurity is deposited to a thickness of 1500 kPa by use of a gas containing phosphorus (PH ₃ ) and silane. In Example 1, during deposition, 200sccm monosilane, 6sccm helium-phosphorous mixed gas containing 99.5% helium and 0.5% phosphorus, and at 100sccm helium was passed through a low pressure CVD reactor having a volume of 184.51 L, the deposition The temperature is 600 ° C. and the reactor pressure is 100 mtorr. At the same time, the deposition ratio is 29.6 kW / min, and the instantaneous sheet resistance after film formation is 2.025 kW / square.

A resist is then formed in the silicon thin film, which uses plasma mixing containing boron tetrafluoride (CF ₄ ) and oxygen (O ₂ ) to form source / drain region 104 (FIG. 1B). Is patterned by Impurities such as residual resist and the like are removed by washing which soaks in boiling nitric acid for 5 minutes and the natural oxide film on the source / drain region S 104 is removed by soaking in 1.67% hydrofluoric acid for 20 seconds. Immediately after cleaning, the silicon film provided to the channel portion is formed by a low pressure CVD process.

During deposition, the volume of LP CVD reactor used is 184.51 liters, and the substrate is positioned horizontally near the reactor center. As required, source gases and diluent gases such as helium, nitrogen, argon, hydrogen and the like are directed to the reactor through the lower portion therefrom and consumed through the upper portion therefrom. A heater divided into three zones was attached to the outside of the reactor such that an isothermal zone of desired temperature was formed at the reactor center almost by controlling the three zones separately. The isothermal zone has a length of approximately 350 mm and shows a temperature variation of 0.2 ° C. or less when the temperature is set to 600 ° C., for example. When the spacing between each substrate inserted into the reactor is 10 mm, 35 substrates are handled during one batch. In Example 1, 17 substrates were placed in an isothermal zone at 200 mm intervals.

The evacuation is carried out by the use of mechanical booster pumps connected in series of rotary pumps. With two pumps operating at 600 ° C. reactor temperature, the equilibrium pressure in the reactor is 5.05 mtorr when helium flows at 9 sccm and 25.20 mtorr when helium flows at 74 sccm. Although the equilibrium pressure in the reactor essentially varies linearly within the flow rate range between the values, the deformation in the linear occurs over a wide flow rate range. For example, with the pump operating at 600 ° C., the equilibrium pressure is 56.56 mtorr when helium is generated at 200 sccm and the pressure is 186.04 mtorr when helium is generated at 1 slm. Although the equilibrium pressure varies linearly between a flow rate of 200 sccm and a flow rate of 1 lsm, the pressure that depends on the flow rate is different from the flow rate between 9 sccm and 9 sccm. The pressure is measured by capacitance manometa irrespective of the type of gas.

The substrate has a source / drain region formed therein and a surface without a native oxide film is immediately inserted into the low pressure CVD reactor with the substrate face down. During insertion, the temperature in the reactor is between 395 ° C. and 400 ° C., and the inside of the reactor is maintained in a nitrogen atmosphere. The nitrogen curtain is formed near the reactor inlet by using nitrogen at approximately 6 slm to minimize air flow in the reactor when the substrate is inserted into the reactor.

After the substrate is inserted into the reactor, exhaust and leakage tests are performed. In the case of normal detection, the reactor temperature is increased from the insertion temperature of 400 ° C. to the deposition temperature. In this embodiment, since the silicon thin film provided as the channel portion is deposited at 600 ° C., the time required for the temperature increase is 1 hour. The time for increasing time must change in response to the deposition temperature. For example, 1 hour and 30 minutes are required when the deposition temperature is 630 ° C., and only 35 minutes are required when the deposition temperature is 550 ° C. During the period of temperature rise, the two pumps are operated and occur so that inert or reducing gases with a purity of at least 99.99% continue to flow. Gases of this type are used as inert or reducing gases, including pure gases such as hydrogen, helium, nitrogen, neon, argon, xenon, krypton and the like, and the gases are mixed therefrom. If helium with a purity of 99.9999% occurs continuously at 350 sccm, as in Example 1, the total reactor pressure is maintained at 80.8 ± 1.3 mtorr with an arbitrary level of 95%. In this embodiment, the reactor pressure is 80.95 mtorr during temperature rise.

After the temperature reaches the deposition temperature, the silicon thin film is deposited using a number of predetermined silanes or predetermined mixed gases including silane and diluent gas guided to the reactor as source gas. During the temperature rise it is possible to use the same gas passed as the diluent gas. In any case, the purity of each gas is at least 99.999%. In this Example 1, the silicon thin film was deposited by injecting 99.999% or higher purity silane at 10 sccm without using dilution gas. During deposition, the total pressure in the reactor is 8.54 mtorr. Since the input in the reactor is the sum of the partial pressure of the silane used as the source gas and the partial pressure of the reactant hydrogen, the partial pressure in this Example 1 cannot be accurately determined. Therefore, the partial pressure is estimated approximately from the equilibrium pressure in the reactor when inert helium gas is injected at 10 sccm under the same conditions. In Example 1, the partial pressure of silane evaluated by this method is 5.4 mtorr. In Example 1, the silicon thin film forming the channel portion was deposited to a thickness of 250 mW at a 14.27 mW / min deposition ratio.

The silicon thin film thus deposited is then patterned using a resist and then etched using a plasma mixture containing carbon tetrafluoride and oxygen to form the silicon thin film 105 channel portion (FIG. 1 (c)). ). In Example 1, the deposited silicon thin film was etched using a 15Pa vacuum plasma containing CF ₂ and O ₂ at a 50sccm: 100sccm ratio with a power of 700w at an etching ratio of 7.6 kW / sec. After washing for 20 minutes at 97 ° C. with 96% sulfuric acid and soaking in 60% boiling nitric acid for 30 minutes, the gate insulating film 106 is then deposited by APCVD treatment (FIG. 1 (d)). In this Example 1, a SiO ₂ film was deposited to a thickness of 1,500 kPa while passing nitrogen / silane gas containing 20% silane at 300 sccm and oxygen at 420 sccm at a substrate temperature of 300 ° C. The deposition ratio is 1.85 mW / sec. The refractive index of the film is 1.455 per light wavelength of 6328 kHz and the rate of etching at 25 ° C. with an aqueous hydrofluoric acid solution of 167% is 21.3 Å / sec.

Then, the thin film serving as the gate electrode 107 is deposited by sputtering deposition or CVD processing or the like. In this embodiment 1, even though indium tin oxide (ITO) was selected as the material for the gate electrode and deposited at 2600 μs by sputtering a metal material such as aluminum or chromium, a silicon film, a silicon metal compound, or the like was deposited on the gate electrode. It can be used as a substance for. After the thin film serving as the gate electrode is deposited, the gate electrode is formed (FIG. 1 (e)), and then the contact hole is opened in the gate insulating film. The source and drain take off electrodes are then formed by sputtering to complete the transistor (FIG. 1F).

2A to 2D illustrate an example of the V _GS −I _ds curve of the sample thin film transistor TFT formed by the above-described method. In the figure, I _ds is the source / drain current and V _GS is the gate voltage. The properties were measured at source / drain voltage V _ds = 4 {V} and at a temperature of 25 ° C. The transistor channel portion has a length L of 10 mu m and a width of 10 mu m. The on current I _ds flowing when the transistor is turned on is 1.32 [μA] while V _GS = 4 [V] and V _GS = 10 [V]. Current I _ds off at least I _ds is 0.12 [pA] at V _ds = 4 [V] and V _GS = -3.5 [V]. The thin film transistor obtained has good characteristics with an on / off ratio of more than seven times the size. The efficient electron mobility obtained in the saturation current region of the transistor is 3.9 [cm ² / vs].

The thin film transistor is formed in the same process as used in Example 1 except for depositing the channel portion silicon thin film. In Example 2, when the channel silicon film was deposited, the time required to increase the temperature was 1½ hours and helium of 99.9999% purity was continuously passed at 350 sccm during the temperature rise. The silicon thin film is deposited at 250 μs at a silane implantation rate of 150 sccm without the deposition temperature of 630 ° C. and the use of dilution gas. During the deposition, the pressure in the reactor was 49.2 mtorr and the partial pressure of silane evaluated by the use of helium instead of silane was 73.4 kPa / min. This example 2 corresponds to the prior art. 2B of FIG. 2 show V _GS -I _ds characteristics of the sample thin film transistor formed by the above-described method. The size and measurement conditions of the transistors are the same as those used in Example 1. In Example 2, the on current I _ds is 0.12 [μA], the off current I _ds is 0.15 [pA] and the on / off ratio is less than six times the magnitude. The effective electron mobility determined in the saturation current region of the transistor is 2.4 cm ² / vs}.

When a silicon film is deposited by a low pressure CVD process to form a channel for the transistor, the silicon film is generally at a high temperature of 630 ° C. or higher in the prior art, since the higher the deposition temperature, the more the transistor characteristics are improved. Is deposited. However, compared with the results obtained in Example 1, which is one embodiment of the present invention, and those obtained in Example 2, which correspond to the prior art, when the silicon thin film channel portion is deposited by a low pressure CVD process, the voltage and 5.4 in the reaction of 8.54 mtorr are deposited. The thin film transistor having the main part with the silicon thin film deposited at the silane partial pressure of the mtorr has a high performance even though the deposition temperature is as low as 600 ° C. compared with Example 2 which corresponds to the prior art where the deposition temperature is 630 ° C. Shows.

The thin film transistor is formed by the same process as used in Example 1 except for depositing a silicon thin film channel portion. In Example 3, when the silicon thin film channel portion is deposited, the time required to increase the temperature is 1 hour and helium of 99.9999% purity is continuously passed at 350 sccm during the temperature rise. The silicon thin film channel portion is deposited at a deposition temperature of 600 ° C. and a silane implantation ratio of 10 to 70 sccm at 15 sccm intervals.

The channel region used for the thin film transistor is 250 kW thick. FIG. 3 is a diagram of the results of efficient electron mobility (determined from the saturation current region) of each thin film transistor obtained by the method described above as a function of pressure in the reactor. Table 1 shows the silane partial pressure, deposition rate and efficient electron mobility for each sample as assessed by using helium instead of silane. The errors shown in FIG. 3 and Table 1 are interval evaluations with 95% confidence levels.

As shown in Table 1 or Figure 3, when the pressure in the reactor is less than 15 mtorr or the silane partial pressure is 10 mtorr or less, efficient mobility, such as sample numbers 3-4 or 3-5, is improved to 40% or more. And a transistor having good characteristics can be obtained.

The thin film transistor is formed by a process as used in Example 1 except for depositing a channel portion silicon thin film. In Example 4, the time required to raise the temperature when the channel portion silicon thin film was deposited was 1 hour and helium having a purity of 99.9999% or more was continuously passed at 350 sccm during the temperature rise time. The channel portion silicon thin film was deposited to a thickness of 250 에 for the thin film transistor by using 40 sccm of silane diluted to 700 sccm of helium at a deposition temperature of 600 ° C. During deposition, the total pressure in the reaction chamber was 146.4 mtorr. The calculated silane partial pressure was 7.81 mtorr using the Dalton's law for partial pressure. The deposition rate was 24.7 dl / min. The effective electron mobility determined from the saturation current region of the thin film transistor is 3.77 [cm /v.s]. Comparison of sample 3-3 of Example 3 with sample 4 of Example 4 shows that when the silane partial pressure is 10 mtorr or lower due to the use of diluent gas, the effective mobility is 15 mtorr or higher in the reaction chamber. Even in this case, it has been improved by about 50%, showing that good flexibility as a transistor can be obtained.

An SiO lower layer film was formed on a quartz glass substrate and one quartz silicon substrate. Then, a silicon film was formed on the lower layer film. Then, the components of the silicon film were examined. The quartz glass used as the substrate had a diameter of 75 mm and a thickness of 1.2 mm. The single crystal silicon wafer had an orientation of 100 and was doped with phosphorus, resulting in an n-type semiconductor. The resistivity of the wafer was 3.0 kcm. Each substrate was soaked in 60% boiling nitric acid for 5 minutes to remove contamination from the substrate surface and again 5% aqueous solution of hydrofluoric acid for 10 seconds to remove the native oxide film formed on the surface of each substrate. Was bathed in. Immediately after washing, a 2,000 micron SiO underlayer film was deposited by the APCVD process. The deposition conditions are the same as in the case of depositing the SiO lower layer film 102 in the first embodiment.

Each substrate was then heated in a nitrogen atmosphere at 600 ° C. for 2 hours. Properties such as refractive index, etching rate, and the like and the thickness of the SiO film formed by the CVD process were changed by subsequent heat treatment. Changes in the properties of the SiO underlayer film affect the properties of the silicon film deposited thereon. In Embodiment 5, heat treatment for heat generation applied to the SiO lower layer film is performed when the silicon thin film 103 containing the impurity is formed. In this manner, the channel portion silicon film is deposited under the same conditions as in the case of forming the channel portion silicon film in Examples 1 and 3.

Each substrate was then immersed in boiling nitric acid for 5 minutes and again in an aqueous solution of 1.67% hydrofluoric acid for 20 seconds to clean the surface of SiO. At the time of bathing, approximately 400 Pa of SiO film was removed. After each substrate was washed with pure water bubbled with nitrogen for 15 minutes and dried in a spin dryer, a silicon film was deposited on the SiO underlayer film by a low pressure CVD process. This deposition was performed by a low pressure CVD apparatus such as that used to deposit the channel silicon film in Example 1. In Example 5, when a silicon wafer was used as the substrate, a silicon film was deposited under the same conditions as those used in Examples 3 and 4. That is, after the substrate was inserted into the reactor maintained at a temperature of 390 ° C. to 400 ° C., the temperature in the reactor was raised to a deposition temperature of 600 ° C. over 1 hour. During the period in which the reactor temperature rose to a deposition temperature of 600 ° C., a mechanical booster pump and a rotary pump were operated, and helium with a purity of 99.9999% or higher was passed at 350 sccm. The silicon film was deposited in such a manner that the silane flow rate was set from 10 sccm to 70 sccm at an interval of 15 sccm without using diluent gas under the same conditions as used in Example 3 and at 40 sccm under the same conditions as used in Example 4 The silane was deposited in such a way that it was diluted with 710 sccm of helium. The thickness of each of the deposited films was 250 kPa. In Example 5, when a quartz glass plate was used as the substrate, a silicon film was deposited under the same conditions as in the case where the silicon wafer was used as the substrate except for the method of raising the thickness and temperature of the deposited film. In Example 5, when a quartz glass plate was used as the substrate, the films deposited under the above conditions were 5,000 kPa ± 250 kPa, 1000 kPa + 50 kPa and 1370 kPa + 30 kPa. Before each silicon film was deposited, the temperature of the reactor rose from 400 ° C. to 600 ° C., while passing through nitrogen having a purity of at least 99.99% at 900 sccm, while maintaining the pressure of the reactor at about 160 mtorr. The crystallographic orientation in the direction perpendicular to the substrate surface in each of the silicon thin films deposited under the various conditions was examined by X-ray diffraction. In other words, the volume ratio of orientation in each direction was determined from the measured X-ray diffraction intensities, and compared with the ratio of the diffraction intensities of the completely randomly oriented silicon powder. Planar imbalances were also compared. In such a measurement, the thickness of each film was 5000 mm ± 250 mm. Crystals of silicon thin film samples with thickness of 1000Å ± 50Å were calculated by laser RAMAN spectroscopy, and the crystals of silicon thin film samples with thickness of 1370Å ± 30Å and 250Å, respectively, were multi-wavelength polarization analyzer (multi-wavelength spectroscopic ellipsome Tri, MOSS-ES4G manufactured by Sopra, France). In laser RAMAN spectroscopy, 830 (cm ) To 108 cm Scanning is performed in the region of < RTI ID = 0.0 > Raman scattering integrated intensity IC at) and about 130 cm Acoustic Vertical Waveform Mode (TA) Approx. 290 cm Acoustic horizontal waveform mode (LA) at approx. Optical horizontal waveform mode (LA) and approx. 480 cm The crystals were determined from the relative ratios between the sum Ia of the scattering integration intensities of amorphous silicon, including the optical vertical waveform mode (TO), in which the frequencies were determined by amorphous silicon (Appl. Pys. Lett., 40 (6). 534 (1982).

That is, the crystallinity P was calculated by the following equation.

σ = Ic / (Ic + Ia)

0.08 was used as the correction factor K for scattering the integrated strength. In the multi-wavelength elliptical polarization method, scanning was performed using a rotating polarizer in the wavelength range of 250 nm to 850 nm. The incident angle was 70 degrees. The spectra of tanρ and cosΔ were obtained. The pre-measured spectrum of amorphous silicon and that of crystalline silicon is determined by the desired size ratio between amorphous silicon and crystalline silicon in accordance with DBR BRUGGEMAN, Ann. Phys. (Leipzig) 24,636 (1935). The crystallinity was determined by the mixing ratio by the magnitude of the resulting spectra that best matches the measured spectra.

4 shows the pressure relationship between the planar anisotropy of the reactor and the silicon thin film obtained by the LP CVD process. In the reactor only the flow rate of silane was changed from 10 sccm to 70 sccm. The pressure generated in the reactor is shown on the abscissa of FIG. Silicon films were deposited at pressures far below the 40 mtorr to 750 mtorr used in conventional low pressure CVD processes. It can be seen from FIG. 4 that the reflection can be obtained completely from the {220} plane at a total pressure of about 20 mtorr, while the reflection from the {111} plane becomes stronger at a total pressure of 15 mtorr or less. The partial pressure of the silane obtained using helium instead of silane and the pressure between the reactors are shown in Table 1 of Example 3. The silane partial pressure corresponding to the total pressure of 15 mtorr at which the planar anisotropy is changed is 10 mtorr. Another silicon thin film was deposited in the same manner as described above using 40 sccm silane diluted with 710 sccm helium. The total pressure of the reactor during the deposition was 146.4 mtorr and the silane partial pressure calculated using Dalton's law of partial pressure was 7.81 mtorr. In terms of plane anisotropy, the orientation of the {111} plane in this thin film was 0.279 and the orientation of the {220} plane was 0.646. Thus the orientation of the {111} plane is compared to the orientation of 0.021 in the {111} plane when deposited at a total reactor pressure of 21.1 mtorr and a silane flow rate of 40 sccm without any dilution as shown in FIG. It has been found that this can be increased by reducing the silane partial pressure from 10 mtorr to below.

FIG. 5 shows the degree of crystallinity of a 1.370 micron thick sample measured by multi-wavelength elliptic polarization and a 1,000 micron thick sample measured by laser Raman spectroscopy. Since the two methods have different measurement principles, degrees of crystallinity and thicknesses, the absolute values differ from one another. However, FIG. 5 shows a stepwise change in the degree of crystallinity at the total reactor pressure of 15 mtorr or the silane partial pressure of 10 mtorr. The crystallinity measured by Raman spectroscopy was 41.0% when the silicon thin film was prepared by using 40sccm silane diluted with 710sccm of helium such that the silane pressure was 7.81mtorr. It was%.

Therefore, in order to produce a silicon thin film having an orientation or high crystallinity, which is mainly {111} suitable by low pressure CVD process at a low temperature of 600 ° C. or lower, the total reactor pressure is reduced to 15 mtorr or less, or the silane partial pressure is 10 mtorr. Or less.

The refractive index and absorbance of the silicon thin film formed on SiO of the silicon wafer used as the substrate were measured by multiple spectroscopic ellipscopy (MOSS-ES4G manufactured by Sopra Co, LTD, France). In Example 5, the silicon thin film was deposited under the same conditions as those in which the channel silicon film was deposited to form the transistors in Examples 3 and 4, and the thickness of the thin film was 250 [mu] s within an error range. The thickness interval quantification including the measurement error is 5.2 kV with a 95% confidence level. In other words, the characteristics of the same silicon film having a thickness of 250 kPa were examined in terms of transistor characteristics of the silicon film in Examples 3 and 4 and in terms of optical properties of the silicon film in Example 5. Table 2 shows the index of refraction for 589.3 nm light in air, the index of refraction for 308 nm light in air, and the absorbance for 404.7 nm light of a silicon film having a thickness of 250 Hz, all of which are described above. Measured by law. The crystallinity of a silicon film having a thickness of 1000 μs, also determined by Raman spectroscopy, along with the total reactor pressure and silane partial pressure for each sample, and the effective mobility as shown in Examples 3 and 4 are shown. From Table 2, it can be seen that the effective mobility is significantly improved when a silicon film having a crystallinity of about 40% as measured by Raman spectroscopy is used in the channel portion of the transistor. In addition, a silicon film having a refractive index of 4.06 or less for light of 589.3 nm in air, a refractive index of 4.46 or more for light of 308 nm in air, or 0.81 or less for light of 404.7 nm in the air is a channel portion semiconductor layer. It can be seen that the effective mobility can be significantly improved when used at.

As described above, according to the present invention, a thin film semiconductor device including a substrate having a surface coated with an insulating material and a silicon film formed on the substrate to act as an active layer can be manufactured. Here, the mobility can be improved by adjusting the crystallinity and the optical properties of the silicon film. When a good silicon film with the {111} direction is placed in a low pressure CVD process, the total pressure in the reactor is 15 mtorr or less, and the silicon partial pressure is 10 mtorr or less. According to the present invention, a thin film semiconductor device having good transistor characteristics can be produced and the present invention has the effect of increasing the performance and thus reducing the cost of an active matrix liquid crystal display in which thin film transistors are used by making and integrating LSI multilayers. have.

Claims (4)

A thin film semiconductor device comprising a substrate having at least a surface covered with an insulating material and a silicon film semiconductor layer formed on one of the sides of the substrate to provide an active layer of the transistor, wherein the semiconductor layer is exposed to light at a wavelength of 589.3 nm in air. A thin film comprising a silicon film having a refractive index of 4.06 or less, and a silicon film having a refractive index of 4.46 or more for light having a wavelength of 308 nm in air, or a silicon film having an absorption index of 0.81 or less at a wavelength of 404.7 nm. Semiconductor device. A thin film semiconductor device comprising a substrate having at least a surface covered with an insulating material and a silicon film semiconductor layer formed on one of the sides of the plate to provide an active layer of the transistor, wherein the semiconductor layer is measured when measured by a Raman spectrometer. A thin film semiconductor device comprising a silicon film having a crystallinity size of at least% reached. A method of fabricating a thin film semiconductor device comprising forming a silicon film semiconductor layer on one of the sides of a substrate having at least a surface covered with an insulating material such that the semiconductor layer is provided as an active layer of the transistor, the total reactor pressure of 10 mtorr or less. And depositing the silicon film by low pressure chemical vapor deposition (LP CVD) using monosilane (SiH ₄ ) as the source gas at the silane partial pressure below. Silicon films having a crystallinity size reaching 40% or more as measured by Raman spectroscopy or silicon films having a good {111} orientation mainly by low pressure chemical vapor deposition (LP CVD) at low temperatures below 600 ° C. A silicon thin film deposition method comprising: depositing a silicon thin film using monosilane (SiH ₄ ) as a source gas at a total reactor pressure of 15 mtorr or less or a silane partial pressure of 10 mtorr or less.