KR0177106B1 - Moire clear circuit for display device - Google Patents

Abstract

The present invention improves the method of compensating moiré by changing the input signal (V_Sync) of the vertical amplifier, thereby clearing the moiré phenomenon by shaking the vertical center at the rear end of the vertical amplifier, that is, the vertical deflection yoke end. It is about a circuit.

The moiré clear control unit 70 generates a pulse twice the vertical period by triggering the vertical synchronizing signal, and is turned on / off according to the output signal of the moiré clear control unit 70 and flows in the vertical deflection coil V_DY. A switching transistor Q2 for determining the direction of the current, a current controller 80 for adjusting the current flowing through the switching transistor Q2, and a current flowing through the switching transistor Q2 are coupled to a vertical output circuit terminal. It includes a vertical center control circuit 60 for ringing and moiré phenomena by changing the moiré clear operating voltage when the moiré clear pulse turns the switching element on or off at a rate ½ times the vertical period. Clearing, the current flowing through the switching element is adjusted according to the change of the output voltage of the comparator (OP1) and finally the moiré noise attenuation amount can be adjusted Have.

Description

Moire clear circuit of display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to attenuate the moiré phenomenon by shaking the vertical center at a speed of twice the vertical period, and to reduce the interference by moiré clear by toggling the moiré clear enable state. Moiré clear circuit of a display device.

In general, color monitors, unlike mono monitors, are subject to limitations due to shadow masks and dot screens.

This applies to slitted screens and Trinitrons in addition to the dot method, but the results are different. This is because the screen structure is divided.

Moiré is a grain or wavy phenomenon caused by the interference between the shadow mask and the scanning pattern, which is caused by the limitation on the beam size.

In other words, when a beam passes through a shadow mask matrix of a cathode ray tube (hereinafter referred to as a CRT), interference occurs, and a moiré phenomenon occurs on the screen in a display mode of a specific frequency. Caused discomfort.

The prior art regarding moire clear to solve this inconvenience is disclosed in US Patent 5,107,188 and the circuit is shown in FIG.

The first NOR gate NOR1 receives and inverts the video synchronization signal through both input terminals, and the synchronization signal is delayed by the resistor R1 and the capacitor C1, thereby delaying the second NOR gate NOR2 and the third NOR. It is input to the gate NOR3. At this time, the output signal of the first NOR gate NOR1 is transmitted to the clock terminal of the counter IC, which is composed of a D flip-flop, and the Q (Q-bar) output terminal of the counter IC is a D input terminal ( Data input), and toggles the high or low logic signal to the Q output.

The Q (Q-bar) output terminal of the counter IC is connected to the other input terminal of the second NOR gate NOR2, and the Q output terminal is connected to the other input terminal of the third NOR gate NOR3.

In addition, the output signal of the second NOR gate NOR2 is transmitted to the fourth NOR gate NOR4 through the resistor R2 and the capacitor C2, and the output signal of the third NOR gate NOR3 is the variable resistor VR1. And a capacitor C3 to the other input terminal of the fourth NOR gate NOR4.

At this time, the delayed synchronization signal is output from the output terminal of the fourth NOR gate NOR4.

FIG. 2 shows waveforms of input and output signals of each part of FIG. 1.

(A) is a pulse in which the synchronization signal inverted by the first NOR gate NOR1 is transferred to the clock stage of the counter IC, and (B) is a D input terminal and Q (Q) of the counter IC. -bar) represents the pulse transmitted from the output terminal to one input terminal of the second NOR gate Mor2, and (C) represents the pulse transmitted from the Q output terminal of the counter IC to one input terminal of the third NOR gate NOR3. have.

In addition, (D) represents a pulse to which the synchronization signal delayed via the resistor R1 and the capacitor C1 is applied to the input terminal of the second NOR gate NOR2, and the two signals (B) and (D) 2 Input to NOR gate (NOR2) and appear as shown in (E). Depending on the nature of the NOR gate, the output signal is output high when both input signals are low, otherwise the output is low Indicates a signal.

On the other hand, a delayed synchronization signal through the RC filter is input to one input terminal of the third NOR gate NOR3, and an output signal of the Q output terminal of the counter IC is transmitted to the other input terminal as (C). do.

The two signals (C) and (D) are input to the third NOR gate (NOR3) and appear as shown in (F). As in the case of the second NOR gate, only when the two input signals are both in the low state. The output signal is output high.

(E) and (F), which are output signals of the second and third NOR gates NOR2 and NOE3, are respectively passed through the resistors R2 and VR1 and the capacitors C2 and C3, respectively. Is passed to the two inputs.

At this time, the output signal of the fourth NOR gate NOR4 may appear as (H) or (I), and (I) indicates that the signal delayed according to the adjustment of the variable resistor VR1 according to the user's operation. As input, both (E) and (F) change the width of the output signal representing the high logic when it is low. That is, the time constant of the output signal of the third NOR gate changes according to the change of the variable resistor VR1, and the time applied to the fourth NOR gate is delayed than the time applied to the fourth NOR gate. As a result, the delayed synchronous output signal results in the electron beam being phase shifted on the surface of the cathode ray tube.

As described above, the center of the vertical synchronization signal is continuously delayed left and right as the most convenient method of causing vertical interference, and the vertical amplifier is operated by synchronizing the vibration of the vertical signal, resulting in the vertical center shaking.

However, such a conventional moiré clear circuit has a problem in that a circuit for delaying a vertical synchronization signal is complicated and the vertical synchronization is broken when the circuit malfunctions.

An object of the present invention to solve this problem is to provide a moiré clear circuit that can be applied to the vertical center circuit pulses twice the vertical period, the user can adjust the amount of interference.

The present invention for achieving this object is connected to the vertical deflection coil (V_DY) of the vertical output circuit, the vertical center control circuit for determining the direction of the current flowing through the vertical deflection coil (V_DY) and according to the user's moire clear intention Moiré that triggers the vertical synchronization signal to be input and outputs the output signal of one cycle to two cycles of the vertical synchronization signal to turn on / off the signal applied to the vertical center control circuit. And a current control unit connected to the clear control circuit and the vertical center control circuit and the moire clear control circuit to control the amount of current flowing through the vertical center control circuit.

1 is a circuit diagram showing the configuration of a conventional moire clear circuit;

2 is a signal waveform diagram shown in each part of FIG. 1;

3 shows a configuration of a vertical deflection circuit portion according to the application of the present invention.

Block Diagram,

4 is a circuit diagram of a moire clear circuit of FIG. 3 in detail;

5 is a waveform diagram of each part of FIG. 4.

Hereinafter, the configuration and operation of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram showing the configuration of a vertical deflection circuit portion according to the application of the present invention.

As shown, the microcomputer 10 receives a vertical synchronizing signal transmitted through a video cable connected to a computer and outputs a predetermined DC voltage corresponding to the vertical frequency, and the output voltage of the capacitor using the output voltage of the microcomputer 10. The vertical oscillation circuit 20 generating the sawtooth wave by charging and discharging, the vertical output circuit 40 using the mirror integration to make the deflection current having excellent linearity, and the midpoint voltage of the vertical output circuit 40 A deflection yoke for controlling the distance or speed at which the electron beam reaches the shadow mask by forming a magnetic field by flowing a current provided from the vertical output circuit 40 and the vertical drive circuit 30 to maintain a constant ( 50) and a direct current superimposed on the deflection yoke 50 (V_DY) to adjust the vertical center of the displayed image by changing the magnitude and direction of the direct current. A vertical center control circuit 60, a moiré clear control circuit 70 that attenuates moiré phenomena by adjusting the operation period of the vertical center control circuit 60 by a period twice the vertical synchronization signal, and the vertical It is connected to the center control circuit 60 and the moire clear control circuit 70 is configured to include a current control unit 80 for controlling the amount of current flowing in the vertical center control circuit 60.

4 is a circuit diagram illustrating in detail the vertical output circuit 40, the vertical center control circuit 60, the moire clear control circuit 70 and the current control unit 80 of FIG.

The vertical output circuit 40 receives a vertical output ramp waveform to the inverting terminal, receives an operating voltage V1 from the inverting terminal, and amplifies the vertical output amplifier U1 and the output voltage of the output amplifier U1. An applied deflection yoke V_DY, a capacitor C1 and a resistor R1 connected in series thereto.

The moiré clear control circuit 70 receives the vertical synchronizing signal V_SYNC through the clock terminal CK, and the moiré clear enable / disable control signal transmitted according to the user's intention to the clear terminal CL. A flip-flop U2 for generating one output pulse per two periods of the vertical synchronization signal to the output terminal Q, and resistors R4, R5, and R6 for dividing and delivering the output signal of the flip-flop U2. It is configured by.

At this time, the output signal of the moire clear pulse generation circuit 70 is divided by the resistors R4, R5, and R6 and applied to the base terminal of the switching transistor Q2.

The vertical center control circuit 60 includes a resistor R2 for transmitting a vertical center control signal to the deflection yoke V_DY and the capacitor C1, and an output of the collector terminal of the switching transistor Q2 to the resistor R2. The optocoupler OPT1, which is a coupling element for changing the direction of the current flowing by changing the level of the potential applied to the vertical deflection coil by receiving a voltage, is connected. Such a coupling device may have the same effect by using a transformer or ASIC coupling the base of the switching transistor Q2.

The output terminal of the comparator OP1 for controlling the current flowing through the switching transistor Q2 is connected to the emitter terminal of the switching transistor Q2 through the resistor R7.

A resistor R8 for transmitting the reference voltage V2 is connected to the inverting terminal (-) of the comparator OP1, and a capacitor C2 is connected between the inverting terminal (-) and the output terminal, and the non-inverting terminal (+). Resistors R9 and R10 for dividing and transferring the moiré clear operation voltage transmitted from the microcomputer (not shown) are connected.

The moire clear circuit according to the present invention having such a configuration is operated as follows. The moire clear pulse generation circuit 70 enables the flip-flop U2 to generate an output signal for controlling the on / off operation of the switching transistor Q2. The flip-flop U2 is operated by triggering the vertical synchronizing signal V_SYNC, and the signal of the output terminal Q of the flip-flop U2 is displayed as high or low according to the vertical period.

When the signal applied to the clear terminal CL of the flip-flop U2 is an enable signal, the speed is ½ times the period of the vertical synchronization signal V-sync input to the clock terminal CK, that is, the vertical pulse. When the switching transistor Q2 is turned on / off at the speed of outputting one pulse while two are inputted, the moiré clear operating voltage Moire Adjust, that is, the voltage applied to the non-inverting terminal (+) of the comparator OP1 By changing the moiré attenuation can be adjusted.

The flip-flop U2 at this time is a D-type flip-flop and represents an output signal that is toggled at an edge portion at which the input signal changes from a low state to a high state.

The vertical synchronizing signal V_SYNC input to the clock terminal of the flip-flop U2 appears as shown in FIG. 5A, and is located at the points ①, ②, and ③ where the rising edges of the vertical synchronizing signal are located. The output signal of the flip-flop U2 is output at a period of ½ times the vertical period by being toggled at the points (① ', ②', ③ ').

In addition, a moiré clear enable / disable toggle signal is transmitted to the clear stage CL of the flip-flop U2, and the moiré clear circuit is in an enabled state. This is to receive a selection signal so that the user can enable or disable the moiré clear circuit because a low image frequency may occur when the vertical frequency is low.

At this time, the collector voltage of the transistor Q2 is changed by the DC voltage applied to the base end of the transistor Q2, and the controlled current changes the potential level through the optocoupler OPT1 to vertically center the vertical output. Allow it to change at ½ times the cycle.

In addition, the current flowing through the switching transistor Q2 is controlled by the comparator OP1, and the current flowing from the emitter stage to the collector stage as the bias voltage of the emitter stage of the transistor Q2 varies according to the output signal of the comparator. Will control the amount of.

The selection signal may be realized by a selection switch provided at an external portion of the display device or a switching element capable of generating an electrical signal, and may use a predetermined key of a generally used remote control.

When the moiré clear pulse turns the switching element on or off at the rate of ½ times the vertical period, the moiré clear operation voltage is changed to clear the moiré phenomenon and change the output voltage of the comparator OP1. Accordingly, the current flowing through the switching device is adjusted, and thus, the moiré noise attenuation amount can be adjusted.

Claims (4)

Triggering the vertical sync signal to generate pulses ½ of the vertical period. Moire clear adjustment unit 70, A switching transistor Q2 that is turned on / off according to the output signal of the moiré clear adjusting unit 70 and determines a direction of a current flowing in the vertical deflection coil V_DY; A vertical center control circuit 60 for coupling a current flowing through the switching transistor Q2 to a vertical output circuit stage; Moiré clear circuit of the display device including a current amount adjusting unit for adjusting the current flowing through the switching transistor (Q2). The method of claim 1, The moiré clear pulse generating unit 70 includes a flip-flop U2 whose output is varied according to a vertical period input by receiving a vertical synchronous pulse to the clock terminal and receiving a moiré clear enable signal to the clear terminal. Moire clear circuit of the display device characterized by the above-mentioned. The method of claim 2, And a moiré clear enable / disable control signal is input to the clear end of the flip-flop (U2). The method of claim 1, The vertical center control circuit (60) is a moire clear circuit of the display device, characterized in that it comprises an optocoupler (OPT1) is switched depending on whether the switching element is turned on.