KR0175563B1 - Clock line check device of I2C bus - Google Patents

Abstract

The present invention relates to an I ² C bus clock line check apparatus for checking whether a clock line is abnormal on an I ² C bus by using a timer, and a data line (SDA) and a clock line (SCL) of an I ² C bus A start and end condition detecting means (100) for detecting a start and end condition indicating a start and end condition of data transmission by detecting a signal transmitted through the start and end condition of data transmission; A CPU (200) for controlling the state of the clock line according to a signal output from the start and end condition detecting means (100); And the CPU 200 senses the state of the clock line SCL of the I ² C bus and interrupts the CPU 200 if the state of the clock line SCL is maintained for a predetermined period or longer And a clock line state detecting means 300 for outputting the clock line state.

Therefore, the present invention has an effect of improving transmission efficiency by preventing an error of transmission data and restoring a clock line by preventing an operation of a clock line by checking an abnormal state of a clock line on an I ² C bus.

Description

Clock line check device of I2C bus

The present invention relates to a clock line of the I ² C bus checking device that checks the presence of error in the clock on the line I ² C bus.

Generally, the I ² C bus is a data line used for data transfer between each part (A, B, C, and D), for example, a CPU, a memory, and an I / O device as shown in FIG. Two lines transmitting data and clock, respectively. Devices connected to the I ² C bus are also software accessible and multiple masters can be on the same bus at the same time. In other words, each part (A, B, C, D) connected to the I ² C bus can become a master when a clock is generated.

For example, when a part A generates a clock and becomes a master, the remaining parts B, C, and D become slaves. When the other part B generates a clock and becomes a master, C and D becomes a slave and another part C generates a clock and becomes a master, the remaining parts A, B and D become a slave and another part D generates a clock When it becomes master, the remaining parts (A, B, C) become slave.

In addition, the I ² C bus can transmit data from 100 Kbps to 400 Kbps, so that multiple devices (A, B, C, and D) can be connected to the same bus as long as the capacitor does not exceed 400 pF.

The I ² C bus consists of two lines: one data line (SDA) for transmitting data and one clock line (SCL) for transmitting the clock. Therefore, when the master transmits the clock through the clock line SCL, the slave transmits or receives data through the data line SDA in synchronization with the clock transmitted through the clock line SCL.

However, a stuck phenomenon may occur in the clock line (SCL) of the I ² C bus due to a noise or a state of a master or a slave. That is, there may be a case where the state of the clock line is not normal due to the noise or the state of the master or the slave.

In particular, since the I ² C bus is wired AND, when the state of the master or the slave is '0', it is difficult to transmit clocks to the I ² C bus, thereby causing a transmission error.

Present invention to improve the above problems by using a timer, I ² C bus to check the status of the clock line and the clock line of the I ² C bus for allowing the clock line of the I ² C bus is always to be a normal operation check The purpose is to provide a device

FIG. 1 is a schematic diagram of a general I ² C bus. FIG.

FIG. 2 is a block diagram of a clock line checking apparatus according to the present invention; FIG.

FIG. 3 is a signal waveform diagram for explaining a start condition and a termination condition; FIG.

FIG. 4 is a flow chart for explaining the operation of the present invention; FIG.

FIG. 5 is a detailed configuration diagram of the start and end condition detection unit of FIG. 2; FIG.

FIG. 6 is a detailed configuration diagram of a clock line checking unit of FIG. 2;

DESCRIPTION OF THE REFERENCE NUMERALS

100: start and end condition detection unit 200: CPU

300: clock line state detection unit 310: clock line check unit

320: Timer 330: Internal clock generator

331: Prescaler 332: Oscillator

335: I ² C controller 410, 420, 430, 450, 530: comparator

440: inverter 510, 520: flip-flop

The present invention relates to a clock line of the I ² C bus checking device that checks the presence of error in the clock on the line I ² C bus.

In order to achieve the above object, an I ² C bus clock line checking apparatus according to the present invention detects a signal transmitted through a data line and a clock line of an I ² C bus, Start and end detection means for detecting a condition; A CPU for controlling the state of the clock line according to a signal output from the start and end condition detection means; And a clock line state detecting unit for detecting a state of a clock line of the I ² C bus under the control of the CPU and outputting an interrupt to the CPU when the clock line maintains a predetermined state for a predetermined period or longer .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The apparatus for checking the clock line of the I ² C bus according to the present invention includes a start and end condition detecting unit 100, a CPU 200, a clock line state detecting unit 300, and an I ² C controller 335).

The start and end condition detection unit 100 detects a signal transmitted through the data line SDA and the clock line SCL of the I ² C bus and detects start and end conditions indicating the start and end states of data transmission.

The CPU 200 controls the state of the clock line according to a signal output from the start and end condition detector 100. [

The clock line state sensing unit 300 senses the state of the clock line SCL of the I ² C bus under the control of the CPU 200 so that the clock line SCL maintains a constant state for a predetermined period of time to output the interrupt to the CPU (200), the I ² according to the internal clock that is output from the internal clock generating unit 330, the internal clock generating unit 330 for generating an internal clock (CLK) of a constant cycle A clock line checking unit 310 for checking the state of the clock line SCL of the C bus and outputting the checked result to the CPU 200 and a control unit 310 for controlling the output from the internal clock generating unit 330 And a timer 320 for counting an internal clock CLK and outputting an interrupt (INT) to the CPU 200.

Here, the period of the internal clock CLK is 1 / N (N is an integer) of the period of the clock transmitted through the clock line of the I ² C bus.

The internal clock generating unit 330 includes an oscillator 332 and a prescaler 331 for dividing the clock output from the oscillator 332 and outputting the clock to the clock line checking unit 310 and the timer 320. [ .

The I ² C controller 335 releases the clock line SCL under the control of the CPU 200.

The operation of the clock line checking apparatus of the I ² C bus according to the present invention will be described with reference to FIGS. 3 and 4.

First, a start condition is detected by detecting a signal transmitted through a data line SDA and a clock line SCL of the I ² C bus in the start and end condition detecting unit 100. That is, as shown in FIG. 3, since the data line SDA transitions from '1' to '0' in a state where the clock transmitted through the clock line SCL is '1' And the termination condition detection unit 100 detect when the data transmitted through the data line SCL transits from '1' to '0' when the clock transmitted through the clock line SCL is '1' 200).

When the start condition is detected and the start condition detection signal is output to the CPU 200, the CPU 200 operates the clock line checking unit 310 of the clock line state detecting unit 300 to detect the state of the clock line SCL (341).

That is, in the clock line checking unit 310, when the start condition is generated under the control of the CPU 200, the clock line SCL is set to '0' according to the internal clock CLK output from the internal clock generating unit 330 Quot; 1 " or " 1 ", and outputs the checked value to the CPU 200. [

In other words, the internal clock generator 330 generates the internal clock CLK, which is 1 / N times the period of the clock transmitted through the clock line SCL using the oscillator 332 and the prescaler 331, The clock line checking unit 310 checks the change of the clock transmitted to the clock line SCL according to the period of the internal clock CLK generated by the internal clock generating unit 330 And outputs it to the CPU 200.

At this time, if the clock transmitted to the clock line SCL transits to '0' or '1', the CPU 200 determines whether a termination condition is detected again (342).

That is, in the start and end condition detecting unit 100, the start condition detecting unit detects a termination condition. As shown in FIG. 3, in a state where the clock transmitted through the clock line SCL is '1' The start and end condition detection unit 100 detects the start and end conditions of the data line SDA through the data line SCL when the clock transmitted through the clock line SCL is '1' because the data line SDA transitions from '0' Detects the case where the transmitted data transits from '0' to '1', and outputs the detected data to the CPU 200.

At this time, when the termination condition is detected in the start and end condition detecting unit 100, the CPU 200 stops the operation of the clock line checking unit 310 and stops the operation of checking the abnormality of the clock line until the start condition is detected again .

If the termination condition is not detected, the CPU 200 sets (343) the timer 320 configured as a counter when the clock line is changed according to the inspection result of the clock line checking unit 310, The internal clock CLK output from the internal clock generator 330 is counted while decreasing from the set value to '0' (operation 344).

At this time, when the value of the timer 320 becomes '0', the timer 320 generates an interrupt and outputs it to the CPU 200 (345, 346).

That is, in order to check a stuck state in which the state of '0' or '1' lasts in the clock line checking unit 310, the timer 320 stores the initial value by the CPU 200, And decreases its value according to the internal clock CLK output from the unit 330. At this time, if the decremented value of the timer 320 becomes '0', the CPU 200 interrupts.

The initial value of the timer 320 is set by the CPU 200. The initial value is input by the user in advance and stored in a memory such as a ROM so that the CPU 200 can set the timer 320 .

When an interrupt is output from the timer 320, the CPU 200 controls the I ² C controller 335 to release the clock line SCL (347).

If the timer value is not 0, the clock line check unit 310 checks whether the value of the clock line is changed 341. If the value of the clock line is not changed, (344).

This operation will be schematically described with reference to FIG. 4 as follows.

If the start condition is detected 340 and the value of the clock line is changed 341 the timer 320 is set to the initial value 343 and the timer is reset to '0' according to the generated internal clock CLK 320) (344, 345). At this time, if the timer value becomes '0' (345), an interrupt is generated to release the clock line (346, 347).

Also, if the value of the clock line fluctuates (341), the timer is reset to the initial value and the timer value is decremented.

On the other hand, the operation of checking the state of the clock line SCL is from the time when the start condition occurs to the time when the end condition occurs, so that the operation for checking the clock line is stopped until the start condition is generated .

As shown in FIG. 5, the start and end condition detecting unit 100 is enabled according to a signal transmitted through a clock line (SCL) of the I ² C bus and outputs a signal transmitted through the data line SDA And a comparator 410 for comparing the output signal of the comparator 410 and the data line SDA according to a signal transmitted through a clock line SCL of the I ² C bus. A comparator 420 which compares the transmitted signals and outputs a termination condition signal to the CPU 200, a comparator 420 which is enabled in response to a signal transmitted through a clock line SCL of the I ² C bus and outputs the data line SDA, And an inverter 440 for inverting the output signal of the comparator 430 and a signal transmitted through a clock line SCL of the I ² C bus, And the output signal of the inverter 440 and the And a comparator 450 comparing the signals transmitted through the data line SDA and outputting a start condition signal to the CPU 200. [

The operation of the start and end condition detecting unit 100 configured as described above will be described.

When the clock transmitted through the clock line SCL of the I ² C bus is '1', the comparators 410, 420, 430 and 450 are enabled.

At this time, the comparator 430 compares '1' with the data transmitted through the data line SDA of the I ² C bus in order to detect the start condition.

Here, if the data transmitted through the data line SDA of the I ² C bus is '1', the comparator 430 outputs '1' and the comparator 430 outputs the signal from the inverter 440 Is inverted and becomes '0'.

At this time, the comparator 450 compares the data transmitted through the data line (SDA) of the I ² C bus with '0' output from the inverter 440 and outputs the data to the CPU 200.

Here, if the data transmitted through the data line SDA of the I ² C bus is '0', the comparator 450 outputs '1' to inform the CPU 200 of the start condition.

On the other hand, in order to detect the termination condition, the comparator 410 compares the data transmitted through the data line SDA of the I ² C bus with '0'.

When the data transmitted through the data line SDA of the I ² C bus is '0', the comparator 410 outputs '1', and the comparator 410 outputs the signal again to the comparator 420. To the data transmitted through the data line (SDA) of the I ² C bus and output to the CPU 200.

Here, if the data transmitted through the data line SDA of the I ² C bus is '1', the comparator 420 outputs '1' to inform the CPU 200 of the termination condition.

On the other hand, when the clock transmitted through the clock line SCL of the I ² C bus is not '1', the start condition and the end condition are not detected.

As shown in FIG. 6, the clock line checking unit 310 receives the internal clock CLK output from the internal clock generating unit 330 as a clock input, and outputs the clock line SCL of the I ² C bus A flip-flop 510 for receiving a signal transmitted through the flip-flop 510 as a data input, an internal clock CLK output from the internal clock generator 330 as a clock input, and an output of the flip- And a comparator 530 for comparing the outputs of the flip-flops 510 and 520 and outputting the comparison results to the CPU 200. The flip-

The operation of the clock line checking unit 310 configured as described above will be described.

When the internal clock CLK output from the internal clock generator 330 is input, the flip-flop 510 receives a signal transmitted through the clock line SCL. When the internal clock CLK is applied again, Flop 510 receives a signal transmitted to a clock line SCL as an input, and outputs a signal received from a previous clock to a flip-flop 520. [

Therefore, the signals transmitted through the clock line SCL are latched in the flip-flops 510 and 520 in synchronization with the internal clock CLK. Signals latched in the flip-flops 510 and 520, that is, signals transmitted through the clock line SCL for two cycles of the internal clock CLK are input to the comparator 530 and compared.

At this time, if the signal transmitted through the clock line SCL has changed for two cycles of the internal clock CLK, '0' is outputted from the comparator 530 to the CPU 200 to change the value of the clock line SCL Will be announced. If the signal transmitted through the clock line SCL has not been changed for two cycles of the internal clock CLK, a value of '1' is output from the comparator 530 to the CPU 200 so that the value of the clock line SCL is It is not changed.

As described above, the I ² C bus clock line checking apparatus according to the present invention checks the abnormal state of the clock line on the I ² C bus to prevent the occurrence of errors in the transmission data by preventing the clock line from being driven, Thereby improving the transmission efficiency by restoring the line.

An object of the present invention is a clock line inspection apparatus of the I ² C bus to ensure that checks the presence of error in the clock line to drive the clock lines on the I ² C bus to provide.

Claims (7)

A start and end condition detection means (100) for detecting a signal transmitted through a data line (SDA) and a clock line (SCL) of the I ² C bus and detecting a start and end condition indicating a start and end status of data transmission; A CPU (200) for controlling the state of the clock line according to a signal output from the start and end condition detecting means (100); And the CPU 200 senses the state of the clock line SCL of the I ² C bus and interrupts the CPU 200 if the state of the clock line SCL is maintained for a predetermined period or longer And a clock line state detecting means (300) for outputting the clock line state of the I ² C bus. 2. The I ² C bus according to claim 1, further comprising an I ² C controller (335) for releasing the clock line (SCL) under control of the CPU (200) Check device. The apparatus of claim 1, wherein the clock line state sensing means (300) comprises: an internal clock generator (330) generating an internal clock (CLK) of a predetermined period; A clock line checking unit 310 for checking a state change of the clock line SCL of the I ² C bus according to an internal clock output from the internal clock generating unit 330 and outputting the checked result to the CPU 200; And a timer 320 for counting an internal clock CLK output from the internal clock generator 330 under the control of the CPU 200 and outputting an interrupt (INT) to the CPU 200 A clock line check device for an I < ² > C bus. The method of claim 3, wherein said internal clock (CLK) cycle is 1 / N of the cycle of the clock transmitted over the clock line of the I ² C bus, checking (N is an integer) the clock line of the I ² C bus, characterized in that the Device. 5. The apparatus of claim 4, wherein the internal clock generator (330) comprises: an oscillator (332); And a clock line inspection apparatus of the I ² C bus, characterized by consisting of a prescaler 331 that divides the clock output from the oscillator 332 output to the clock line inspection section 310 and the timer 320. The method of claim 3, wherein the clock line checking unit 310 sends the internal clock (CLK) output from the internal clock generating unit 330 to the clock input through a clock line (SCL) of the I ² C bus, A first flip-flop 510 for receiving a signal input from the first flip-flop 510 as a data input; A second flip-flop 520 for taking the internal clock CLK output from the internal clock generator 330 as a clock input and the output of the first flip-flop 510 as a data input; And said first and second flip-flops (510, 520) by comparing its output to the clock line inspection apparatus of the I ² C bus, characterized by comprised a comparator 530 for outputting to the CPU (200) of. 2. The apparatus of claim 1, wherein the start and end condition detection means (100) is enabled according to a signal transmitted through a clock line (SCL) of the I < ² & A first comparator 410 for comparing '0'; And is enabled according to a signal transmitted through a clock line (SCL) of the I ² C bus to compare an output signal of the first comparator 410 with a signal transmitted through the data line (SDA) A second comparator 420 for outputting to the CPU 200; A third comparator 430 which is enabled according to a signal transmitted through the clock line SCL of the I ² C bus and compares '1' with a signal transmitted through the data line SDA; An inverter 440 for inverting an output signal of the third comparator 430; And a clock signal line (SCL) of the I < ² > C bus to compare the output signal of the inverter (440) with a signal transmitted through the data line (SDA) the fourth comparator 450, the clock line inspection apparatus of the I ² C bus, characterized by configured to output, including a CPU (200).