KR0172746B1 - Flash memory device - Google Patents

Abstract

The present invention provides a flash memory device capable of improving the operating characteristics of a cell by precharging a bit line of a sufficiently programmed memory cell string to a Vpc supply voltage higher than the supply voltage when checking a word line wide program of a NAND type flash memory cell string. It is about.

Description

Flash memory device

1 is a circuit diagram of a conventional flash memory device.

2 is a circuit diagram of a flash memory device according to the present invention.

3 is a detailed circuit diagram of a memory cell string of FIGS. 1 and 2.

4 is a waveform diagram for explaining the operation of FIG.

* Explanation of symbols for main parts of the drawings

11: Y-decoder 12 to 15: first to fourth switching means

16: memory cell string 17: voltage switching circuit

18: latch circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device. In particular, when checking a word line wide program of a NAND TYPE flash memory cell string, only a bit line of a sufficiently programmed memory cell string is higher than a power supply voltage Vcc. A flash memory device is configured to be precharged to a Vpc power supply voltage.

In general, in a flash memory device programmed by hot electron injection, all of the memory cells connected to any one word line can be programmed at a time by programming or unprogramming (leave it in an erased state). This programming method is called a wordline wide program.

Next, a word line wide program check operation of a conventional NAND type flash memory cell string will be described with reference to FIG. 1.

For example, although the circuit shown in FIG. 1 is required as many as the number of memory cells connected to one word line, only one circuit is shown for convenience of description. During the program check of the memory cell string, the precharge circuit 1 precharges all the bit lines BL of the memory cell string to the power supply voltage Vcc. Then, the program check operation is performed in the sense amplifier and the write circuit 3 by the timing pulse of the read pre-condition circuit 2. At this time, when the bit line BL is discharged by the memory cell of the selected memory cell string 4, a small pitch between adjacent bit lines according to coupling between bit lines of the highly integrated NAND type flash memory cell. ) Affects stable circuit operation. In addition, since the read pre-condition circuit is connected to each bit line of the memory cell block, the chip area becomes large.

Accordingly, the present invention can eliminate the above-mentioned disadvantages by selectively supplying a Vpc supply voltage higher than the supply voltage Vcc to the bit line of the sufficiently programmed memory cell string when checking the word line wide program of the NAND type flash memory cell string. The purpose is to provide a flash memory device.

The present invention for achieving the above object is a Y-decoder for switching the supply of data input through the data bus line in accordance with the Y-decoder signal, and the data input through the Y-decoder in accordance with a program enable signal A first switching means for supplying a bit line of a memory cell string, a second switching means for switching a supply of a power supply voltage according to a bit line voltage and a read enable bar signal of the memory cell string, and having two nodes; A latch circuit for latching voltages inverted to each node according to the operation of the first and second switching means and the voltage switching circuit, and a fourth switching voltage supplying Vpc higher than the power supply voltage according to a precharge enable signal. And switching means and fifth switching means for switching a ground voltage supply in accordance with the read pre-condition enable signal. It features.

According to the present invention, stable circuit operation is possible, for example, by selectively supplying a Vpc power supply voltage higher than the power supply voltage Vcc to a bit line of a sufficiently programmed memory cell string.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a circuit diagram of a flash memory device according to an embodiment of the present invention. Operation of the flash memory device will be described with reference to FIGS. 3 and 4 as follows.

In the word line wide program and the program check of the flash memory device, for example, at least eight circuits as shown in FIG. 2 are required for the number of memory cells connected to one word line.

First, the operation during word line wide programming will be described. The precharge enable signal PC and the program enable signal P are high. The read enable signal Rb is in a high state. The division select signals SS and SSS of the memory cell string 16 are high and the read pre-condition enable signal RPC is low. At this time, the data in the low state is supplied from the data bus line DB to the node K1 through the NMOS transistor N1 of the Y-decoder 11 turned on by the Y-decoder signal Yi. Subsequently, the NMOS transistor N5 of the first switching means 12 that receives the program enable signal P is turned on to turn on the voltage of the node K1 to the bit line BL of the memory cell string 16. This is supplied. The NMOS transistor N3 of the third switching means 14, which is a read pre-condition circuit for inputting the read pre-condition enable signal RPC, is turned off. While the PMOS transistor P2 of the second switching means 13 which receives the read enable bar signal Rb is turned off, the bit line BL of the memory cell string 16 is inputted. The NMOS transistor N6 of the second switching means 13 is also turned off. In addition, the PMOS transistor P1 of the fourth switching means 15 that receives the precharge enable signal PC is turned off. At this time, the potentials of the nodes K1 and K2 are latched in the low and high states by the inverters 11 and 12 of the latch circuit 18 which use the drain voltage as the power source during the programming of the voltage switching circuit 17.

Accordingly, the potential of the node K1 is latched in the low state and the potential of the node K2 is in the high state, so that the word line wide program is executed for the memory cell string 16.

On the other hand, the operation during the program confirmation and the read only operation that is a subsequent mode by the program algorithm will be described as follows.

First, an operation for precharging the bit line BL will be described. The read enable bar signal Rb is in a high state. The precharge enable signal PC goes from a high state to a low state. The Y-decoder signal Yi and the read pre-condition enable signal RPC go from high to low. That is, in order to precharge the bit line BL of the memory cell string, the Y-decoder signal Yi and the read pre-condition enable signal RPC remain high for an arbitrary time Δt. do. The division select signals SS and SSS of the memory cell string 16 are in a low state (T2 time in T1 in FIG. 4). The NMOS transistor N3 of the third switching means 14, which is a read pre-condition circuit for inputting the read pre-condition enable signal RPC, is turned on. The NMOS transistor N1 of the Y-decoder 11, which receives the Y-decoder signal Yi, is turned on. At this time, the PMOS transistor P1 of the fourth switching means 15 that receives the precharge enable signal PC is turned on to supply a voltage Vpc higher than the power supply voltage Vcc to the memory cell string 16. It is supplied to the bit line BL. Therefore, the bit line BL voltage of the memory cell string 16 is precharged to the high state. The NMOS transistor N5 of the first switching means 12 which receives the program enable signal P as an input is turned off. At this time, the PMOS transistor P2 of the second switching means 13 which receives the read enable bar signal Rb is turned on, while the bit line BL of the memory cell string 16 is input. The NMOS transistor N6 of the second switching means 13 is turned off. Therefore, the nodes K1 and K2 of the latch circuit 18 are latched in the low and high states by the voltage switching circuit 17.

That is, each node K1 and K2 of the latch circuit 18 is latched in the low and high states, and the voltage Vpc of the bit line BL of the memory cell string 16 is higher than the power supply voltage Vcc. Will be precharged.

Thereafter, when the precharge operation of the bit line BL ends (T3 time in T2 of FIG. 4), the read enable bar signal Rb remains high, and the precharge enable signal PC and the The division select signals SS and SSS of the memory cell string 16 go from a low state to a high state. The Y-decoder signal Yi and the read pre-condition enable signal RPC remain high.

At this time, when the program state of the memory cell string 16 is not sufficiently programmed (that is, the erased state), current flows through the memory cell string 16, so that a bit line of the memory cell string 16 is generated. (BL) is discharged from the high state to the low state (B of T3 time to T2 in FIG. 4). On the contrary, when the program state of the memory cell string 16 is sufficiently programmed, the current flowing through the memory cell string 16 is blocked, so that the bit line BL of the memory cell string 16 is in a high state. Precharged (A at T2 in FIG. 4 for T3 hours).

Thereafter, the read enable bar signal RB is set from the high state to the low state (T4 to T5 time in FIG. 4) to perform a program check operation. At this time, the Y-decoder signal Yi and the read pre-condition enable signal RPC are set from the high state to the low state.

First, an operation of a state in which the program state of the memory cell string 16 is not sufficiently programmed (that is, an erase state) will be described.

Current flows through the memory cell string 16, so that the bit line BL of the memory cell string 16 goes from a high state to a low state. Therefore, while the PMOS transistor P2 of the second switching means 134 that receives the read enable bar signal Rb is turned on, the bit line BL of the memory cell string 16 is inputted. The NMOS transistor N6 of the second switching means 13 is turned off. Therefore, the nodes K1 and K2 of the latch circuit 17 are latched low and high by the drain voltage when the program of the voltage switching circuit 17 is checked.

That is, when any of the memory cells of the memory cell string 16 is not programmed, the bit lines of the memory cell string 16 are latched by latching the potentials of the nodes K1 and K2 into low and high states, respectively. (BL) is discharged and program operation is performed until fully programmed.

On the contrary, when the program state of the memory cell string 16 is sufficiently programmed, the current flowing through the memory cell string 16 is cut off so that the bit line BL of the memory cell string 16 is in a high state. Precharged to At this time, the NMOS transistor and the PMOS transistors N6 and P2 of the second switching means 13 which respectively input the bit line BL and the read enable bar signal Rb of the memory cell string 16 are turned on. do. Therefore, the node K1 goes high. At this time, the potential of the node K2 is latched to the high state through the inverter I1 which inputs the power supply voltage Vcc of the voltage switching circuit 17.

That is, when the memory cell string 16 is sufficiently programmed, the potentials of the nodes K1 and K2 are inverted into high and low states, and the bit line BL of the memory cell string 16 is precharged. In this case, the memory cell string 16 is no longer programmed during the next program operation.

On the other hand, when the read pre-condition enable signal RPC becomes high, the third switching means 14 which is the read pre-condition circuit is turned on by the NMOS transistor N3 through the Y-decoder 11. The two nodes K1 and K2 of the latch circuit 18 are pre-conditioned in a low state and a high state.

Thereafter, when the read enable bar signal Rb goes from the low state to the high state (T5 time in FIG. 4), the word wide program operation is terminated for the memory cell string.

As described above, according to the present invention, when a word line wide program of a NAND type flash memory cell string is checked, a bit line of a sufficiently programmed memory cell string is precharged to a Vpc power supply voltage higher than the power supply voltage. The influence between the bit lines is eliminated, and the circuit configuration is simple, which is excellent in improving the operation characteristics and reliability of the cell.

Claims (5)

A Y-decoder for switching the supply of data input through the data bus line in accordance with a Y-decoder signal, and a second source for supplying data input through the Y-decoder in accordance with a program enable signal to a bit line of a memory cell string. A first switching means, a second switching means for switching a supply of a power supply voltage according to a bit line voltage and a read enable bar signal of the memory cell string, and two nodes, the first and second switching means and voltage switching. A latch circuit for latching voltages inverted to each node according to an operation of the circuit, fourth switching means for switching a Vpc voltage supply higher than the power supply voltage according to a precharge enable signal, and lead pre-condition enable And a fifth switching means for switching the ground voltage supply according to the signal. 2. The flash memory according to claim 1, wherein said first switching means is composed of an NMOS transistor connected between a node K1 of said latch circuit and a bit line of said memory cell string, and having said program enable signal as an input. Device. 2. The PMOS transistor and the NMOS transistor of claim 1, wherein the second switching means is connected in series between a node K1 and a power supply terminal of the latch circuit, and inputs a bit line voltage and a read enable bar signal of a memory cell string, respectively. Flash memory device, characterized in that configured. 2. The flash memory device according to claim 1, wherein said third switching means is composed of an NMOS transistor connected between a data bus line and ground and having a read pre-condition enable signal as an input. 2. The flash memory device according to claim 1, wherein said fourth switching means comprises a PMOS transistor connected between a Vpc power supply terminal and a bit line of said memory cell string and receiving a precharge enable signal.