KR0172394B1 - Semiconductor memory device having a data-inversion function internally - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of performing data inversion operation internally.

2. The technical problem to be solved by the invention:

In the related art, data cannot be processed internally in a chip, and when data is inverted, data is transferred to the outside of the chip to process data by an operation of a graphics processor. This operation is caused by collectively moving the data designated by the source address when moving the data to the destination address. In addition, when converting the color in pixel units while moving the data of the source address to the destination address, the cell data corresponding to the pixel is read out of the memory device, and the data is processed by the graphic processor to obtain the source address. After writing, data can be moved to the destination address using the internal latch circuit. Therefore, in the conventional case, the functional degradation of the semiconductor memory device is a problem. Accordingly, it is a problem of the present invention to implement a device of a semiconductor memory having an improved function.

3. Summary of the solution of the invention:

A memory cell for storing a plurality of data information, a column selection circuit for controlling input and output of data stored in the memory cell by a column address, a plurality of input / output line pairs through which predetermined data is moved, and the input / output line pair An input sense amplifier for sensing and amplifying the transmitted data, an internal latch circuit for storing the data sensed and amplified by the input sense amplifier for a predetermined time, and a connection between the input sense amplifier and the internal latch circuit and connected to a predetermined control signal. A predetermined first transfer gate controlling an operation of transferring the output of the input sense amplifier to the internal latch circuit, a write driver connected to one end of the column selection circuit and driving an output of the internal latch circuit; The internal latch circuit is connected between the internal latch circuit and the write driver by a predetermined control signal. 12. A semiconductor memory device having a predetermined second transfer gate for controlling an operation of transferring an output of the output to the write driver, wherein the input sense amplifier, the internal latch circuit, and the write driver are connected in plural to one input / output line pair. Selectively enable all or part of the plurality of input sense amplifiers in response to an output of a predetermined input sense amplifier control means for inputting and logically combining a predetermined control clock, mask signal, enable signal and least significant bit information; A dual data transmission path is provided between the input sense amplifier and the first transmission gate to output the output of the input sense amplifier as one of the dual data transmission paths as it is during a predetermined first operation. Inverts the output of the input sense amplifier to the other one of the dual data transmission paths. By the implementation of a semiconductor memory device, it characterized in that the output is to eliminate the above problems.

4. Important uses of the invention:

Semiconductor memory device with improved functionality.

Description

Semiconductor memory device that performs data inversion function internally

1 shows a data processing path according to the prior art.

2 is a diagram illustrating a data processing path according to an embodiment of the present invention.

3 is a detailed circuit diagram of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having improved performance by performing a data inversion function.

In recent years, frame buffer memory has been designed to improve functions by mounting, on-chip, circuits having functions that have been conventionally performed by a graphic processor in a memory device. The window RAM of the frame buffer memory includes a plurality of input / output sense amplifiers per one input / output line and a plurality of input / output sense amplifiers per one input line to perform a block move operation of data on a cathode ray tube (CRT). Two internal latch circuits, a plurality of transfer gates, and a plurality of write drivers are incorporated to perform the above-described block move operation.

The process is as follows. That is, when the source data at the source addresses Xs and Ys is moved to the destination address Xd and Yd, the read / write operation is performed through the input / output pad as in the conventional case. After moving to the internal latch circuit using the internal latch circuit embedded in the memory chip (DRAM TO LATCH, DTL), instead of moving to the destination address, the data in the internal latch circuit is transferred to the destination address. Therefore, it is internally performed to move data at high speed (referred to as LATCH TO DRAM, LTD).

The data select / un select function, which is frequently used in the window state, is an operation of converting the color of data designated by the selected source address and writing it back to the source address (this is called a data selection function). ) And converts the color of the selected data into the original color and writes it to the source address (this is called a data non-selection function). In this case, in order to convert the color, data designated by the source address must be read out of the memory, and then the color must be converted by the graphic processor and written to the source address again. Therefore, even if the internal latch circuit is built in the memory device, data movement using the internal latch circuit is possible only in the case of simple data movement that does not require data processing. Therefore, data processing is required as the data selection / non-selection function. In this case, the data must be read out of the memory device, and then the data must be inverted from the graphic processor, that is, the color is converted, and the data is written back to the source. Therefore, when performing such a function, the semiconductor memory device is slowed down, and a significant functional degradation such as malfunction due to loss of signal voltage which is likely to occur in the process of data moving inside and outside the chip is expected.

This operation process is shown in FIG. 1 is a view showing a data processing path of a window RAM according to the prior art.

In the configuration of FIG. 1, when the control clock DTLCLK is enabled when data of the memory cell 10 is transmitted to the internal latch circuit 24 through the column select circuit 12 and the input sense amplifier 14, the input sense amplifier is enabled. When the data sensed at (14) is transferred in a single data transfer path 20 and through the transfer gate 22 collectively, and requires data processing for cell data, the block move operation using an internal latch circuit is performed. Internal operation cannot be performed internally, and the cell data is read out of the chip to invert the data in the graphic processor, and then written back to the memory cell, and then the block move operation is performed by the internal operation. Therefore, it takes a long time to perform a block move operation that requires data processing, and the data must be moved in and out of the chip, thereby degrading performance.

The above problem is caused by collectively moving the data designated by the source address when moving the data to the destination address. In addition, when converting the color in pixel units while moving the data of the source address to the destination address, the cell data corresponding to the pixel is read out of the memory device, and the data is processed by the graphic processor to obtain the source address. After writing, data can be moved to the destination address using the internal latch circuit.

It is therefore an object of the present invention to provide an apparatus of a semiconductor memory for processing data at high speed.

Another object of the present invention is to provide a semiconductor memory device having improved performance by adding a function to internally invert data.

In order to achieve the objects of the present invention, a memory cell for storing a plurality of data information, a column selection circuit for controlling the input and output of the data stored in the memory cell by a column address, and a plurality of input and output lines to move the predetermined data A pair, an input sense amplifier for sensing and amplifying data transmitted through the input / output line pair, an internal latch circuit for storing a predetermined amount of data sensed and amplified by the input sense amplifier, and the input sense amplifier and the internal latch circuit. A predetermined first transfer gate connected between the first and second transfer gates for controlling an operation of transferring the output of the input sense amplifier to the internal latch circuit by a predetermined control signal, and connected to one end of the column selection circuit. A light driver for driving an output, and connected between the internal latch circuit and the light driver According to an aspect of the present invention, there is provided a semiconductor memory device including a predetermined second transfer gate configured to control an operation of transferring an output of the internal latch circuit to the write driver by a predetermined control signal. A plurality of write drivers are connected to one input / output line pair, and the plurality of write drivers are input in response to an output of a predetermined input sense amplifier control means for inputting and combining a predetermined control clock, a mask signal, an enable signal, and least significant bit information. Selectively enable all or part of the input sense amplifiers and provide a dual data transmission path between the input sense amplifier and the first transmission gate so that the inputs are transmitted to one of the dual data transmission paths during a predetermined first operation; Outputs the output of the sense amplifier as it is, and during the second predetermined operation, In the transport path is characterized in that the inversion to output the output of the input sense amplifiers.

Hereinafter, exemplary embodiments of a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

2 is a diagram illustrating a data processing path according to an embodiment of the present invention.

Referring to FIG. 2, the memory cell 32 is connected to one end of the column select circuit 34. The other end of the column selection circuit 34 is commonly connected to an input terminal of the input sense amplifier 36 and an output terminal of the write driver 52. The output terminal of the input sense amplifier 36 is connected to the input terminal of the dual data transmission path 40. The output terminal of the dual data transmission path 40 is connected to the input terminal of the transmission gate 42. The output terminal of the transfer gate 42 is connected to the input terminal of the internal latch circuit 46. The output terminal of the internal latch circuit 46 is connected to the input terminal of the transfer gate 50. The output terminal of the transfer gate 50 is connected to the input terminal of the write driver 52, and the output terminal of the write driver 52 is connected to the other end of the column selection circuit 34 as described above. Output terminals of the input sense amplifier control means 38 and the transfer gate control means 44 are connected to the control electrodes of the input sense amplifier 36 and the transfer gate 42, respectively. In addition, the output terminal of the precharge circuit 48 and the control clock LTDCLK are connected to the internal latch circuit 46 and the control electrodes of the transfer gate 50. The output terminal of the write driver control circuit 54 is connected to the control electrode of the write driver 52. As the input terminals of the input sense amplifier control means 38, a control clock DTLCLK, a mask signal MASK, an enable signal and? EN and least significant bit information? LSB are input, respectively. In addition, control pulse DTLP, input data Di, and mask signal MASK are input to the input terminals of the transmission gate control means 44, respectively. A mask signal MASK is input to the input terminal of the precharge circuit 48. As the input terminals of the write driver control circuit 54, a mask signal MASK, input data Di, a write control signal? WR, a control clock LTDCLK, and least significant bit information? LSB are respectively input.

3 is a detailed circuit diagram of FIG. The operation according to the invention is described with reference to FIG. 2 and FIG.

According to the present invention, when the data designated by the source address is transmitted to the internal latch circuit 46, a path for directly transmitting data from the input sense amplifier 36 to the internal latch circuit 46, and the input sense amplifier 36 The input data Di and the mask signal when the DTL operation is performed on the transfer gate 42 which transfers the data of the input sense amplifier 36 to the internal latch circuit 46. The bit-to-bit control by the MASK allows color selection by data selection / non-selection functions and pixel units. In addition, the internal latch circuit 46 is provided with a precharge circuit 48 controlled by a mask signal MASK to add a function of quickly erasing the bit plane of the memory cell using the LTD, thereby providing a constant on the corresponding display means. This will add the ability to quickly erase the area. As a result, data processing can be performed internally at a high frequency.

If a source address is specified and one row is selected in the memory cell, the data stored in the unit memory cell connected to the row is first amplified by a bit line sense amplifier (not shown) and then a predetermined number of column selection circuits 34 ) Is loaded on the predetermined number of input / output lines. The data carried on the input / output line is amplified secondly by a predetermined number of input sense amplifiers 46. At this time, the input sense amplifier 46 is operated by the input sense amplifier control means 38 for inputting the control clock DTLCLK, the mask signal MASK, the enable signal? EN, and the low-order bit information? LSB. In the normal read operation, only one of the predetermined number of input sense amplifiers 36 is operated by the least significant bit information? LSB and the enable signal? EN. However, during the DTL operation, the control clock DTLCLK generates Enable all input sense amplifiers. However, when the mask signal MASK is in the 'high' state, the corresponding input sense amplifier is disabled, and only the input sense amplifier corresponding to the mask signal MASK in the 'low' state is enabled. A dual data transmission path 40 and a transmission gate 42 are provided between the input sense amplifier 36 and the internal latch circuit 46. The dual data transmission path 40 inverts the output of the input sense amplifier 36. It consists of a pass delivered directly and a pass delivered directly, and there are transmission gates in each pass. The transfer gate is controlled by the transfer gate transfer means 44 which inputs the external input data Di input through the input buffer during operation of the DTL and the control pulse DTLP generated by the mask signal MASK and the enable clock øEN. When the signal MASK is 'high', all of the corresponding transmission gates are disabled. When the mask signal MASK is 'low', one of the two transmission gates is selected according to the state of the external input data Di. In this case, when the external input data Di is 'high', uninverted data is transmitted from the input sense amplifier 36 to the internal latch circuit 46. When the state of the external input data Di is 'low', the input sense amplifier ( In 36, the inverted data is transmitted to the internal latch circuit 46. The internal latch circuit 46 has a precharge circuit 48 controlled by the mask signal MASKD. When the mask signal MASK is 'high', the internal latch circuit 46 is precharged.

Therefore, when the mask signal MASK is 'low' and the external input data Di is 'high', uninverted data is transmitted to the internal latch circuit 46, and the mask signal MASK is 'low' and the external input data Di When is low, the data of the input sense amplifier 36 is inverted and transmitted to the internal latch circuit 46. However, when the mask signal MASK is 'high', the corresponding input sense amplifier 36 and the dual data transmission path 40 are disabled so that data of the input sense amplifier 36 is not transmitted to the internal latch circuit 46. Only the precharge circuit 48 precharges the corresponding internal latch circuit 46.

Data transmitted to the internal latch circuit due to the DTL operation is transmitted to the destination addresses Xd and Yd through the predetermined number of write drivers 52 through the transfer gate 50 during the LTD operation. At this time, the transfer gate 50 is enabled by receiving the control clock LTDCLK to transfer data from the internal latch circuit 46 to the write driver 52. The write driver 52 is controlled by the write driver control circuit 54 which inputs the external input data Di, the mask signal MASK, the write control signal? WR, the control clock LTDCLK and the least significant information? LSB, which are input through the input buffer during the LTD operation. do. When the mask signal MASK is 'high' and the external input data Di is 'high' during the LTD operation, the corresponding write driver is disabled so that the data of the corresponding memory cell is not converted, and the mask signal MASK is 'high'. When the external input data Di is 'high' and the external input data Di is 'low', the corresponding write driver is enabled so that data precharged to the internal latch circuit 46 is written to the corresponding memory cell. However, when the mask signal MASK is 'low', all of the predetermined number of write drivers are enabled regardless of the external input data Di, and the data of the internal latch circuit is written to the corresponding memory cell. In the normal write operation, only one of the predetermined number of write drivers is enabled by the lowest order? LSB.

By implementing the semiconductor memory device as described above, the data inversion function is performed internally on the chip, thereby significantly improving the performance of the semiconductor memory device. In other words, even when data processing is performed, processing is performed internally, thereby preventing malfunctions during processing speed and processing operation.

Claims (5)

A memory cell for storing a plurality of data information, a column selection circuit for controlling input and output of data stored in the memory cell by a column address, a plurality of input / output line pairs through which predetermined data is moved, and the input / output line pair An input sense amplifier for sensing and amplifying the transmitted data, an internal latch circuit for storing the data sensed and amplified by the input sense amplifier for a predetermined time, and a connection between the input sense amplifier and the internal latch circuit and connected to a predetermined control signal. A predetermined first transfer gate controlling an operation of transferring the output of the input sense amplifier to the internal latch circuit, a write driver connected to one end of the column selection circuit and driving an output of the internal latch circuit; The internal latch circuit is connected between the internal latch circuit and the write driver by a predetermined control signal. 12. A semiconductor memory device having a predetermined second transfer gate for controlling an operation of transferring an output of the output to the write driver, wherein the input sense amplifier, the internal latch circuit, and the write driver are connected in plural to one input / output line pair. Selectively enable all or part of the plurality of input sense amplifiers in response to an output of a predetermined input sense amplifier control means for inputting and logically combining a predetermined control clock, mask signal, enable signal and least significant bit information; A dual data transmission path is provided between the input sense amplifier and the first transmission gate to output the output of the input sense amplifier as one of the dual data transmission paths as it is during a predetermined first operation. Inverts the output of the input sense amplifier to the other one of the dual data transmission paths. The semiconductor memory device characterized in that the output. The semiconductor memory device of claim 1, wherein the predetermined first operation is a block move operation. 2. The semiconductor memory device according to claim 1, wherein said second predetermined operation is a data selection operation. 2. The semiconductor memory device according to claim 1, wherein all or part of a plurality of the first transfer gates are activated in response to a control pulse synchronized with the predetermined control clock, external input data, and a mask signal. The semiconductor memory device according to claim 1, wherein the internal latch circuit further comprises a precharge circuit controlled to the mask signal to precharge the internal latch circuit during a predetermined normal read operation.