KR0172353B1 - Input signal control circuit of semiconductor memory device - Google Patents

Abstract

1. the technical field to which the invention described in the claims belongs;

The present invention relates to an input signal control circuit of a semiconductor memory device.

2. The technical problem to be solved by the invention;

The present invention minimizes the path of the master signal to determine the latch timing in a dynamic RAM operating at high frequency, and includes a delay before the latch of the slave stage to have a margin that satisfies the setup and holding time, and is optimal in high frequency operation. It provides an input signal control circuit for controlling the setup and holding time of the.

3. Summary of the Solution of the Invention;

An input signal control circuit of a semiconductor memory device having a high frequency operation with an input signal for activating reads and writes by selecting rows and columns of a unit 를 constituting a memory array. A first input buffer unit for converting a signal of the TTI level into a signal of the CMOS level; A first driver unit for amplifying and driving an output signal of the first input buffer unit to supply a master signal to external control circuits; A second input buffer part for converting a Tiel level signal into a CMOS level signal using the same signal as the first input buffer part as an input signal; A third input buffer unit for converting the TI level signal into a CMOS level signal using a TTI level slave clock as an input signal; A delay unit for delaying an output signal of the third input buffer unit; A latch unit for latching an output signal from the delay unit using the output signal output from the second input buffer unit as a control signal; A second driver unit which amplifies and drives a signal stored in the latch unit and supplies a slave signal to external control circuits is provided.

4. Significant use of the invention;

It is suitably used for semiconductor memory devices.

Description

Input signal control circuit of semiconductor memory device

1 is a block diagram showing the configuration of an input signal control circuit according to the prior art.

2 is a block diagram showing a configuration of an input signal control circuit according to the present invention.

3a, 3b, and 3c are detailed block diagrams of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input signal control circuit of a semiconductor memory device, and in particular, minimizes a transmission path of a master signal that determines a latch point during high frequency operation, and includes a delay before latching a slave signal. The present invention relates to an input signal control circuit for optimizing -up and hold time.

In recent years, semiconductor memory devices have become increasingly large in size and high speed due to the development of manufacturing technology. Therefore, an input signal control circuit for controlling the set-up and hold time that is to be maintained in the memory device operated at a high frequency is essential. Since dynamic random access memory (DRAM) is operated at a low frequency (40 MHz or less), the setup and maintenance time of the memory specification are sufficiently defined, and therefore, no problem was found in the implementation method according to the prior art. . However, in the case of a dynamic RAM (DRAM) having a high frequency (50 MHz or more) function, there is a problem that the conventional technology cannot fundamentally solve the problem due to densely setting up and holding time specifications.

1 is a block diagram showing the configuration of an input signal control circuit according to the prior art. Referring to FIG. 1, the configuration and the operation will be described. The TTL level master clock and the TTL level slave clock are transmitted to the input buffers 10 and 40, respectively. The input buffers 10 and 40 convert the signal of the TTL level into a signal of the CMOS level, and the master signal changed from the first input buffer 10 to the CMOS level corresponds to the first driver 20. Used as a master signal after roughness. The master signal is also generated as a delay signal via a separate delay unit 30. The delayed signal is determined by the second input buffer 40 to determine the latch timing of the latch unit 50 for latching the CMOS level signal converted from the TTL level to the CMOS level, thereby satisfying the setup and maintenance time. However, in the high-frequency dynamic DRAM (DRAM), the conventional input signal control circuit as shown in FIG. 1 has a problem that the margin of setup and holding time cannot be sufficiently guaranteed.

Accordingly, an object of the present invention is to minimize the path of the master signal to determine the latch point in the dynamic ram operated at high frequency, and to provide a margin that satisfies the setup and holding time by providing a delay before the latch of the slave stage. An input signal control circuit for controlling an optimal setup and holding time is provided.

In order to achieve the above object, an input signal of a semiconductor memory device having a high frequency operation with an input signal for activating reads and writes by selecting rows and columns of a unit 있는 constituting a memory array in accordance with an aspect of the present invention. The control circuit includes: a first input buffer unit for converting a TI level signal into a CMOS level signal using a TI level master clock as an input signal; A first driver unit for amplifying and driving an output signal of the first input buffer unit to supply a master signal to external control circuits; A second input buffer part for converting a Tiel level signal into a CMOS level signal using the same signal as the first input buffer part as an input signal; A third input buffer unit for converting the TI level signal into a CMOS level signal using a TTI level slave clock as an input signal; A delay unit for delaying an output signal of the third input buffer unit; A latch unit for latching an output signal from the delay unit using the output signal output from the second input buffer unit as a control signal; And a second driver unit for amplifying and driving a signal stored in the latch unit to supply a slave signal to external control circuits.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

2 is a block diagram showing the configuration of an input signal control circuit according to the present invention. Referring to FIG. 2, the first driver 110 and the TTL level slave generating the master signal by inputting the first and second input buffers 100 and 120 and the output signals of the first input buffer 100 as inputs to the TTL level master clock. The output signal of the delay unit 140 is controlled by using the third input buffer 130 for inputting the clock and the delay unit 140 for inputting the output signal of the third input buffer 130 and the output signal of the second input buffer 120 as control signals. A latch unit 150 for latching and a second driver 160 for outputting a slave signal by inputting the output signal of the latch unit 150 are configured. Referring to the operation of FIG. 2, in this configuration, there are first and second input buffers 100 and 120, and the first input buffer 100 is connected to a number of control circuits to increase driving ability in the first driver 110 as a master signal. Works. In this case, the second input buffer 120 generates a TTL level master clock as the internal signal as quickly as possible to determine a latch.

In general, in the high frequency operation dynamic ram, the specification has a setup time of about 7 nanoseconds (ns) and a holding time of about 0 nanoseconds (ns). Therefore, in order to have a margin in this specification, a TTL level master clock is required as described above. A second input buffer 120, that is, a second input buffer 120 is provided separately from the first input buffer 100 to obtain a margin satisfying the setup and holding time during high frequency operation.

3A, 3B, and 3C are detailed circuit diagrams of the blocks shown in FIG. 2, and have the same reference numerals as the block diagrams in FIG.

First, FIG. 3A is a detailed internal circuit diagram of the first input buffer 100 and the first driver of FIG. 2, and includes a delay circuit composed of an inverter chain 3 having an input control signal PIINIT and having a predetermined delay time. Source) is connected to an external power supply voltage VCC terminal, a drain is commonly connected to each other, and a gate is connected to an output terminal of the inverter chain 3, PMOS transistors 5,7,9,11 and PMOS transistors 5,7 Source and gate are connected to a common output terminal of the signal output circuit VREFBUF as a drain input and a source and gate are connected to the common output terminal of the PMOS transistors 5, 7, 9, and 11, respectively. Is connected to the PMOS transistors 19, 21 and 23 which input the column address strobe signal CASB as the drain input, and the gate input terminal is connected to the output terminal of the inverter chain 3. An NMOS transistor 35 having a source connected to the drains of the PMOS transistors 19, 21, and 23, and a TIMEL-level ground voltage VSSTTL terminal commonly connected to the drain and the source, and an NMOS transistor having the signal VREFBUF as a gate input. 25, an NMOS transistor 29 having a drain and a gate connected to a common output terminal of the PMOS transistors 5, 7, 9, 11 and a drain connected to an output terminal of the PMOS transistor 5, 7, 9, 11, An NMOS transistor 27 having a source connected to each other, a drain connected to a common output terminal of the PMOS transistors 5, 7, 9, and 11, and a gate connected to each gate of the NMOS transistors 29 and 27, respectively. And 33. The first driver 110 includes a PMOS transistor 37 having one side connected to an external power supply voltage VCC terminal and a gate connected to a drain of the PMOS transistors 19, 21, 23, and the PMOS transistors 19, 21, 23. An MOS transistor 39 connected to a drain, the drain being connected to a drain of the PMOS transistor 37, and a PMOS transistor 41 and an MOS transistor 43 formed by connecting common drains of the PMOS transistor 37 and the ENMOS transistor 39 to a gate. And an inverter chain 45 connected to the common drain and the input terminal of the PMOS transistor 41 and the NMOS transistor 43 and having a predetermined delay time. Operation is omitted since the individual elements are connected.

FIG. 3B is a detailed internal circuit diagram of the second input buffer 102 of FIG. 2, which is substantially the same as that of FIG. 3A, except that the delay circuit is removed from the input terminal of the input signal and that the activation signal PIRST is applied as the input signal. As a point and a driver, only the Emmos transistor 39, the PMOS transistor 37, and the inverter 9 consist of different points.

FIG. 3C is a detailed internal circuit diagram of the third input buffer 130, the delay unit 140, the latch unit 150, and the second driver of FIG. 2, and the source and drain of the NMOS transistor 25 in the configuration of FIG. The common source terminal of the NMOS transistors 27, 29, 31, and 33 is connected to the ground voltage VSS terminal, and the gate terminal of the PMOS transistors 19, 21, 23 is not connected to the common source terminal of 29, 31, 33. The difference is that the external address Ai is input as an input, and the delay unit 140 is further provided, and the delay unit 140 includes the inverters 61 and 63 connected in series. In addition, compared to the first driver 110 of FIG. 3A, the second driver 160 of FIG. 3C further includes a PMOS transistor 42 between the source of the PMOS transistor 37 and the external power supply voltage VCC terminal. The latch control signal PLYALB1 is input to the gate input of. In addition, the configuration in which the NMOS transistor 44 is further provided between the source of the NMOS transistor 39 and the ground voltage VSS terminal and the gate input terminal thereof is connected to the transfer gate 93 is different from that of the first driver 110 of FIG. 3A.

As described above, in the present invention, the concept of the setup and the maintenance time in the high frequency operation dynamic RAM and the SDRAM, the WRAM, etc. is more and more closely approached to the system, compared to the conventional setup and maintenance time concept. Memory control configuration has become complicated. In the implementation of the configuration of the present invention, the determination of the setup and maintenance time is achieved by determining the latch time with an internal signal generated in synchronization with the TTL level master clock in internally latching a valid TTL level slave clock. To realize. Although the first and second input buffers 100 and 120 may be configured as ones without being separated separately, since the delay unit 140 needs to use information, it is difficult to minimize the latch timing and the fan of the master signal. Since it has a fan out loading at the same time, the latch timing is delayed by that much, so the first and second input buffers 100 and 120 are preferably separated from each other.

Another feature for realizing the present invention is receiving the TTL level slave clock and converting it to the CMOS level through the third input buffer 130, and through the delay unit 140, the slave signal is properly margined with the latch timing by the master clock generation signal. Delay to increase the level up to a certain level and latches the valid slave signal in the latch unit 150 to maximize the input signal path inside the chip, and to realize high-speed operation and have a margin of setup and maintenance time separately. Has

As described above, according to the present invention, it is possible to obtain a margin that satisfies the setup and holding time during low frequency as well as high frequency operation.

Although the present invention described above is limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (4)

An input signal control circuit of a semiconductor memory device having a high frequency operation with an input signal for activating reads and writes by selecting rows and columns of a unit 를 constituting a memory array. A first input buffer unit for converting a signal of the TTI level into a signal of the CMOS level; A first driver unit for amplifying and driving an output signal of the first input buffer unit to supply a master signal to external control circuits; A second input buffer part for converting a Tiel level signal into a CMOS level signal using the same signal as the first input buffer part as an input signal; A third input buffer unit for converting the TI level signal into a CMOS level signal using a TTI level slave clock as an input signal; A delay unit for delaying an output signal of the third input buffer unit; A latch unit for latching an output signal from the delay unit using the output signal output from the second input buffer unit as a control signal; And a second driver unit for amplifying and driving a signal stored in the latch unit to supply a slave signal to external control circuits. The input signal control circuit of claim 1, wherein the second input buffer unit is separated from the first input buffer unit by one or more. The input signal control circuit of claim 1, wherein the latch unit determines the latch timing of the slave signal of the TI level according to the control signal of the second input buffer. The input signal control circuit of claim 1, wherein the delay unit is positioned between the third input buffer unit and the latch unit.