KR0172280B1 - Sensing circuit of a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sensing circuit of a semiconductor device, wherein the reference cell is composed of a single bit, not a cell array type, and the word line is biased independently of the word line of the main cell. By applying the control gate of the reference cell without applying the confirmation voltage to the control gate of the cell, the layout of the cell is reduced during erasing, and the circuit configuration is simplified since the drive capability of the confirmation voltage generating circuit is not large. In addition, the recovery time for charging and discharging the control gate is drastically reduced in order to make the read mode from the read mode to the normal read mode, thereby reducing the overall program and erase time. It relates to a sensing circuit.

Description

Sensing Circuit of Semiconductor Device

1 is a sensing circuit diagram of a conventional semiconductor device.

2 is a characteristic curve of a cell current according to a control gate voltage of a cell in FIG.

3 is a timing diagram of a control gate during erasing in FIG.

4 is a sensing circuit diagram of a semiconductor device according to the present invention.

* Explanation of symbols for main parts of the drawings

11: X-decoder 12: Y-decoder

13 sense amplifier 14 read voltage generation circuit

15: Program confirmation voltage generation circuit 16: Erase confirmation voltage generation circuit

17: Mod State Machine

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sensing circuit of a semiconductor device. In particular, a reference cell is composed of a single bit, not a cell array, and a word line is a main cell. The present invention relates to a sensing circuit of a semiconductor device which is biased independently of a word line of a cell) and applied to a control gate of a reference cell without applying a confirmation voltage to a control gate of a main cell.

In general, in reading data of a non-volatile memory cell that senses current, the sensing speed depends on the threshold voltage V _t of the reference memory cell. It is applied to a flash EEPROM cell or the like that requires a stable sensing speed without being affected by the variation of the threshold voltage of the reference memory cell.

1 is a sensing circuit diagram of a conventional semiconductor device, the operation of which is described below.

The reference chamber M1 is configured in the form of the main cell M2 and the cell array 9, and the word line W / L is also shared with the main cell M2. In addition, the bias applied to the control gate of the reference cell M1 is applied to the read voltage from the read voltage generation circuit 4 regardless of the mode. On the other hand, data of the mode state machine 7 which inputs data of the command user interface circuit 8 is input in a plurality of modes 4 to 5. At this time, the bias applied to the control gate of the main cell M2 is applied to the confirmation voltage from the program check voltage generation circuit 5 and the erase check voltage generation circuit 6 through the MUX circuit 10. This allows the program and erase confirmation to be carried out via the sense amplifier 3. The reference cell is selected according to the selection of the word lines W / L having the X-decoder 1 as input and the selection transistors N1 and N2 having the Y-decoder 2 as input. In this case, the reference cells are UV Erase cells, and variations in the cell's threshold voltage Vt occur due to uniformity or other factors of the process, resulting in read and verify operations. Will affect. In the confirmation mode, the threshold voltage distribution of the main cell arrays is made wider, which causes deterioration of device characteristics.

2 is a characteristic curve of the cell current according to the control gate voltage of the cell in FIG. Control gate voltage, V1 denotes an erase margin, V2 denotes a program margin, Ier denotes an erase cell current, Ip denotes a program cell current, and Iuer denotes a reference cell current. This is a characteristic curve showing a method of controlling the cell current by applying confirmation voltages generated during programming and erasing to the control gate of the main cell in consideration of the margin at the time of reading. However, from the standpoint of the confirmation voltage generation circuit, which is a reference voltage generation circuit, the loading is considerably large, and accordingly, the switching of the control gate voltage accumulated at the high voltage for programming and erasing to the program and erasure confirmation voltage is again performed. This will be time consuming. In addition, a recovery step for returning to the biasing state of the read voltage from the check voltage is additionally required. As a result, there is a problem in that the time until the device enters the program and erase mode is returned to the normal read state, that is, the entire time of the program and erase mode is delayed. . Unexplained code T1 denotes an erase setup time, T2 denotes an erase time, T3 denotes an erase confirmation time, and T4 denotes a confirmation time. In addition, Vcg2 represents a read voltage, Vcg1 represents an erase confirmation voltage, and Vcg4 represents an erase voltage.

Accordingly, the present invention configures the reference cell as a single bit rather than a cell array, biases the word line independently from the word line of the main cell, and applies a confirmation voltage to the control gate of the main cell. It is an object of the present invention to provide a sensing circuit of a semiconductor device that can solve the above disadvantages by applying to a control gate of a reference cell without applying.

The present invention for achieving the above object is a plurality of reference cells consisting of a single bit, not a cell array form, and each mode data to be biased independently of the word line of the main cell to the select gate of the reference cell A mode state machine for supplying, a program confirming voltage generating circuit, a read voltage generating circuit and an erasing confirming voltage generating circuit for supplying data to the control gate of the reference cell, a select gate for inputting data of an X-decoder; A node connected to a main cell having a source connected to ground, a select transistor for inputting data of the Y-decoder, a resistor connected to a power supply voltage and a drain of the reference cell, a resistor connected to the power supply, and Each node, which is the connection point with the drain of the main cell via the select transistor, is input to It is characterized by consisting of a sense amplifier.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a sensing circuit diagram of a semiconductor device according to an exemplary embodiment of the present invention, wherein a plurality of reference cells M11 to M13 and single select bits of the reference cells M11 to M13 that are configured as a single bit rather than a cell array form are shown. A mode state machine 17 for supplying respective mode data PGMV, READ, and ERV to be biased independently of the word line W / L of the main cell M14, and the reference. Data of the program confirmation voltage generation circuit 15, the read voltage generation circuit 14 and the erase confirmation voltage generation circuit 16, and the X-decoder 11 for supplying data to the control gates of the cells M11 to M13. A main cell 11 having a select gate (word line) and a source connected to ground (Vss), a selection transistor N11 for inputting data of the Y-decoder 12, and a power supply Vcc. Is connected to the resistor R1 and the reference cells M11 to M13. A node K1, which is a connection point with a phosphorus, and a node K2, which is a connection point between a resistor R2 connected to the power supply Vcc and a drain of the main cell M14 via the selection transistor N11, are respectively input. It consists of a sense amplifier 13 to be described, the operation thereof is as follows.

At the time of reading, the read signal READ is generated by the mode state machine 17 and applied to the select gate of the reading reference cell M12. At this time, the reading reference cell M12 is turned on and the sense amplifier 13 is turned on. ) And read operation is performed.

In the program confirmation, the program confirmation signal PGMV is applied from the mode state machine 17 to the select gate of the program confirmation reference cell M11. The reference cell M11 is turned on, and thus, the drain of the program check reference cell M11 and the sense amplifier 13 are connected to each other, thereby sensing. In this case, the program confirmation voltage is applied to the control gate of the cell array by a voltage higher than the read voltage to secure a margin. However, in the present invention, a voltage lower than the read voltage is applied to the control gate of the reference cell. A read voltage is applied to the control gate of the array.

The erase check operation is operated in the same manner as described above, and the erase check voltage is generated higher than the read voltage so that the reference cell current flows more than the read operation, so that the margin when the sense amplifier 13 reads the data of the cell array to 1 Will have In particular, since erasing is performed in units of chips or sectors, a single-bit erasing confirmation reference is generated unlike the conventional method of generating a confirmation voltage and applying a voltage to the corresponding control gate of the cell array. The voltage is applied only to the control gate of the cell. Therefore, the voltage transition time of the control gate is greatly shortened. In addition, since the select gate of the reference cell is not connected to the word line and is independent as in the conventional method, it can be easily controlled without using a complex mux circuit.

As described above, according to the present invention, the reference cell is composed of a single bit, not a cell array type, the word line is biased independently of the word line of the main cell, and the control gate of the main cell is provided. By applying to the control gate of the reference cell without applying the confirmation voltage to the cell, the layout of the cell is reduced during erasing, and the circuit configuration is simplified since the drive capability of the confirmation voltage generating circuit is not required to be large. In addition, the recovery time for charging and discharging the control gate is greatly reduced in order to make the normal read mode from the confirmation mode, which is excellent in shortening the overall program and erase time.

Claims (3)

A plurality of reference cells composed of a single bit, a mode state machine for supplying respective mode data to select gates of the plurality of reference cells, and a plurality of voltage generations for supplying respective data to control gates of the reference cell A main cell having a circuit, a select gate for inputting data of an X-decoder and a source connected to ground, a selection transistor for inputting data of the Y-decoder, a resistor connected to a power supply voltage, and a reference cell And a sense amplifier for inputting a node, which is a connection point with a drain, and a node, which is a connection point with a resistor connected to the power supply and a drain of a main cell via the selection transistor, respectively. The sensing circuit of claim 1, wherein the mode state machine is configured to independently bias the select gates of the plurality of reference cells and the word lines of the main cells. The sensing circuit of claim 1, wherein the plurality of voltage generation circuits comprise a program check voltage generation circuit, a read voltage generation circuit, and an erase confirmation voltage generation circuit.