KR0172234B1 - Control apparatus of the frequency of self-refresh - Google Patents
Control apparatus of the frequency of self-refresh Download PDFInfo
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- KR0172234B1 KR0172234B1 KR1019950006320A KR19950006320A KR0172234B1 KR 0172234 B1 KR0172234 B1 KR 0172234B1 KR 1019950006320 A KR1019950006320 A KR 1019950006320A KR 19950006320 A KR19950006320 A KR 19950006320A KR 0172234 B1 KR0172234 B1 KR 0172234B1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40626—Temperature related aspects of refresh operations
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4068—Voltage or leakage in refresh operations
Abstract
본 발명은 반도체 장치의 셀프 리프레쉬 주기 조절장치에 관한 것으로, 셀의 누설전류로 온도 변화를 감지하는 온도 검출기의 출력을 이용하여 온도에 따른 데이타 유지시간의 변화를 고려하여 셀프 리프레쉬 주기를 조절할 수 있도록 함으로써, 불필요한 전력소비를 억제한 저소비 전력의 칩을 구현할 수 있는 효과가 있다.The present invention relates to a self-refresh cycle control device of a semiconductor device, so that the self-refresh cycle can be adjusted in consideration of a change in data retention time according to temperature using an output of a temperature detector that detects a temperature change by a leakage current of a cell. By doing so, there is an effect that can implement a chip of low power consumption in which unnecessary power consumption is suppressed.
Description
제1도는 종래의 셀프 리프레쉬 주기 조절장치의 블럭도.1 is a block diagram of a conventional self refresh cycle control device.
제2도는 제1도에 도시된 온도 검출기의 회로도.2 is a circuit diagram of the temperature detector shown in FIG.
제3도는 본 발명의 실시예에 따른 셀프 리프레쉬 주기 조절장치의 블럭도.3 is a block diagram of a self refresh cycle control apparatus according to an embodiment of the present invention.
제4a도 ∼ 제4c도는 제3도에 도시된 누설전류 발진기의 회로도 및 단면도.4A to 4C are circuit diagrams and cross-sectional views of the leakage current oscillator shown in FIG.
제5도는 제3도에 도시된 온도 검출기의 회로도.5 is a circuit diagram of the temperature detector shown in FIG.
제6도는 제3도에 도시된 셀프 리프레쉬 주기 발진기의 상세도.6 is a detailed view of the self refresh cycle oscillator shown in FIG.
제7도는 제6도에 도시된 주파수 드라이버의 회로도.7 is a circuit diagram of the frequency driver shown in FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10, 21 : 온도 검출기 11 : 제1 링 오실레이터10, 21: temperature detector 11: first ring oscillator
12 : 제2 링 오실레이터 13,22 : 셀프 리프레쉬 주기 발진기12: second ring oscillator 13,22: self-refresh cycle oscillator
20 : 누설 전류 발진기 30 : 링 오실레이터20 leakage current oscillator 30 ring oscillator
31∼33 : 주파수 드라이버31 to 33: frequency driver
본 발명은 반도체 장치의 셀프 리프레쉬 주기조절장치에 관한 것으로, 보다 상세하게는 셀의 누설 전류량에 따라 셀프 리프레쉬 주기를 조절할 수 있도록 함으로써 전류 소모를 줄인 셀프 리프레쉬 주기 조절장치에 관한 것이다.The present invention relates to a self-refresh cycle control device of a semiconductor device, and more particularly, to a self-refresh cycle control device to reduce the current consumption by being able to adjust the self-refresh cycle according to the leakage current of the cell.
반도체 기억소자인 디램(DRAM)은 하나의 캐패시터(capacitor)와 하나의 트랜지스터로 셀이 구성되어 있기 때문에, 소자가 데이타 리드/라이트(read/write) 동작을 수행하지 않는 스탠바이 상태로 칩을 일정시간 이상 방치하게 되면 셀에 저장된 전하가 셀 플레이트(cell plate) 등으로 방전되어 셀 데이타가 파괴되는 단점이 있으므로, 디램 셀의 데이타를 보존하기 위해서는 일정 시간마다 셀 데이타를 재저장하는 리프레쉬 동작을 하게 된다.DRAM, a semiconductor memory device, is composed of one capacitor and one transistor, so that the chip is in a standby state in which the device does not perform data read / write operations. If the battery is left unattended, the charge stored in the cell is discharged to the cell plate and the cell data is destroyed. Therefore, in order to preserve the data of the DRAM cell, a refresh operation is performed to restore the cell data at regular intervals. .
그러나, 상기 리프레쉬 동작시는 많은 양의 전력이 소모되므로 이를 감소시키기 위하여, 통상적인 씨비알 모드(CBR mode)에서 수십 ㎲가 경과하면 칩 내부의 카운터가 동작하여 칩의 모든 셀들을 순차적으로 리프레쉬하는 셀프 리프레쉬 기능이 점차 디램 칩에 탑재되고 있다.However, since a large amount of power is consumed during the refresh operation, in order to reduce this, in a typical CBR mode, when several tens of powers pass, a counter inside the chip operates to refresh all the cells of the chip sequentially. Self-refreshing features are increasingly embedded in DRAM chips.
하지만, 상기 셀프 리프레쉬의 경우라 하더라도 리프레쉬 한 주기당 많은 셀의 데이타가 재증폭되기 때문에 많은 양의 전력 소모가 발생하게 되며, 리프레쉬 동작을 수행하는 주기에 따라 그 전력 소모가 결정된다.However, even in the case of the self refresh, since a large amount of data is re-amplified in one refresh cycle, a large amount of power is consumed, and the power consumption is determined according to the cycle of performing the refresh operation.
일반적으로 상기 전력 소모에 영향을 미치는 리프레쉬 주기는 셀 데이타 유지시간에 의해 결정되며, 셀의 데이타 유지시간은 칩의 온도 변화에 밀접한 연관이 있고 보통 고온에서 데이타 유지시간이 가장 짧다.In general, the refresh period affecting the power consumption is determined by the cell data holding time, and the data holding time of the cell is closely related to the temperature change of the chip, and usually the shortest data holding time at high temperature.
이에 따라, 기존의 셀프 리프레쉬의 동작 주기는 고온에서의 셀의 데이타 유지시간을 고려하여 짧게 구현되므로, 칩이 저온으로 동작하는 경우에는 셀 데이타 유지시간이 길어지는데도 불구하고 셀프 리프레쉬 주기는 여전히 짧아서 필요 이상의 전력 소모를 유발하는 문제가 있었다.Accordingly, since the operation cycle of the conventional self refresh is shortened in consideration of the data retention time of the cell at high temperature, the self refresh cycle is still short when the chip data is operated at low temperature even though the cell data retention time is long. There was a problem causing more power consumption than necessary.
상기 문제점을 해결하기위해 종래의 셀프 리프레쉬 주기 조절장치에서는 온도에 따라 저항성분이 다른 소자를 사용하여 온도를 검출한 다음 셀프 리프레쉬 주기를 조절하도록 하였다.In order to solve the above problem, the conventional self refresh cycle control device detects a temperature using an element having a different resistance component according to temperature, and then adjusts the self refresh cycle.
제1도는 종래의 셀프 리프레쉬 주기 조절장치의 블럭도로서, 칩의 온도 변화를 감지하여 일정신호를 출력하는 온도 검출기(10)와, 상기 온도 검출기(10)로부터의 출력신호에 의해 제어되고 각각 주기가 다른 펄스신호를 일정하게 출력하는 제1, 제2 링 오실레이터(11,12)와, 상기 제1 및 제2 링 오실레이터(11,12)로부터 출력된 신호에 의해 셀프 리프레쉬 주기를 발생시키는 셀프 리프레쉬 주기 발진기(13)로 구성된다.1 is a block diagram of a conventional self-refresh period adjusting device, which is controlled by a temperature detector 10 for detecting a temperature change of a chip and outputting a constant signal, and controlled by an output signal from the temperature detector 10. Refresh to generate a self refresh cycle by the signals output from the first and second ring oscillators 11 and 12 and the signals output from the first and second ring oscillators 11 and 12. It consists of a periodic oscillator 13.
제2도는 제1도에 도시된 온도 검출기(10)의 회로도를 도시한 것으로, 온도변화에 따라 저항의 변화가 적은 폴리(poly) 저항(R1,R4)과, 온도변화에 따라 저항의 변화가 큰 액티브(active) 저항(R2,R3)을 이용하여 분압된 노드(N1,N2)의 전압을 차동증폭함으로써, 온도를 감지하는 구조로 되어있다.FIG. 2 is a circuit diagram of the temperature detector 10 shown in FIG. 1. The poly resistors R1 and R4 having a small change in resistance with a temperature change and a change in resistance with a temperature change are shown in FIG. The temperature is sensed by differentially amplifying the voltages of the divided nodes N1 and N2 using large active resistors R2 and R3.
상기 온도 검출기(10)의 출력신호로 동작하는 상기 제1 및 제2 링 오실레이터(11,12)는 서로 다른 주기를 갖고 있으며, 적어도 두 개 이상으로 구성되어 온도가 일정 이하의 경우에는 상기 제1 링 오실레이터(11)를 동작하여 리프레쉬 신호를 발생시키고, 온도가 일정 이상의 경우에는 상기 제1 링 오실레이터(11) 및 제2 링 오실레이터(12)를 차례로 동작시킴으로써 온도변화에 따라 리프레쉬 주기를 조절할 수가 있다.The first and second ring oscillators 11 and 12, which operate as output signals of the temperature detector 10, have different periods, and are composed of at least two or more, and the first and second ring oscillators 11 and 12 have a predetermined period. The ring oscillator 11 is operated to generate a refresh signal, and when the temperature is above a certain level, the first ring oscillator 11 and the second ring oscillator 12 are operated in sequence to adjust the refresh cycle according to the temperature change. .
상기와 같이 온도의 변화에 따라 리프레쉬 주기를 조절하는 방법으로 종래의 경우에서는 온도에 따라 저항 성분이 다른 두 저항소자를 이용하여 구현하였으나, 본 발명에서는 셀에서 생기는 누설 전류량을 검출하고 이에 따른 온도의 변화에 따라 리프레쉬 주기를 조절할 수 있도록 하고자 한다.As described above, the refresh cycle is adjusted according to the change in temperature. However, in the related art, two resistive elements having different resistance components according to the temperature are implemented. However, in the present invention, the amount of leakage current generated in the cell is detected and thus We want to be able to adjust the refresh cycle according to the change.
따라서, 본 발명에서는 셀의 누설 전류량에 따라 셀프 리프레쉬 주기를 조절할 수 있도록 한 셀프 리프레쉬 주기 조절장치를 제공하는데에 그 목적이 있다.Accordingly, an object of the present invention is to provide a self-refresh cycle control device capable of adjusting the self-refresh cycle according to the leakage current of the cell.
상기 목적을 달성하기 위하여, 본 발명의 셀프 리프레쉬 주기 조절장치는 셀프 리프레쉬 동작을 위해 일정한 주기를 갖는 펄스신호를 출력하는 링 발진기와, 셀에 저장된 전하가 셀 플레이터등으로 방전되어 셀 데이타가 파괴될때 생기는 누설전류를 감지한 신호를 출력하기 위한 누설전류 감지 수단과, 상기 누설전류 감지 수단으로부터의 출력과 온도에 따라 각각 저항성분이 다른 두 저항소자로부터 분주된 기준전압을 비교·증폭하여 칩의 온도 변화를 감지하는 온도 검출수단과, 상기 온도 검출수단으로부터 출력된 신호에 의해 상기 링 오실레이터의 출력을 적정 비율로 분주하여 리프레쉬 주기를 변화시키는 주파수 드라이버 수단을 구현하였다.In order to achieve the above object, the self-refresh period adjusting device of the present invention is a ring oscillator for outputting a pulse signal having a certain period for the self-refresh operation, and the charge stored in the cell is discharged to the cell plate, etc. to destroy the cell data The temperature of the chip by comparing and amplifying the leakage current detection means for outputting a signal that detects the leakage current generated when the signal is generated, and a reference voltage divided by two resistance elements having different resistance components according to the output and the temperature from the leakage current detection means. Temperature detection means for detecting a change and a frequency driver means for varying the refresh period by dividing the output of the ring oscillator at an appropriate ratio by the signal output from the temperature detection means.
이하, 첨부된 도면을 참조하여 본 발명의 일실시예를 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
제3도는 본 발명의 실시예에 따른 셀프 리프레쉬 주기 조절장치의 블럭도로서, 셀에 저장된 전하가 셀 플레이트등으로 방전되어 셀 데이타가 파괴될 때 생기는 누설 전류량을 검출하는 누설전류 발진기(20)와, 상기 누설전류 발진기로부터의 출력된 출력신호와, 온도에 따라 각각 저항성분이 다른 두 저항소자로부터 분주되어 출력된 기준전압을 비교·증폭하여 칩의 온도 변화를 감지하는 온도 검출기(21)와, 상기 온도 검출기로부터의 출력된 신호를 이용하여 셀프 리프레쉬 주기를 조절하는 셀프 리프레쉬 주기 발진기(22)를 구비한다.3 is a block diagram of a self-refresh cycle control device according to an embodiment of the present invention, the leakage current oscillator 20 for detecting the amount of leakage current generated when the charge stored in the cell is discharged to the cell plate, and the cell data is destroyed; A temperature detector 21 for comparing and amplifying the output signal output from the leakage current oscillator and a reference voltage output from two resistance elements having different resistance components according to temperature, and amplifying the temperature change of the chip; A self refresh cycle oscillator 22 is used to adjust the self refresh cycle using the output signal from the temperature detector.
제4a도 내지 제4c도는 제3도에 도시된 누설전류 발진기(20)의 회로도 및 단면도를 나타낸 것으로, 디램 셀에서의 누설 전류량을 감지할 수 있도록 구현하였다.4A to 4C show a circuit diagram and a cross-sectional view of the leakage current oscillator 20 shown in FIG. 3 and implemented to detect the amount of leakage current in the DRAM cell.
상기 제4a도는 누설전류 발진기(20)의 회로도로서, 전원전압(Vcc) 및 노드(N3) 사이에 접속된 저항(R5)과, 상기 노드(N3) 및 기판전위(Vbb) 사이에 접속된 다이오드(D1)로 구성되어, 상기 노드(N3)에서의 분압된 전위를 출력한다. 상기 다이오드(D1)가 역바이어스 상태에서 누설전류를 만들어낼 수 있다. 상기 출력전위(N3)로 발생하는 전위는 누설전류에 비례하는, 즉 V = IR에 해당하는 전위차를 유발하는데 여기서는 전류가 누설에 의한 전류이므로 이 값이 온도에 따라 변하게 되므로, 출력전위는 온도에 따라 변하게 된다.(즉, 상기 누설전류는 온도와 밀접한 관련을 갖고 있어서 온도가 10도 증가하면 상기 누설 전류는 두 배로 증가하는 특징을 가지고 있다.)FIG. 4A is a circuit diagram of the leakage current oscillator 20. The resistor R5 connected between the power supply voltage Vcc and the node N3 and the diode connected between the node N3 and the substrate potential Vbb. (D1), the divided potential at the node N3 is output. The diode D1 may generate a leakage current in a reverse bias state. The potential generated by the output potential N3 causes a potential difference that is proportional to the leakage current, that is, V = IR. Here, since the current is a leakage current, this value changes with temperature. (I.e., the leakage current is closely related to temperature, so that the leakage current doubles as the temperature increases by 10 degrees.)
상기 제4b도는 누설전류 발진기(20)의 단면도로서, 셀에서의 누설전류에 비례하는 값을 얻도록 P형 기판에 N-웰(Well)로 구성되며, 상기 P형 기판 및 N-웰 상에 도우핑된 P+형 불순물 확산 영역에 기판전위(Vbb)가 인가되고 상기 N-웰 상에 도우핑된 N+형 불순물 확산 영역으로는 저항(R5)을 통하여 전원전위(Vcc)가 인가되는 구조이다.FIG. 4B is a cross-sectional view of the leakage current oscillator 20, which is composed of N-wells in a P-type substrate to obtain a value proportional to the leakage current in the cell, and is formed on the P-type substrate and the N-wells. The substrate potential Vbb is applied to the doped P + type impurity diffusion region and the power source potential Vcc is applied to the N + type dopant diffusion region doped on the N-well through the resistor R5. to be.
그리고, 상기 제4c도는 P형 기판위에 N-웰을 도우핑하고, 상기 N-웰 상에 다시 P-웰을 도우핑한 다음, 상기 P-웰 상에 N+형 불순물 확산 영역과 P+형 불순물 확산 영역을 도우핑하고 상기 N+형 불순물 확산 영역으로 전원전압(Vcc)이 인가되고 상기 P+형 불순물 확산 영역으로는 저항(R5)을 통하여 기판 전위(Vbb)가 인가되는 구조이다.In FIG. 4C, the N-well is doped on the P-type substrate, the P-well is doped again on the N-well, and then the N + -type impurity diffusion region and the P + -type are formed on the P-well. the doped with the impurity diffusion region and the N + type diffusion to a power supply voltage (Vcc) is applied to the region P + type diffusion region is a structure to which the substrate voltage (Vbb) through a resistor (R5).
제5도는 제3도에 도시된 온도 검출기의 회로도로서, 전원전압(Vcc) 및 노드(N4) 사이에 접속되며 게이트가 상기 노드(N4)에 연결된 PMOS트랜지스터(Q7)와, 전원전압(Vcc) 및 노드(N5) 사이에 접속되며 게이트가 상기 노드(N4)에 연결된 PMOS트랜지스터(Q8)와, 상기 노드(N4) 및 노드(N6) 사이에 접속되며 게이트가 상기 누설전류 발진기(21)의 출력노드(N3)에 연결된 NMOS트랜지스터(Q9)와, 상기 노드(N5) 및 상기 노드(N6) 사이에 접속되며 게이트가 노드(N7)에 연결된 NMOS트랜지스터(Q10)와, 상기 노드(N6) 및 접지 전압(Vss) 사이에 접속되며 게이트에 인에이블 신호(en)가 인가되는 NMOS트랜지스터(Q11)와, 전원전압(Vcc) 및 상기 노드(N7) 사이에 접속된 저항(R6)과, 상기 노드(N7) 및 접지전압(Vss) 사이에 접속된 저항(R7)과, 상기 노드(N5)의 신호를 출력하는 출력단자(S1)로 구성된다.FIG. 5 is a circuit diagram of the temperature detector shown in FIG. 3, which is connected between a power supply voltage Vcc and a node N4 and whose gate is connected to the node N4, and a power supply voltage Vcc. And a PMOS transistor Q8 connected between the node N5 and a gate connected to the node N4, and connected between the node N4 and the node N6, the gate of which is output of the leakage current oscillator 21. NMOS transistor Q9 connected to node N3, NMOS transistor Q10 connected between node N5 and node N6 and whose gate is connected to node N7, and node N6 and ground. An NMOS transistor Q11 connected between a voltage Vss and an enable signal en is applied to a gate, a resistor R6 connected between a power supply voltage Vcc and the node N7, and the node (N). Resistor R7 connected between N7) and ground voltage Vss, and an output terminal S1 for outputting the signal of node N5.
상기 누설전류 발진기(20)의 출력노드에는 다수개의 온도 검출기(21)가 설치되어 상기 누설전류 발진기(20)에서 발생한 누설전류를 이용하여 온도를 감지할 수 있다.A plurality of temperature detectors 21 are installed at the output node of the leakage current oscillator 20 to sense a temperature using the leakage current generated by the leakage current oscillator 20.
상기 누설전류 발진기(20)의 출력노드(N3)의 전위가 온도의 변화에 따라 저항성분이 다른 두 개의 저항소자(R6, R7)로 이루어진 분압기로부터 분압된 노드(N7)의 전위보다 크게 되면, 상기 출력노드(N3)가 게이트에 연결된 상기 NMOS트랜지스터(Q9)를 크게 턴-온시킴으로써 PMOS트랜지스터(Q7 및 Q8)을 턴-온시킨다. 따라서 상기 노드(N5)의 출력단의 전위는 높아지게 된다. 반대로 상기 누설전류 발진기(20)의 출력노드(N3)의 전위가 상기 분압기의 출력노드(N7)의 전위보다 작으면, 상기 NMOS트랜지스터(Q10)가 크게 턴-온되어 상기 출력단(N5)의 전위를 낮추게 된다.When the potential of the output node N3 of the leakage current oscillator 20 is greater than the potential of the node N7 divided from the voltage divider consisting of two resistance elements R6 and R7 having different resistance components according to the temperature change, The output node N3 turns on the PMOS transistors Q7 and Q8 by greatly turning on the NMOS transistor Q9 connected to the gate. Therefore, the potential of the output terminal of the node N5 becomes high. On the contrary, if the potential of the output node N3 of the leakage current oscillator 20 is smaller than the potential of the output node N7 of the voltage divider, the NMOS transistor Q10 is turned on greatly and thus the potential of the output terminal N5. Will be lowered.
제6도는 제3도에 도시된 셀프 리프레쉬 주기 발진기의 상세도로서, 일정한 주기의 펄스신호를 발생시키는 링 오실레이터(30)와, 상기 링 오실레이터(30)로부터의 출력 신호의 주기를 n배 늘린 신호를 발생시키는 다수의 주파수 드라이버 회로(31∼33)로 구성된다.6 is a detailed view of the self-refresh cycle oscillator shown in FIG. 3, in which a ring oscillator 30 generating a pulse signal of a constant cycle and a signal in which the period of the output signal from the ring oscillator 30 are increased n times. And a plurality of frequency driver circuits 31 to 33 for generating the?
그 동작은 고온에서는 상기 링 오실레이터(30)의 출력 신호가 직접 리프레쉬 주기가 되고, 상온 또는 상대적인 저온에서는 상기 링 오실레이터(30)의 n배 주기를 갖는 신호가 상기 주파수 드라이버 회로(31∼33)에서 만들어져서 리프레쉬 주기가 된다.In operation, the output signal of the ring oscillator 30 is a direct refresh period at a high temperature, and a signal having an n times period of the ring oscillator 30 is at the frequency driver circuits 31 to 33 at room temperature or relative low temperature. It is created and becomes a refresh cycle.
제7도는 제6도에 도시된 주파수 드라이버들 중 하나의 주파수 드라이버(31)의 회로를 나타낸 것으로, 상기 링 오실레이터(30)의 출력신호(r.o) 및 입력신호(fn)(첫번째 입력신호는 Vcc)를 입력하여 논리조합된 신호를 노드(N9)로 출력하는 NAND게이트(G1)와, 상기 노드(N9) 및 온도 검출기의 출력신호(Sn)를 입력하여 논리조합된 신호를 노드(N10)으로 출력하는 NAND게이트(G2)와, 상기 노드(N10) 및 노드(N11) 사이에 접속된 인버터(G5)와, 상기 노드(N10)에 NMOS의 게이트가, 상기 노드(N11)에 PMOS의 게이트가 접속되며 노드(N12)의 신호를 노드(N13)으로 전달하는 전달트랜지스터(Q12)와, 상기 노드(N13) 및 노드(N14) 사이에 병렬접속된 인버터(G6,G7)와, 상기 노드(N10)에 PMOS의 게이트가, 상기 노드(N11)에 NMOS의 게이트가 접속되며 상기 노드(N14)의 신호를 노드(N15)로 전달하는 전달트랜지스터(Q13)와, 상기 노드(N15) 및 노드(N16) 사이에 병렬접속된 인버터(G8,G9)와, 상기 노드(N16) 및 상기 노드(N12) 사이에 접속된 인버터(G10)와, 상기 노드(N16)로 부터 리프레쉬 주기를 출력하는 출력단자와, 상기 노드(N13)의 신호와 입력신호(fn)를 입력하여 논리조합된 신호를 노드(N17)로 출력하는 NAND게이트(G3)와, 상기 노드(N17) 및 노드(N18) 사이에 접속된 인버터(G4)와, 상기 노드(N18)로부터 카운터된 입력신호를 출력하는 단자로 구성된다.FIG. 7 shows a circuit of one frequency driver 31 of the frequency drivers shown in FIG. 6, in which the output signal ro and the input signal fn of the ring oscillator 30 (the first input signal is Vcc). NAND gate G1 for outputting the logically combined signal to the node N9, and the output signal Sn of the node N9 and the temperature detector are inputted to the node N10. An output NAND gate G2, an inverter G5 connected between the node N10 and the node N11, a gate of an NMOS at the node N10, and a gate of a PMOS at the node N11. A transfer transistor Q12 which is connected and transmits a signal of the node N12 to the node N13, inverters G6 and G7 connected in parallel between the node N13 and the node N14, and the node N10. Is a PMOS gate connected to the node N11, and a transfer transistor for transmitting a signal of the node N14 to the node N15. The inverter Q13, the inverters G8 and G9 connected in parallel between the node N15 and the node N16, the inverter G10 connected between the node N16 and the node N12, An output terminal for outputting a refresh period from the node N16, a NAND gate G3 for inputting a signal of the node N13 and an input signal fn, and outputting a logically combined signal to the node N17; And an inverter G4 connected between the node N17 and the node N18, and a terminal for outputting an input signal counted from the node N18.
상기 셀프 리프레쉬 주기 발진기(22)는 상기 각각의 주파수 드라이버 회로(31∼33)로 들어오는 온도 검출기(21)의 출력신호(Sn)에 의해 제어되어 자기 자신으로 들어오는 입력신호(fn)의 반주기의 신호를 출력하게 된다. 따라서 상기 주파수 드라이버 회로(31)로 입력되는 상기 온도 검출기(21)의 출력신호(Sn)에 의해 리프레쉬 주기가 조절되는데, 고온일 경우에는 상기 링 오실레이터(30)의 출력신호(r.o)가 직접 리프레쉬 주기가 되어 상기 리프레쉬 주기가 빨라지게 되고, 상온 또는 상대적인 저온에서는 상기 온도 검출기(21)의 출력신호(Sn)에 의해 선택된 주파수 드라이버 회로에 의해 리프레쉬 주기가 늦어지게 된다.The self-refresh period oscillator 22 is controlled by the output signal Sn of the temperature detector 21 entering each of the frequency driver circuits 31 to 33, and the half-cycle signal of the input signal fn coming into itself. Will print Therefore, the refresh cycle is controlled by the output signal Sn of the temperature detector 21 input to the frequency driver circuit 31. When the temperature is high, the output signal ro of the ring oscillator 30 is directly refreshed. The refresh cycle is quickened by the cycle, and the refresh cycle is delayed by the frequency driver circuit selected by the output signal Sn of the temperature detector 21 at room temperature or relative low temperature.
이상에서 설명한 바와 같이, 누설전류로 칩의 온도 변화를 감지하여 일정한 신호를 출력하는 온도 검출기를 포함하는 본 발명의 셀프 리프레쉬 주기 조절장치를 디램소자의 내부에 구현하게 되면 온도 변화에 따른 데이타 유지시간의 변화를 고려하여 리프레쉬의 주기를 적절히 조절할 수 있으므로 불필요한 전력소비를 억제한 저소비 전력의 칩을 구현할 수 있는 효과가 있다.As described above, if the self-refresh cycle control device of the present invention includes a temperature detector for detecting a temperature change of the chip with a leakage current and outputting a constant signal, the data holding time according to the temperature change is realized. Since the refresh cycle can be adjusted appropriately in consideration of the change of, it is possible to implement a chip of low power consumption in which unnecessary power consumption is suppressed.
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| KR0129197B1 (en) * | 1994-04-21 | 1998-10-01 | 문정환 | A refresh control circuit of memory cell array |
| KR0179097B1 (en) * | 1995-04-07 | 1999-04-15 | 김주용 | Data read and write method |
-
1995
- 1995-03-24 KR KR1019950006320A patent/KR0172234B1/en not_active IP Right Cessation
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1996
- 1996-03-21 US US08/619,221 patent/US5680359A/en not_active Expired - Lifetime
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| KR100803352B1 (en) * | 2006-06-12 | 2008-02-14 | 주식회사 하이닉스반도체 | Apparatus and Method for Controlling Refresh of Semiconductor Memory |
| US7474580B2 (en) | 2006-06-12 | 2009-01-06 | Hynix Semiconductor Inc. | Apparatus and method for controlling refresh operation of semiconductor integrated circuit |
| KR100834404B1 (en) * | 2007-01-03 | 2008-06-04 | 주식회사 하이닉스반도체 | Semiconductor memory device with refresh-signal generator and method for the operation |
| US7672184B2 (en) | 2007-01-03 | 2010-03-02 | Hynix Semiconductor Inc. | Semiconductor memory device with refresh signal generator and its driving method |
| US11868153B2 (en) | 2021-09-07 | 2024-01-09 | SK Hynix Inc. | Semiconductor integrated circuit device capable of compensating for current leakage and method of operating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960035634A (en) | 1996-10-24 |
| US5680359A (en) | 1997-10-21 |
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