JP3359618B2 - Semiconductor integrated circuit and power supply circuit with delay time correction function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention has a delay time correction function.
And a power supply circuit .

[0002]

2. Description of the Related Art In a dynamic random access memory (DRAM), which is one of the semiconductor memory devices, an internal step-down level Vint, a word line boost level VPP, and a bit line are used in addition to a power supply voltage level VCC externally supplied. Various voltage levels, such as a precharge level Vpr and a substrate bias level VBB, are required to ensure reliability and reduce current consumption. In the case of a 16 Mbit DRAM, for example, V
With respect to CC = 5V (based on the ground potential VSS = 0V), Vint = 3.3V, VPP = 4.5V, Vpr = 1.6.
5V, VBB = about -2V.

Conventionally, to obtain these voltage levels,
MOSF as disclosed in JP-A-63-244217
A power supply voltage conversion circuit using an ET (field effect MOS transistor) has been used.

When a plurality of circuit blocks are operated synchronously in a semiconductor integrated circuit such as a DRAM, various delay circuits are used for adjusting the timing between the circuit blocks. Specifically, the case of a DRAM will be described. For example, a row decoder for selecting a memory cell via a word line and a minute potential read out from the memory cell selected by the row decoder onto a bit line are provided in its peripheral circuit. And a timing circuit for adjusting the timing of activating the sense amplifier so as to amplify the signal. The timing circuit delays the activation of the sense amplifier from the selection of the word line by the row decoder. This timing circuit can be constituted by a normal inverter chain comprising a plurality of stages of inverters each constituted by only two MOSFETs. However, in such a simple timing circuit, the delay time has a large temperature dependency.

To reduce the temperature dependency of the delay time, a CR delay circuit using a time constant determined by a resistor and a capacitor has been devised. As an example, a CR described in JP-A-63-327715 is disclosed.
Delay circuit and "A New CR-Delay Circui" by Yoji Watanabe
t Technology for High-Density and High-Speed DRAM '
s (New CR delay circuit technology for high-density and high-speed DRAM) ", IEEE J. Solid-State Circuits, vol. 24,
pp. 905-910, 1989.

FIG. 40 shows a configuration example of a semiconductor integrated circuit using a conventional CR delay circuit. In the semiconductor integrated circuit shown in the figure, a peripheral circuit 302 includes a plurality of stages of CR delay circuits 301. In the CR delay circuit 301, 3
03 is a comparator circuit, 304 is a P-type MOSFET,
305 is an N-type MOSFET, P1 is an input signal, P2 is an output signal, R1 is a charging resistor, R2 and R3 are voltage dividing resistors, and C is a capacitor. Each CR delay circuit 301
, A voltage VCC obtained by stabilizing an externally supplied power supply voltage is supplied as an internal power supply voltage by a constant voltage generation circuit 306.

According to this configuration, each CR delay circuit 301
Is dependent only on a constant determined by the geometric dimensions of each of the resistance elements R1 to R3 and the capacitor element C, so that the temperature dependence of the delay time is reduced.

[0008]

In the conventional power supply voltage conversion circuit, although the fluctuation of the output voltage with respect to the fluctuation of the external power supply voltage level VCC is suppressed, the threshold voltage of the MOSFET fluctuates due to the temperature change. There has been a problem that the output voltage sometimes fluctuates.

In addition, if the conventional CR delay circuit is used for all portions of the peripheral circuit of the semiconductor integrated circuit that require a delay, the peripheral circuit is compared with the case where a delay circuit composed of an ordinary inverter chain is used. However, there is a problem that the layout area becomes large.

An object of the present invention is to automatically correct a delay time.
It is an object of the present invention to provide a semiconductor integrated circuit and a power supply circuit having the function of:

[0011]

Means for Solving the Problems The inventions of claims 1 to 9 are:
The present invention relates to a semiconductor integrated circuit including a peripheral circuit and a delay time correction circuit for correcting a delay time of the peripheral circuit.

More specifically, a first aspect of the present invention is a first delay circuit for delaying a pulse signal, and a first delay circuit for delaying the same pulse signal as the pulse signal supplied to the first delay circuit. Wherein the logic circuit has the same delay time temperature dependency as the peripheral circuit but different from the first delay circuit, and the delay time of the pulse signal at a reference temperature is the same as that of the first delay circuit. The potential of the second delay circuit set to match and the potential of the output line used as the supply line of the stabilized power supply voltage to each of the second delay circuit and the peripheral circuit can be changed according to the control signal. A constant voltage generating circuit for holding a constant value; and a delay time of the second delay circuit being longer than a delay time of the first delay circuit based on respective output signals of the first and second delay circuits. A promotion signal if it becomes And a delay time difference detecting circuit for outputting a suppression signal when the delay time of the second delay circuit is smaller than the delay time of the first delay circuit. A control signal is output to the constant voltage generation circuit so as to increase the potential of the output line each time a signal is received and to decrease the potential of the output line each time a suppression signal is received from the delay time difference detection circuit. And a control circuit for controlling the delay time.

According to a second aspect of the present invention, the delay time correction circuit employs a configuration further including a pulse generation circuit for supplying a common pulse signal to the first and second delay circuits. .

According to a third aspect of the present invention, the delay time difference detection circuit includes a circuit for outputting first and second detection signals as the promotion signal and the suppression signal. The detection signal has a pulse which transits at the same time, and the second signal is transmitted when the delay time of the second delay circuit is longer than the delay time of the first delay circuit.
If the pulse width of the detection signal is larger than the pulse width of the first detection signal, and the delay time of the second delay circuit is smaller than the delay time of the first delay circuit,
Is determined to be smaller than the pulse width of the first detection signal.

According to a fourth aspect of the present invention, the control circuit includes a circuit for outputting a plurality of logic signals as the control signal, and the control circuit outputs a logic signal having a predetermined logic level among the plurality of logic signals. The number is changed according to the difference between the pulse widths of the first and second detection signals output from the delay time difference detection circuit.

According to a fifth aspect of the present invention, the second delay circuit has a delay phase with respect to a reference signal whose delay time at a reference temperature is set to coincide with an output signal of the first delay circuit. A circuit is provided for outputting a first output signal and a second output signal having a phase advanced with respect to the reference signal. In addition, the delay time difference detection circuit is configured to control the first delay circuit in accordance with the input timing of the first and second output signals of the second delay circuit with respect to the input timing of the output signal of the first delay circuit. A first detection signal indicating whether there is a difference between the delay time and the delay time of the second delay circuit, and a second detection indicating which one of the first and second delay circuits has a longer delay time. And a circuit for outputting a signal as the promotion signal and the suppression signal, wherein the delay time of the second delay circuit is the first
When the delay time of the second delay circuit is longer than the delay time of the second delay circuit, the first detection signal indicating the existence of the delay time difference and the second detection signal having the first logic level are different from each other. When the delay time is smaller than the delay time of the first delay circuit, a first detection signal indicating the existence of a delay time difference and a second detection signal having a second logic level are output from the delay time difference detection circuit. did.

According to a sixth aspect of the present invention, the delay time difference detection circuit has a logic that uses the output signal of the first delay circuit and the first and second output signals of the second delay circuit as input signals. An OR circuit, and a first signal for outputting the first detection signal by latching an output signal of the OR circuit.
And a second circuit for outputting the second detection signal by latching an output signal of the first delay circuit at an output timing of a first detection signal from the first latch circuit. And a latch circuit.

According to a seventh aspect of the present invention, the delay time difference detection circuit includes a first delay circuit and a second delay circuit. A first detection signal indicating which one of the two delay circuits is longer, and a second detection signal indicating whether there is a difference between the delay time of the first delay circuit and the delay time of the second delay circuit. And a circuit for outputting the detection signal as the promotion signal and the suppression signal, and when the delay time of the second delay circuit is longer than the delay time of the first delay circuit, the first logic level is changed. When the first detection signal and the second detection signal indicating the presence of the delay time difference have a delay time of the second delay circuit smaller than the delay time of the first delay circuit, the second logic level A first detection signal having It was that a second detection signal indicative of the presence of a delay time difference are respectively outputted from the delay time difference detecting circuit.

In the invention of claim 8, the delay time difference detection circuit outputs the first detection signal by amplifying a potential difference between output signals of the first and second delay circuits. A monostable multivibrator for outputting the second detection signal having a constant pulse width triggered by a transition of one of the output signals of the first and second delay circuits; and It was decided to adopt a configuration provided with.

According to a ninth aspect of the present invention, the peripheral circuit includes a row decoder for selecting a memory cell via a word line, and the output line of the constant voltage generation circuit is
It is used as a power supply voltage supply line to each of the second delay circuit and the row decoder.

According to a tenth aspect of the present invention, the potential of an output line as a stabilized output voltage used as a common power supply for a plurality of circuit blocks each constituted by a logic circuit on a semiconductor substrate in response to a temperature rise. The present invention relates to a semiconductor integrated circuit configured so that the delay time of each of the plurality of circuit blocks can be kept constant by increasing the delay time.

More specifically, the invention according to claim 10 is the first delay circuit in which the delay time of the pulse signal has a small temperature dependency, and the delay time of the pulse signal at a reference temperature is the first delay circuit.
A second delay circuit having a logic circuit as a temperature monitor set so as to coincide with the delay circuit of the first and second delay circuits according to a difference between a delay time of the first delay circuit and a delay time of the second delay circuit. If the delay time of the second delay circuit is longer than the delay time of the first delay circuit, a promotion signal is output and the delay time of the second delay circuit is equal to the first delay circuit.
A delay time difference detection circuit for outputting a suppression signal when the delay time becomes smaller than the delay time of the delay circuit, and increasing the potential of the output line each time a promotion signal is received from the delay time difference detection circuit, and A constant voltage generation circuit for lowering the potential of the output line each time a suppression signal is received from the time difference detection circuit, wherein the stabilized output voltage on the output line from the constant voltage generation circuit is the second delay This adopts a configuration supplied as power to the circuit.

According to the eleventh aspect of the present invention, the first delay circuit, the second delay circuit, and the delay time difference detection circuit are each disposed on the semiconductor substrate one by one, and the constant voltage generation circuit is connected to the plurality of circuit blocks. Are arranged on the semiconductor substrate so as to be close to each other, and the promotion signal and the suppression signal are respectively transmitted between each of the plurality of constant voltage generation circuits and the delay time difference detection circuit. In this case, two signal lines are provided.

In the twelfth aspect of the present invention, the first and the second
Is arranged substantially at the center of the semiconductor substrate.

According to a thirteenth aspect of the present invention, the first and the second
The delay circuit is disposed near the heat generation center on the semiconductor substrate.

[0026]

[0027]

[0028]

[0029]

[0030]

The invention of claim 14-16, for keeping constant the delay time of the logic circuit by bring in accordance with the potential of the output line as a regulated output voltage used as a power source of the logic circuit to the temperature rise It relates to a power supply circuit.

Specifically, the invention of claim 14 is the first delay circuit in which the delay time of the pulse signal has a small temperature dependency, and the delay time of the pulse signal at the reference temperature is the first delay circuit.
A second delay circuit having a logic circuit as a temperature monitor set so as to match the delay circuit of the first embodiment, and detecting a difference between a delay time of the first delay circuit and a delay time of the second delay circuit And a delay time difference detecting circuit for increasing the potential of the output line when the delay time of the second delay circuit is longer than the delay time of the first delay circuit. For changing the potential of the output line according to the output of the delay time difference detection circuit so as to lower the potential of the output line when the delay time of the first delay circuit becomes shorter than the delay time of the first delay circuit. A constant voltage generating circuit, wherein the stabilized output voltage on the output line from the constant voltage generating circuit is supplied as power to the second delay circuit.

According to a fifteenth aspect of the present invention, the first delay circuit is configured to use a time constant determined by a resistance element and a capacitor element.

According to a sixteenth aspect of the present invention, the delay time difference detection circuit is configured to delay the second delay circuit according to a difference between a delay time of the first delay circuit and a delay time of the second delay circuit. When the time is longer than the delay time of the first delay circuit, a promotion signal is output. When the delay time of the second delay circuit is shorter than the delay time of the first delay circuit, A function of outputting a suppression signal, wherein the constant voltage generation circuit raises the potential of the output line each time it receives a promotion signal from the delay time difference detection circuit and receives a suppression signal from the delay time difference detection circuit It has a function of reducing the potential of the output line each time.

[0035]

In the semiconductor integrated circuit according to the first aspect of the present invention, the output line voltage of the constant voltage generation circuit is controlled so as to eliminate the difference between the delay time of the first delay circuit and the delay time of the second delay circuit. By doing so, the delay time of a peripheral circuit including a delay circuit or the like using the output line voltage as a power supply is corrected. In other words, even if a delay circuit composed of a normal inverter chain is used for a peripheral circuit, the temperature dependence of the delay time is corrected. Reduced. According to the second aspect of the present invention, it is not necessary to supply a special pulse signal for detecting the delay time difference from outside the semiconductor integrated circuit.

According to the third aspect of the present invention, the delay time difference between the first and second delay circuits is converted into the difference between the pulse widths of the first and second detection signals by the delay time difference detection circuit. According to the fourth aspect of the present invention, the first and second signals are controlled by the control circuit.
Is converted into the number of logic signals having a predetermined logic level.

According to the fifth and sixth aspects of the present invention, the first and second outputs having a phase difference between the output signal of the first delay circuit and the output of the second delay circuit. By using the signal, the presence or absence of the delay time difference is detected with a certain range of dead zone. Moreover, the width of the dead zone is changed by setting the phase difference between the first and second output signals of the second delay circuit.

According to the seventh and eighth aspects of the present invention, the use of the amplifying function of the flip-flop and the monostable multivibrator enables the presence or absence of a delay time difference to be detected with high sensitivity.

According to the ninth aspect, the delay characteristics of the row decoder are matched with the delay characteristics of the word line. The delay characteristic of a word line has a small temperature dependency of a CR type determined by its distribution constant. On the other hand, the original delay characteristics of the row decoder have a large temperature dependence of the transistor type.
Therefore, by controlling the power supply voltage of the row decoder according to the temperature change, the delay characteristic of the row decoder is changed to a CR-type delay characteristic having a small temperature dependency.
This makes it possible to realize a semiconductor memory device in which the timing margin for activating the sense amplifier is reduced.

In the semiconductor integrated circuit according to the tenth aspect of the present invention, by controlling the potential of the output line as a stabilized output voltage based on the difference in delay time between the first and second delay circuits, The delay time of a plurality of circuit blocks using the stabilized output voltage as a power source is kept constant. Thus, a highly reliable semiconductor integrated circuit can be realized. Moreover, the output of the constant voltage generation circuit can be controlled only by the two signals output from the delay time difference detection circuit, that is, the promotion signal and the suppression signal.

According to the eleventh aspect of the present invention, since the constant voltage generating circuits are dispersedly arranged on the semiconductor substrate so as to be close to each of the plurality of circuit blocks, the output current of each constant voltage generating circuit is reduced. be able to. In addition, the outputs of the plurality of constant voltage generation circuits can be centrally controlled with only two signal lines for transmitting the promotion signal and the suppression signal output from one delay time difference detection circuit.

According to the twelfth aspect of the present invention, the first and the second
Since the delay circuit of was placed almost in the center on the semiconductor substrate,
The output of each constant voltage generation circuit can be controlled based on the average temperature on the semiconductor substrate. In addition, a signal line for transmitting the promotion signal and the suppression signal can be shortened.

According to the thirteenth aspect, the first and the second
Is arranged near the heat generation center on the semiconductor substrate, the temperature change can be immediately reflected in the output of each constant voltage generation circuit.

[0044]

[0045]

[0046]

In the power supply circuit according to the fourteenth aspect , by controlling the potential of the output line as the stabilized output voltage based on the difference between the delay times of the first and second delay circuits, The delay time of the logic circuit using the output voltage as the power supply is kept constant. According to the invention of claim 15 ,
The first delay circuit having small temperature dependence is realized as a CR delay circuit.

According to the sixteenth aspect of the present invention, the output potential of the constant voltage generation circuit, that is, the output of the power supply circuit, is formed by only two signal lines for transmitting the promotion signal and the suppression signal output from the delay time difference detection circuit. The line potential can be controlled.

[0049]

Embodiment 1 (Reference Potential Generation Circuit) First, a reference potential generation circuit according to a first embodiment of the present invention will be described.
This will be described with reference to FIGS.

(1) Embodiment 1.1 (Resistive Load / Ground Potential Reference Type) The configuration of FIG. 1 is for generating a constant potential difference between the ground line 3 as a reference potential line and the output node 2. The circuit includes a resistance means R, a feedback means F, and a diode means D. Resistance element 4 constituting resistance means R
Is constituted by a polysilicon resistor or a diffusion resistor, and is inserted between a power supply line 1 (VCC: external power supply voltage level) and an output node 2. The N-type MOSFET 5 constituting the feedback means F has a gate connected to the output node 2 and a source connected to the ground line 3 (VSS: ground potential). Further, three other N-type MOSFETs 6 connected in series with each other so as to constitute the diode means D.
Reference numerals 7 and 8 are inserted between the drain of the N-type MOSFET 5 of the feedback means F and the output node 2.

(2) Embodiment 1.2 (Resistive Load / External Power Supply Voltage Level Reference Type) The configuration of FIG. 2 generates a constant potential difference between the power supply line 31 as a reference potential line and the output node 32. And a resistance means R and a feedback means F as in the case of FIG.
And diode means D. Resistance means R
Is constituted by a polysilicon resistor or a diffusion resistor, and is inserted between the ground line 33 (VSS: ground potential) and the output node 32. The P-type MOSFET 35 constituting the feedback means F has a gate connected to the output node 32 and a source connected to the power supply line 31 (V
CC: external power supply voltage level). The other three P-type MOSFETs 36, 37, 38 connected in series with each other to constitute the diode means D are inserted between the drain of the P-type MOSFET 35 of the feedback means F and the output node 32.

(3) Embodiments 1.3 and 1.4 (Transistor Load Type) The configuration shown in FIG. 3 is used as the resistance means R in FIG. Is used. Further, in the configuration of FIG. 4, the resistance means R in FIG.
This uses the channel resistance of the MOSFET 39.

(4) Embodiment 1.5 (variable output type) The configuration of FIG. 5 is such that the potential of the output node 2 can be changed according to the control signal C in the circuit of FIG. That is, one of the three N-type MOSFETs 6, 7, 8 constituting the diode means D is an N-type MOSFET.
Short-circuit means S for short-circuiting the source and drain of T7 is provided, and the resistance means R has a variable resistance value. The short-circuit means S is composed of another N-type MOSFET 10, and its gate is supplied with a control signal for ON / OFF through a first control input terminal 11. On the other hand, the resistance means R is composed of four resistance elements 12,
13, 14, and 15, of which three resistance elements 1
Three P-type M for short-circuiting 3, 14, 15 individually
OSFETs 16, 17, and 18 are further provided.
The gates of these three P-type MOSFETs 16, 17, 18 are respectively connected to the second to fourth control input terminals 19, 2
Control signals for ON / OFF are provided through 0 and 21.

(5) Embodiment 1.6 (variable output type) The configuration of FIG. 6 allows the potential of the output node 2 to be changed according to the control signal C in the transistor load type circuit shown in FIG. It was done. That is, another N-type MOSFET 1 for short-circuiting a part of the three N-type MOSFETs 6, 7, 8 constituting the diode means D.
0 and a second and third P-type MOSFET 9 inserted between the power supply line 1 and the output node 2 so as to form the resistance means R.
The MOSFETs 22 and 23 are connected in parallel.
The gate of the N-type MOSFET 10 constituting the short-circuit means S;
And the second and third P-type MOSFs of the resistance means R
Control signals for ON / OFF are supplied to the gates of the ETs 22 and 23 through first to third control input terminals 11, 24 and 25, respectively.

The operation of each reference potential generating circuit configured as described above will be described.

First, the principle of operation will be described using the basic type shown in FIG. According to the configuration shown in the figure, a small current always flows from the power supply line 1 to the ground line 3 as a reference potential line via the resistance means R, the diode means D and the feedback means F. Here, the N-type MO constituting the feedback means F
Assuming that the drain of SFET 5 is internal node A, the potential difference between internal node A and output node 2 is the sum of the threshold voltages Vt of three N-type MOSFETs 6, 7, 8 constituting diode means D, that is, 3Vt.
Is almost equal to If the ambient temperature increases and Vt increases, the potential difference between internal node A and output node 2 increases. However, along with this, the potential difference between the source and the gate of the N-type MOSFET 5 constituting the feedback means F increases, and as a result, the feedback N-type MOSFET
5, the channel resistance decreases. As a result, the potential of the internal node A decreases, and as a result, the output node 2 is kept almost at the potential before the threshold voltage Vt changes. That is, the temperature dependency of the potential of the output node 2 is reduced. The above is a brief description of the operation principle.

In the configuration of FIG. 2, unlike the case of FIG. 1, the power supply line 31 is used as the reference potential line, but the operation principle is the same as that described above. It will be kept constant regardless of the variation of Vt. 3 and 4 use the channel resistances of the MOSFETs 9 and 39 as the resistance means R. By using the channel resistance of the MOSFET as described above, the layout area of the circuit can be reduced as compared with the case of using a resistance element having a small sheet resistance constituted by the polysilicon resistance or the diffusion resistance.
5 and 6 allow the resistance value of the resistance means R and the series number of MOSFETs constituting the diode means D to be changed in accordance with the control signal C, so that the potential of the output node 2 can be changed. It was done. In particular, according to the configuration of FIG. 6, the reference potential generation circuit can be configured only with MOSFETs. However, the N-type MOSFET 10 constituting the short-circuit means S in FIG. 6 is for coarse adjustment of the output, and the second and third P-type MOSFETs 22 and 2 in the resistance means R are provided.
Reference numeral 3 is for fine adjustment of the output.

In each of the configurations shown in FIGS.
When the sum of the conductances of the respective MOSFETs constituting the diode means D is equal to the conductance of the MOSFETs constituting the feedback means F, the effect of reducing the temperature dependency is maximized. That is, when the channel width of each of a plurality of MOSFETs constituting the diode means D is W1, the channel length is L1, the number of series is N, and the channel width of the MOSFET constituting the feedback means F is W2 and the channel length is L2. , W1 / L1 and W2 / L2 are approximately N: 1.

FIG. 7 shows a simulation result of the reference potential generating circuit according to the present embodiment. It is shown that the present embodiment reduces the temperature dependency of the output potential.

Embodiment 2 (Constant Voltage Generating Circuit) Next, a constant voltage generating circuit according to a second embodiment of the present invention will be described with reference to FIGS.

(1) Embodiment 2.1 (Basic Type) The configuration of FIG. 8 is a circuit for holding the potential of the output line 44 at a predetermined value, and the reference potential generating circuit 41 shown in FIG.
In addition, a comparator circuit 42 and a P-type MOSFET 43 as a driver circuit for driving the output line 44 are added. The comparator circuit 42 compares the potential of the output node 41a of the reference potential generation circuit 41 with the potential of the output line 44.
Is supplied to the gate of the P-type MOSFET 43.

According to this configuration, when the potential of the output line 44 is about to decrease due to, for example, an increase in the load current, the difference between the reference potential from the output node 41a of the reference potential generating circuit 41 and the potential of the output line 44 is determined by the comparator. The gate voltage is controlled by the circuit 42 so that the drain current of the P-type MOSFET 43 is increased, thereby preventing the output voltage from lowering. As a result, a stabilized output voltage is obtained on the output line 44. Moreover, the circuit shown in FIG. 8 can change the setting of the stabilized output voltage according to the control signal C by the action of the resistance means R and the short-circuit means S.

However, the constant voltage generation circuit of FIG. 8 has the following problems. That is, when the voltage to be generated is close to the external power supply voltage level VCC, the output potential of the reference potential generating circuit 41 should be set to such a voltage level.
Will not work properly.

Comparator circuit 4 using MOSFET
FIG. 9 shows a typical circuit configuration of the second example. In FIG.
Reference numerals 7a and 47b denote differential N-type MOSFETs whose gates are supplied with input potentials V + and V-, 48a and 48b are current mirror P-type MOSFETs, and 49 is a common N-type MOSFET whose gate is supplied with a standby signal Vsb. FIG. 10 shows the input / output characteristics of the comparator circuit 42.
As shown in the figure, when the input voltage approaches the power supply level, the output Vout of the comparator circuit 42 changes to the ground potential VSS.
It does not fall down to the end. In other words, the comparator circuit 42 has an input voltage of a current mirror P-type MOSFET.
When the threshold voltages of 48a and 48b are divided, normal comparison operation is not performed.

A description will now be given of a constant voltage generating circuit to which a voltage shift circuit is added so as to shift the operating point of the comparator circuit 42 to an optimum position.

(2) Embodiment 2.2 (Addition of Voltage Shift Circuit) The configuration of FIG. 11 is obtained by adding a capacitor element 45 and a voltage shift circuit 46 to the circuit of FIG. The capacitor element 45 is inserted between the output line 44 and the feedback input terminal of the comparator circuit 42 to prevent oscillation. The voltage shift circuit 46 includes a plurality of P-type MOSFs constituting the diode means D in the reference potential generation circuit of FIG.
Short-circuit means S for short-circuiting a part of the ET is provided, and resistance means R has a variable resistance value. However, in the reference potential generation circuit of FIG. 4, the power supply line 31 is used as the reference potential line, but in the voltage shift circuit 46 of FIG. 11, the output line 44 is used as the reference potential line via the input node 46a. That is, the voltage shift circuit 46 is a circuit for generating a constant potential difference between the output line 44 and its own output node 46b. The potential of the output node (first node) 41a of the reference potential generating circuit 41 is given as a reference input to the comparator circuit 42, while the potential of the output node (second node) 46b of the voltage shift circuit 46 is Is provided as a feedback input.

The operation principle of the constant voltage generating circuit shown in FIG. 11 will be briefly described. By inserting the voltage shift circuit 46 between the output line 44 and the feedback input of the comparator circuit 42, the potential of the feedback input of the comparator circuit 42 is reduced to a point lower than the potential of the output line 44 by a certain voltage. Is set. In addition, this shift amount does not change even when the temperature changes, as is clear from the above description of the operation of the reference potential generation circuit. On the other hand, the reference input from the reference potential generation circuit 41 to the comparator circuit 42 is similarly set lower than the intended stabilized output voltage. As a result, the operating point of the comparator circuit 42 can be shifted to a range in which it can operate normally. Moreover, the circuit shown in FIG. 11 can change the setting of the stabilized output voltage according to the control signal C by the action of the resistance means R and the short-circuit means S of each of the reference potential generation circuit 41 and the voltage shift circuit 46. It has become.

The capacitor element 45 delays a change in the stabilized output from appearing as a change in the feedback input due to the insertion of the voltage shift circuit 46. As a result, a loop circuit including the comparator circuit 42 and the P-type MOSFET 43 is formed. This is to prevent oscillation. That is, only the fluctuation component is configured to pass through the capacitor element 45.

(3) Embodiment 2.3 (Programmable Constant Voltage Generating Circuit) FIG. 12 shows a programmable constant voltage generating circuit obtained by developing the constant voltage generating circuit of FIG. In FIG.
Reference numeral 52 denotes a reference potential generating circuit according to the first embodiment of the present invention;
Is a comparator circuit, 53 is a P-type MOSFET as a driver circuit, 54 is an output line for a stabilized voltage, 55 is a capacitor element, and 56 is a voltage shift circuit. The resistance means R of the reference potential generation circuit 51 and the resistance means R of the voltage shift circuit 56 are each configured so that the resistance value changes according to the control signal C. Further, the reference potential generating circuit 51 and the voltage shift circuit 56 include a plurality of MOS transistors constituting the diode means D.
Short-circuit means S for short-circuiting between the source and the drain of at least one of the MOS transistors in accordance with the control signal C are provided. 57 is
This is a control circuit for changing the potential of the output line 54 by supplying a control signal C to the reference potential generation circuit 51 and the voltage shift circuit 56.

The control circuit 57 raises the potential of the output line 54 as a stabilized output voltage each time the promotion signal is received, and lowers the potential of the output line 54 each time the suppression signal is received. It has a function of generating C.
That is, the rise and fall of the output voltage can be controlled only by the two signal lines.

When the control circuit 57 receives a standby signal through the standby recognition terminal,
The control signal C is generated so as to reduce the current consumption of each of the reference potential generation circuit 51, the comparator circuit 52, and the voltage shift circuit 56. In order to set the resistance value of each resistance means R of the reference potential generation circuit 51 and the voltage shift circuit 56 to the maximum, and to reduce the through current in the comparator circuit 52, a common N-type MOSFET (FIG.
(Equivalent to 49 in FIG. 3) is turned off. However, a control signal to the comparator circuit 52 is not shown.

Further, the control circuit 57 has a function of generating a control signal C so as to initialize the potential of the output line 54 to a default value when a power-on reset signal is received through the reset recognition terminal. .

The constant voltage generating circuit having the configuration shown in FIG.
2, it can be developed into a programmable constant voltage generating circuit.

Embodiment 3 (Voltage Level Detecting Circuit) Next, a voltage level detecting circuit according to a third embodiment of the present invention will be described with reference to FIGS.

In a DRAM integrated circuit, as described above,
A substrate bias level VBB and a word line boost level VPP are required in addition to the power supply voltage level VCC externally supplied with reference to the ground potential VSS.

(1) Embodiment 3.1 (VBB Level Detection Circuit) FIG. 13 shows a configuration example of a VBB level detection circuit in which the ground potential VSS is used as a reference voltage level, and the substrate bias level VBB is used as a measured voltage level. Things. In the figure, 61
Is a first reference potential generating circuit for generating a constant potential difference between a ground line (VSS: ground potential) and the first node 61a, and includes the same resistance means R, It is provided with feedback means F, diode means D and short-circuit means S. Reference numeral 62 denotes a second reference potential generating circuit for generating a constant potential difference between the measured line at the substrate bias level VBB and the second node 62a.
And a resistance means R, a feedback means F, a diode means D and a short-circuit means S similar to those of the first embodiment. However, the number of N-type MOSFETs constituting the diode means D in series is larger in the second reference potential generation circuit 62,
Mainly, the difference between the numbers determines the depth of the substrate bias to be detected. 63 is a comparator circuit for comparing the potential of the first node 61a with the potential of the second node 62a. The output of the comparator circuit 63 is taken out from the output terminal 64 as a substrate level detection output φ1. This VBB level detection circuit has a feature that the voltage level detection characteristic does not depend on the temperature.

(2) Embodiment 3.2 (VPP level detection circuit) FIG. 14 shows a configuration of a VPP level detection circuit in which the external power supply voltage level VCC is used as a reference voltage level, and the word line boosted level VPP is used as a measured voltage level. This is an example. In the drawing, reference numeral 65 denotes a first reference potential generating circuit for generating a constant potential difference between a power supply line (VCC: external power supply voltage level) and a first node 65a, and 66 denotes a word line boosted level VPP. A second reference potential generating circuit for generating a constant potential difference between the measured line and the second node 66a;
67 is the potential of the first node 65a and the second node 66a
, A comparator circuit 68 for comparing the potential with the potential of .phi.2, and .phi.2 a boosted level detection output. The first and second reference potential generating circuits 65 and 66 are mainly composed of a P-type MO.
13 is a modification of the configuration of FIG. 4 using SFETs.
Is different from the VBB level detection circuit shown in FIG. Also in this VPP level detection circuit, the voltage level detection characteristics do not depend on temperature.

(3) Embodiments 3.3 and 3.4 (Hysteresis Characteristics Type) FIG. 15 shows a VBB level detection circuit having a configuration similar to that shown in FIG. 13 with hysteresis characteristics, and FIG. FIG. 16 shows a VPP level detection circuit having a hysteresis characteristic. First reference potential generation circuits 61 and 65 and second reference potential generation circuit 6
2 and 66 are configured such that the potential of their own output nodes can be changed according to the control signal C by the action of the resistance means and the short-circuit means, respectively.
Hysteresis control circuits 69 and 70 for generating a control signal C so as to change the voltage level detection characteristics in accordance with the level detection outputs φ1 and φ2 from 3, 67 are added.

FIG. 17 is a graph showing characteristics of the VBB level detection circuit of FIG. As shown in FIG. 17, the function of the hysteresis control circuit 69 makes it possible to make the level at which the substrate level detection output φ1 becomes 1 different from the level at which the substrate level detection output φ1 returns to 0. Thus, the operation of the VBB level detection circuit can be stabilized even when noise or the like is applied to the substrate bias level VBB which is the detection level. The VPP level detection circuit in FIG. 16 also has a similar hysteresis characteristic.

Embodiment 4 (Temperature Detection Circuit) Next, a temperature detection circuit according to a fourth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

(1) Embodiment 4.1 (ground potential reference type) The configuration of FIG. 18 is a circuit for determining whether or not the ambient temperature has reached a predetermined temperature. The circuit includes reference potential generating circuits 71 and 72 and a comparator circuit 73. Among them, the first reference potential generating circuit 71 reduces the potential difference having a small temperature dependency by alleviating the influence of the variation of the threshold voltage of the MOS transistor and the ground line (VSS: ground potential) and the first node 71a. And a resistor means R, feedback means F, diode means D, and short-circuit means S similar to those shown in FIG. The second reference potential generation circuit 72 generates a potential difference having a large temperature dependency between the ground line (VSS: ground potential) and the second node 72a due to the fluctuation of the threshold voltage of the MOS transistor. In which the arrangement of the feedback means F in the first reference potential generating circuit 71 is omitted. That is, in the second reference potential generation circuit 72,
One end of a series circuit comprising a plurality of N-type MOSFETs constituting the diode means D is directly connected to a ground line. The comparator circuit 73 calculates the potential of the first node 71a and the second node 71a.
Is a circuit for comparing the potential of the node 72a with the potential of the node 72a.

The output of the first reference potential generating circuit 71, that is, the potential of the first node 71a does not change even if the ambient temperature changes, as described above. On the other hand, since the second reference potential generating circuit 72 does not have the feedback means F for suppressing the temperature dependency, the potential of the second node 72a changes with the ambient temperature. That is, as the temperature changes, the potential difference between the first and second nodes 71a and 72a increases. This is supplied to the comparator 73
And the output is used as temperature detection.

(2) Embodiment 4.2 (External Power Supply Voltage Level Reference Type) FIG. 19 shows another configuration example of the temperature detection circuit. In the figure, reference numeral 75 denotes a first reference potential generating circuit for generating a potential difference having a small temperature dependency between a power supply line (VCC: external power supply voltage level) and a first node 75a; The potential difference having dependency is connected to the power supply line (VCC: external power supply voltage level) and the second node 76a.
A second reference potential generating circuit for generating a voltage between
7 is a comparator circuit for comparing the potential of the first node 75a with the potential of the second node 76a, and 78 is an output terminal. As in the case of FIG. 18, the feedback means F is provided only in the first reference potential generation circuit 75 of the first and second reference potential generation circuits 75 and 76. The first and second reference potential generating circuits 75 and 76 are mainly composed of P-type MOSFs.
Although the configuration of FIG. 4 using ET is different from that of FIG. 18, the operation principle is the same.

(3) Embodiments 4.3 and 4.4 (Hysteresis Characteristics) FIGS. 20 and 21 show the temperature detection circuits shown in FIGS. 18 and 19 having hysteresis characteristics, respectively. The first reference potential generation circuits 71 and 75 and the second reference potential generation circuits 72 and 76 can change the potential of their own output nodes according to the control signal C by the action of the resistance means and the short-circuit means, respectively. It has hysteresis control circuits 79 and 80 for generating a control signal C so as to change the temperature detection characteristics according to the temperature detection outputs from the comparator circuits 73 and 77.

FIG. 22 is a graph showing characteristics of the temperature detection circuit of FIG. As shown in FIG. 22, the temperature t1 at which the temperature detection output becomes 1 and the temperature t0 at which the temperature detection output returns to 0 can be made different by the operation of the hysteresis control circuit 79. As a result, the temperature detection circuit does not malfunction even if the temperature fluctuates instantaneously. The temperature detection circuit of FIG. 21 also has a similar hysteresis characteristic.

Fifth Embodiment (Power Supply Circuit of Active Voltage Control System) Next, a power supply circuit of an active voltage control system according to a fifth embodiment of the present invention will be described with reference to FIGS. .

In the conventional power supply circuit system, it has been aimed that the output voltage does not change even if the ambient temperature changes. However, the operation of a logic circuit on a semiconductor integrated circuit generally becomes slow as the temperature rises. The active voltage control method according to the present embodiment, when the temperature rises,
The purpose is to increase the power supply voltage so as not to slow down the operation of the logic circuit.

(1) Embodiments 5.1 and 5.2 (Temperature Control Type) In the power supply circuit of FIG. 23, the potential of the output line 44 can be changed according to the control signal C by the action of the resistance means and the short-circuit means. The constant voltage generation circuit 81a of FIG. 8 configured as described above is employed, and a control circuit 81b for generating the control signal C is added to the constant voltage generation circuit 81a to form a programmable constant voltage generation circuit 82. In this configuration, the circuit 81b operates according to the output of the temperature detection circuit 83. The power supply circuit of FIG. 24 employs the constant voltage generation circuit 84a of FIG. 11 similarly configured to change the potential of the output line 44 according to the control signal C, and generates the control signal C. Is added to the constant voltage generating circuit 84a to form a programmable constant voltage generating circuit 85, and the control circuit 84b operates according to the output of the temperature detecting circuit 86. 18 to 21 can be adopted as the temperature detection circuits 83 and 86.

The power supply circuits of FIGS. 23 and 24 both control the control circuits 81b and 84b in accordance with the temperatures detected by the temperature detection circuits 83 and 86 so as to increase the potential of the output line 44 in response to the temperature increase. To constant voltage generation circuit 81
a, 84a to generate a control signal C. However, it is intended to match the qualitative tendency, and there is no clear guideline on how much the power supply voltage should be raised when the temperature rises. An improvement in this point is a delay time control type active voltage control method described below.

(2) Embodiment 5.3 (Delay Time Control Type) The power supply circuit of FIG. 25 includes a temperature detection circuit 83 for controlling the programmable constant voltage generation circuit 82 in FIG. It is replaced with an active voltage control circuit 95 including a first delay circuit 92, a second delay circuit 93, and a delay time difference detection circuit 94.

The pulse generating circuit 91 generates a pulse signal by dividing the frequency of a system clock (such as RAS in a DRAM), an internal refresh signal and the like, and converts the pulse signal into a first signal.
And second delay circuits 92 and 93, respectively. The first delay circuit 92 is a delay circuit in which the temperature dependence of the delay time of the pulse signal is small, and uses a time constant determined by, for example, a resistance element and a capacitor element for the delay. An example of the first delay circuit 92 having small temperature dependency is the above-mentioned conventional CR delay circuit. The second delay circuit 93 has a logic gate as a temperature monitor set so that the delay time of the pulse signal at the reference temperature (room temperature) matches the first delay circuit 92. Here, the logic gate indicates a general logic circuit such as a NAND gate used in a peripheral circuit of the DRAM. The delay time difference detection circuit 94
For detecting the difference between the delay time of the delay circuit 92 and the delay time of the second delay circuit 93, wherein the delay time of the second delay circuit 93 is longer than the delay time of the first delay circuit 92. It has a function of outputting a promotion signal when it becomes larger, and outputting a suppression signal when the delay time of the second delay circuit 93 becomes smaller than the delay time of the first delay circuit 92.

The programmable constant voltage generating circuit 82 changes the potential of the output node 41a according to the control signal C by the action of the resistance means and the short-circuit means, thereby changing the potential of the output line 44 as a stabilized output voltage. And a reference potential generating circuit 41 configured to increase the potential of the output line 44 each time a promotion signal from the delay time difference detection circuit 94 is received, and to increase the potential of the output line 44 each time a suppression signal is received.
Has the function of lowering the potential of the Note that at least the second delay circuit 93 is supplied as a power supply with a stabilized voltage on the output line 44 output from the programmable constant voltage generation circuit 82, for example, as the internal step-down level Vint.

Next, the operation of the power supply circuit having the above configuration and shown in FIG. 25 will be described. When the temperature rises, the delay time in the second delay circuit 93 increases. On the other hand, the delay time of the first delay circuit 92 having small temperature dependency does not increase so much. Therefore, a difference occurs between the delay times of the two delay circuits 92 and 93. This is detected by the delay time difference detection circuit 94, and a promotion signal is sent to the programmable constant voltage generation circuit 82 so as to increase the potential of the output line 44. This promotion signal is sent each time a pulse signal is generated in the pulse generation circuit 91. As a result, the output line 44
Rises, and the increase in the delay time of the second delay circuit 93 using the same as the power supply is canceled.

On the other hand, if the delay time in the second delay circuit 93 becomes too small as a result of the delay time in the first delay circuit 92 having a small temperature dependency, the programmable constant voltage generation circuit 82 A suppression signal is sent to lower the stabilized output voltage Vint on output line 44. By these series of operations, the second delay circuit 9
The stabilized output voltage Vint on the output line 44 is adjusted so that the delay time of the third delay circuit 3 is substantially equal to the delay time of the first delay circuit 92. As a result, a large number of logic circuits (not shown) powered by the voltage Vint are used. Are kept constant. By using such an active voltage control type power supply circuit, a highly reliable semiconductor integrated circuit can be realized as described later.

A temperature detecting circuit 86 for controlling the programmable constant voltage generating circuit 85 in FIG.
5, a pulse generation circuit, first and second delay circuits, and a delay time difference detection circuit may be used.

Embodiment 6 (Semiconductor Integrated Circuit) Next, a semiconductor integrated circuit according to a sixth embodiment of the present invention will be described with reference to FIGS.

(1) Embodiment 6.1 (Semiconductor integrated circuit provided with delay time correction circuit: AND type delay time difference detection circuit) The configuration of FIG. 26 applies the power supply circuit technology of FIG. 25 to a semiconductor integrated circuit. It was done. The circuit blocks indicated by 101 to 106 in FIG. 26 correspond to the pulse generation circuit 9 in FIG.
1. These correspond to a first delay circuit 92 having a small temperature dependency, a second delay circuit 93 composed of a logic gate, a delay time difference detection circuit 94, a control circuit 81b, and a constant voltage generation circuit 81a. In the semiconductor integrated circuit of FIG. 26, the output voltage Vint of the constant voltage generation circuit 106 is supplied to the second delay circuit 103 and the peripheral circuit 107 as power supply voltages. The peripheral circuit 107 includes a delay circuit, and the delay circuit is formed of a normal inverter chain including a plurality of stages of inverters each including only two P-type and N-type MOSFETs. The output voltage Vint of the constant voltage generation circuit 106 is supplied to each inverter as a power supply voltage.

According to this configuration, the first delay circuit 102
And the delay time τ2 of the second delay circuit 103
By changing the output voltage Vint of the constant voltage generation circuit 106 until the difference from the above is not recognized, the delay time of the inverter chain in the peripheral circuit 107 using the voltage as a power supply is corrected. That is, despite the fact that a delay circuit composed of a normal inverter chain is used for the peripheral circuit 107, a small temperature-dependent delay characteristic can be realized in the delay circuit. Thus, the layout area of the peripheral circuit 107 is reduced. In addition,
When the temperature characteristic of the pulse generation circuit 101 becomes a problem, an external pulse signal having low temperature dependency may be directly input to the first and second delay circuits 102 and 103.

Next, the delay time difference detecting circuit 10 shown in FIG.
4. Detailed configurations of the control circuit 105 and the constant voltage generation circuit 106 will be sequentially described.

FIG. 27 shows the configuration of the delay time difference detection circuit 104. The delay time difference detection circuit 104, which uses the output signal S1 of the first delay circuit 102 and the output signal S2 of the second delay circuit 103 as input signals, comprises a first delay circuit section 111a,
111b and first NAND circuits 112a and 112b
, Second NAND circuits 113a and 113b, third NAND circuit 114, and second delay circuit sections 115a and 115a.
15b and fourth NAND circuits 116a and 116b. First delay circuit section 111a, 1
Numeral 11b designates an odd number of stages of inverters for delaying the input signals S1 and S2. First NAND circuits 112a, 112b
Are the input signals S1 and S2 and the first delay circuit 111
a and 111b are input. Second
NAND circuits 113a and 113b receive the input signals S1,
S2 and a signal obtained by inverting the output signals S3 and S4 of the first NAND circuits 112a and 112b, respectively, are input. The third NAND circuit 114 is a second NAND circuit.
Signals obtained by inverting the output signals S5 and S6 of the circuits 113a and 113b are input. The second delay circuit units 115a and 115b are connected to the third NAND circuit 114, respectively.
Are configured by the same number of even-numbered stages of inverters for delaying the input signal. 4th NA
The ND circuits 116a and 116b are connected to the second delay circuit 11
5a and 115b and the output signal S7 of the third NAND circuit 114 are input. 4th
, NAND circuits 116a and 116b output first and second detection signals S8 and S9, respectively, as the promotion signal and the suppression signal.

FIGS. 28A to 28I show operation waveform diagrams of the delay time difference detection circuit 104 when τ1 <τ2. First delay circuit units 111a and 111b and first NAND
The input signals S1 and S2 are output by the circuits 112a and 112b.
Generates S3 and S4 having the same pulse width from each other. S3 and S4 correspond to the second NAND circuit 113
The signals a and 113b are changed to signals S5 and S6 having the same falling timing. Third NAND circuit 1
The selector 14 selects the signal having the smaller pulse width of S5 and S6 as S7. The fourth NAND circuit 116a,
116b is a first and second detection signal S8 based on S7.
, S9 are output. At this time, the pulse width of the second detection signal S9 is changed to the pulse width of the first detection signal S8, reflecting that the delay time τ2 of the second delay circuit 103 is longer than the delay time τ1 of the first delay circuit 102. The pulse width difference Δx is proportional to the delay time difference δ between the input signals S1 and S2. However, the first and second detection signals S
8 and S9 have the same rising timing.

Conversely, when τ1> τ2, although not shown, the first and second detection signals S rising at the same time are not shown.
8 and S9 are output from the delay time difference detection circuit 104, and the pulse width of the second detection signal S9 is changed to the first detection signal S9.
8 is made smaller than the pulse width. As will be described later, when the pulse width of the first detection signal S8 is larger, the output voltage Vint of the constant voltage generation circuit 106 is increased when the pulse width of the second detection signal S9 is larger. Is the V
It works to reduce int.

FIG. 29 shows the structure of the control circuit 105. The control circuit 105 that receives the LOAD signal and the RESET signal in addition to the first and second detection signals S8 and S9 from the delay time difference detection circuit 104 is configured as an M-stage bidirectional shift register. Each stage of the shift register includes first and second latch circuits 121 and 122, and first to fourth switching elements each including an N-type MOSFET. First switching element 12
3 is interposed between the output side of the first latch circuit 121 and the input side of the second latch circuit 122, and LOAD is connected to the gate.
A signal is applied. The second switching element 124 is
The first latch circuit 121 is interposed between the input side of the first latch circuit 121 and the output side of the second lower latch circuit 122 in the adjacent lower stage.
Is applied. The third switching element 125 is interposed between the input side of the first latch circuit 121 and the output side of the adjacent upper-stage second latch circuit 122, and has a gate to which the second detection signal S9 is applied. The fourth switching element 126 has the first latch circuit 1 in the upper half.
21 and the power supply line (VCC: external power supply voltage level), and in the lower half, between the input side of the first latch circuit 121 and the ground line (VSS: ground potential). , A RESET signal is applied to the gate.

According to this configuration, first, the fourth switching elements 124 in all stages are opened by the RESET signal, and the first switching elements 123 in all stages are opened by the pulse of the LOAD signal. Thereby, the initial settings of the first and second latch circuits 121 and 122 of all the stages are performed, and the high logic signal is output from the second latch circuit 122 of the upper half and the latch circuit 122 of the lower half. Output a low logic signal. The M logic signals held in the second latch circuit 122 become initial signals of the control signal C to the constant voltage generation circuit 106.

After the RESET signal is released, the first and second detection signals S8 and S9 having the same rising timing are supplied from the delay time difference detection circuit 104. At this time, for example, as shown in FIGS. 28 (h) and (i), the pulse width of the second detection signal S9 is changed to the first pulse, reflecting that τ1 <τ2.
When the pulse width of the first detection signal S8 is larger than the pulse width of the first detection signal S8, the first detection signal S8 transitions to the low state first, so that the lowermost second latch circuit 1
The output of 22 is changed to a low logic signal. That is, when τ1 <τ2, as the pulses of the LOAD signal are sequentially supplied, the number of Low signals among the M logic signals constituting the control signal C increases. Conversely, τ1
If> τ2, the number of High logic signals increases.

FIG. 30 shows the configuration of the constant voltage generation circuit 106. The constant voltage generation circuit 106 that receives the control signal C from the control circuit 105 as an input signal includes a reference potential generation circuit 131, a comparator circuit 132, and a driver circuit 133, as in the configuration of FIG. The potential of the line 134 (Vint: internal step-down level) can be changed according to the control signal C. Reference potential generation circuit 131
Is a circuit for generating a constant potential difference between a ground line as a reference potential line and the output node 131a,
It comprises resistance means R, feedback means F and diode means D. The M resistance elements connected in series to constitute the resistance means R are inserted between a power supply line (VCC: external power supply voltage level) and the output node 131a. In addition, P-type MOSFETs are connected in parallel to each of the resistance elements so that both terminals of the resistance elements can be short-circuited. Are respectively applied. The N-type MOSFET constituting the feedback means F has a gate connected to the output node 131a and a source connected to a ground line (VSS: ground potential). In addition, another 3 connected in series with each other to constitute the diode means D.
The two N-type MOSFETs are N-type MOSFETs of the feedback means F.
It is inserted between the drain of T and the output node 131a. The comparator circuit 132 is composed of two P-type MOSFETs and two N-type MOSFETs as a current mirror type differential amplifier.
Then, the potential of the output node 131a and the potential of the output line 134 are compared. The driver circuit 133 for driving the output line 134 includes a P-type MOSFET in which the output of the comparator circuit 132 is applied to the gate and a normally-on N-type MOSFET.
And a type MOSFET.

According to this configuration, L of the control signal C from the control circuit 105 reflects that τ1 <τ2.
When the number of logic signals ow increases, the reference potential generation circuit 13
As a result, the output voltage Vint increases so as to reduce the delay time τ2 of the second delay circuit 103. Conversely, if τ1> τ2, H
As the number of high logic signals increases, the output voltage Vint decreases so as to increase the delay time τ2 of the second delay circuit 103. That is, the first and second delay circuits 1
Output voltage V so that the delay time difference between
int is changed.

(2) Embodiment 6.2 (Semiconductor Integrated Circuit with Delay Time Correction Circuit: OR Type Delay Time Difference Detection Circuit) The configuration shown in FIG. 31 is one signal output from the first delay circuit. And two signals output from the second delay circuit and having a phase difference therebetween to detect whether there is a delay time difference. In the figure, 141 is a pulse generation circuit, 142 is a first delay circuit, 143 is a second delay circuit, 144 is a delay time difference detection circuit, 145 is a control circuit, 146 is a constant voltage generation circuit, and 147 is a peripheral circuit. Thus, they correspond to the circuit blocks 101 to 107 in FIG. 26, respectively.

The second delay circuit 143 is constituted by a normal inverter chain including (n + 2) or more stages of inverters. The delay time .tau.2 of the second delay circuit 143 is defined by the output signal T4 of the n-th inverter as a reference signal, and the delay time .tau.2 at the reference temperature is the delay time .tau. Of the first delay circuit 142.
1 and the first and second delay circuits 142, 142
143, the temperature dependence of the delay characteristics is set. While only one output signal T1 is extracted from the first delay circuit 142, the output signal T2 (auxiliary output signal) of the (n-2) th inverter is output from the second delay circuit 143; Three signals, an output signal T3 (first output signal) of the (n-1) th inverter and an output signal T5 (second output signal) of the (n + 1) th inverter, are output.

The delay time difference detection circuit 144 has a three-input N
OR circuit 151, first inverter 152, first latch circuit 153, first switching element 154 composed of an N-type MOSFET, and NAND circuit 155
, A second inverter 156, a second switching element 157 formed of a P-type MOSFET, and a second latch circuit 158. The NOR circuit 151 receives the output signal T1 of the first delay circuit 142 and the first and second output signals T3 and T5 of the second delay circuit 143 as input signals. The first inverter 152 is connected to the NOR circuit 15
1 to the first latch circuit 15
3 input. First switching element 154
Is interposed between the output side of the first latch circuit 153 and the ground line, and the second output signal of the second delay circuit 143 is applied to the gate so as to initialize the first latch circuit 153. T5 is applied. The NAND circuit 155 receives the output signal of the first latch circuit 153 and the signal obtained by inverting the auxiliary output signal T2 of the second delay circuit 143 by the second inverter 156 as input signals, and outputs the first delay circuit 142 And outputs a first detection signal T6 indicating whether or not there is a difference between the delay time .tau.1 of the second delay circuit 143 and the delay time .tau.2 of the second delay circuit 143. The second switching element 157 is interposed between the output side of the first delay circuit 142 and the input side of the second latch circuit 158, and has its gate connected to the auxiliary output signal T2 from the second delay circuit 143. Is applied. Second latch circuit 1
58 is a second detection signal T indicating which one of the first and second delay circuits 142 and 143 has a longer delay time.
7 is output. The first and second detection signals T6 and T7 output from the delay time difference detection circuit 144 having the above configuration are supplied to the control circuit 145 as the promotion signal and the suppression signal.

FIGS. 32A to 32G show operation waveform diagrams of the delay time difference detection circuit 144 when τ1> τ2. FIG.
3 (a) to 3 (g) are similar diagrams when τ1 <τ2. First, the output of the first latch circuit 153 is initialized to Low when the second output signal T5 of the second delay circuit 143 becomes High and the first switching element 154 is turned on. Is done. As a result, the first
Is high. First delay circuit 14
When the output signal T1 of the second delay circuit and the first and second output signals T3 and T5 of the second delay circuit 143 have a low level at the same time, the delay time of the first delay circuit 142 is determined by the NOR circuit 151. As a result of the recognition that there is a difference between τ1 and the delay time τ2 of the second delay circuit 143, the output of the first latch circuit 153 transitions from low to high. Therefore, as shown in FIGS. 32 (f) and 33 (f), the first detection signal T6 transitions to Low.
The first detection signal T6, which has once transitioned to Low in this manner, remains in the first state until the first switching element 154 is turned on again by the transition of the second output signal T5 to High. Low by the latch circuit 153
Held in state. When the three input signals T1, T3, and T5 of the NOR circuit 151 do not go Low at the same time, the first detection signal T6 is held in the High state without ever making a transition to Low.

On the other hand, as shown in FIGS. 32A and 32B, the auxiliary output signal T2 of the second delay circuit 143 is high.
If the output signal T1 of the first delay circuit 142 is in the high state when the signal transits from the low state to the low state, the second latch circuit 158 determines that the delay time τ2 of the second delay circuit 143 is Is smaller than the delay time τ1 (τ
The second detection signal T7 is set to Low so as to notify the control circuit 145 of the determination that 1> τ2). Conversely, if the output signal T1 of the first delay circuit 142 is in a low state when the auxiliary output signal T2 changes from high to low as shown in FIGS. 33 (a) and (b), The second detection signal T7 is set high to indicate that .tau.1 <.tau.2.

When the control circuit 145 receives a Low pulse as the first detection signal T6, it outputs the second detection signal T6.
If 7 is in a low state indicating τ1> τ2, the control signal C is output to the constant voltage generation circuit 146 so as to lower the output voltage Vint. If a low pulse is received as the first detection signal T6 and the second detection signal T7 is in a High state indicating τ1 <τ2, a control signal C for increasing the output voltage Vint is output. . When the first detection signal T6 is held in the High state, the change of the output voltage Vint is stopped. By changing the output voltage Vint of the constant voltage generation circuit 146 until the difference between the delay time τ1 of the first delay circuit 142 and the delay time τ2 of the second delay circuit 143 is no longer recognized, , The delay time of the peripheral circuit 147 is corrected.

According to the configuration of FIG. 31, second delay circuit 1
43, the output signal T3 of the (n-1) th inverter
And the output signal T5 of the (n + 1) th inverter are used as reference signals for the output signal T1 of the first delay circuit 142, so that the presence or absence of a delay time difference is detected with a certain range of dead zone. As a result, the constant voltage generation circuit 1
The fluctuation of the output voltage Vint at 46 can be prevented. In addition,
The width of the dead zone can be arbitrarily changed depending on how to take two reference signals from the second delay circuit 143. The auxiliary output signal used for on / off control of the second switching element 157 is (n−2) as long as the logical level of the second detection signal T7 can be set at the pulse output timing of the first detection signal T6. ) Output signal T2 of the inverter at the stage
It is not limited to.

(3) Embodiment 6.3 (Semiconductor Integrated Circuit with Delay Time Correction Circuit: Flip-Flop Delay Time Difference Detection Circuit) The configuration shown in FIG. 34 has one signal output from the first delay circuit. And another signal output from the second delay circuit to detect the presence or absence of a delay time difference.
In the figure, 161 is a pulse generation circuit, and 162 is a first
26, 163 is a second delay circuit, 164 is a delay time difference detection circuit, 165 is a control circuit, 166 is a constant voltage generation circuit, and 167 is a peripheral circuit.
Each corresponds to a circuit block indicated by 107.

The delay time difference detection circuit 164 includes a flip-flop 168 and a monostable multivibrator 169. Flip-flop 168 has two NANs
D circuit, and the first and second delay circuits 16
2 and 163, and outputs a first detection signal U3 indicating which one of the first and second delay circuits 162 and 163 has a longer delay time, using the respective output signals U1 and U2 as input signals. is there. Monostable multivibrator 169
Is composed of two NOR circuits and three inverters. The output signals U1 and U2 of the first and second delay circuits 162 and 163 are used as input signals, and the delay time of the first delay circuit 142 is It outputs a second detection signal U4 indicating whether there is a difference between .tau.1 and the delay time .tau.2 of the second delay circuit 143. The first and second detection signals U output from the delay time difference detection circuit 164 having such a configuration.
3 and U4 are supplied to the control circuit 165 as the promotion signal and the suppression signal.

FIGS. 35A to 35D show operation waveform diagrams of the delay time difference detection circuit 164 when τ1> τ2. FIG.
6 (a) to 6 (d) are similar diagrams when τ1 <τ2. When the two input signals U1 and U2 are both Low, the first detection signal U is output by the flip-flop 168.
3 is in a High state. When U2 transitions to High earlier than U1 as shown in FIGS. 35A and 35B, the first detection signal U3 maintains the High state at this time. Conversely, when U1 transitions to High earlier than U2 as shown in FIGS. 36 (a) and (b), the first detection signal U3 is generated at this time by the amplifying function of the flip-flop 168. Transition to Low rapidly. On the other hand, the monostable multivibrator 169 determines a timing of activation of the control circuit 165 by a pulse signal having a fixed width from a rising point of a signal of the two input signals U1 and U2 which has transitioned to High earlier. As the second detection signal U4. That is,
According to the configuration of the delay time difference detection circuit 164 of FIG. 34, the flip-flop 168 and the monostable multivibrator 16
9, the first and second delay circuits 162, 1
63 small delay time differences can be detected.

If the first detection signal U3 is in the High state indicating τ1> τ2 when receiving the High pulse as the second detection signal U4, the control circuit 165 supplies the output voltage Vint to the constant voltage generation circuit 166. Control signal C is output so as to reduce If the first detection signal U3 is in a low state indicating τ1 <τ2 when a High pulse is received as the second detection signal U4, a control signal C for increasing the output voltage Vint is output. . Since there is no delay time difference, the second detection signal U4 becomes Lo.
If it is kept in the w state, the change of the output voltage Vint is stopped. Thus, the first delay circuit 162
And the delay time τ2 of the second delay circuit 163
By changing the output voltage Vint of the constant voltage generation circuit 166 until no difference is recognized, the delay time of the peripheral circuit 167 using the voltage as a power supply is corrected.

(4) Embodiment 6.4 (Semiconductor Integrated Circuit with Delay Time Correction Circuit: Example of Application to Ring Oscillator) The configuration of FIG. 37 uses the delay of the ring oscillator in the peripheral circuit as a temperature change. It shows an example corrected accordingly. In the figure, 171 is a pulse generation circuit, 172 is a first delay circuit, 173 is a second delay circuit, 174 is a delay time difference detection circuit, 175 is a control circuit, 176 is a constant voltage generation circuit, and 177 is a peripheral circuit. And 101 to 1 in FIG.
07 respectively. However,
The peripheral circuit 177 in the semiconductor integrated circuit of FIG. 37 includes four ring oscillators. Constant voltage generator 1
The output voltage Vint of 76 is supplied to the second delay circuit 173 and each ring oscillator as a power supply voltage.

Each ring oscillator is a 2-input NAN
D circuits 178a to 178d and delay circuit units 179a to 179d each formed of a normal inverter chain are provided. However, the delay circuit unit 179a of the first ring oscillator has eight stages, the delay circuit unit 179b of the second ring oscillator has six stages, the delay circuit unit 179c of the third ring oscillator has four stages, and the fourth stage. The delay circuit section 179d of the ring oscillator includes a two-stage inverter. That is, each of the delay circuit units 179a to 179d has a different delay time. Each delay circuit section 179a to 179
d is supplied with an input pulse signal via NAND circuits 178a to 178d. Further, each delay circuit section 179a
To 179d are output from NAND circuits 178a to 178d.
Is fed back to the delay circuit units 179a to 179d via the. The frequencies of the output pulse signals of the four ring oscillators configured as described above are f4 and f4, respectively.
/ 3f, 2f, and 4f.

According to this configuration, 4 in peripheral circuit 177
Since the output voltage Vint of the constant voltage generation circuit 176 supplied as a power supply voltage to each of the ring oscillators of the system is controlled in accordance with the temperature change, the delay circuits 179a to 179d constituting the main parts of each ring oscillator As a result, the temperature dependence of the output frequency of each ring oscillator is reduced despite the use of a normal inverter chain.

(5) Embodiment 6.5 (Semiconductor Integrated Circuit Equipped with Delay Time Correction Circuit: Application Example to DRAM) The configuration shown in FIG. 38 shows that the delay of each of the row decoder and the timing circuit in the DRAM changes with temperature. FIG. In the figure, 181 is a pulse generation circuit, 182 is a first delay circuit, 183 is a second delay circuit, 184 is a delay time difference detection circuit, 185 is a control circuit,
186 is a constant voltage generation circuit, 187 is a peripheral circuit,
26 correspond to circuit blocks indicated by 101 to 107 in FIG. However, the semiconductor integrated circuit in FIG. 38 includes memory cells at positions where word lines and bit lines cross each other, and the peripheral circuit 187 includes a row decoder 188, a timing circuit 189, and a sense amplifier 190.
The row decoder 188 has a logic gate for selecting a memory cell via a word line. The sense amplifier 190 is a circuit for amplifying a minute potential read from a memory cell selected by the row decoder 188 onto a bit line. The timing circuit 189 is a circuit for adjusting the timing at which an activation signal is output to the sense amplifier 190, and is configured by a normal inverter chain. The output voltage Vint of the constant voltage generation circuit 186 is supplied to the second delay circuit 183 and the row decoder 18.
8 are supplied as power supply voltages to the respective logic gates and the inverters of the timing circuit 189.

According to this configuration, the delay characteristics of row decoder 188 are adjusted to the delay characteristics of the word line. The delay characteristic of a word line has a small temperature dependency of a CR type determined by its distribution constant. On the other hand, the original delay characteristics of the row decoder have a large temperature dependence of the transistor type.
Therefore, conventionally, it is necessary to set the delay time of the timing circuit to a large value in consideration of the timing margin, and the access speed of the memory cell is limited. However, according to the configuration of FIG.
The constant voltage generation circuit 186 is configured to eliminate the difference between the delay time of the first delay circuit 182 formed of a delay circuit and the delay time of the second delay circuit 183 formed of a logic gate similarly to the row decoder 188. , And the output voltage Vint is supplied to the row decoder 188 as a power supply voltage, so that the delay characteristics of the row decoder 188 can be changed to the same CR type delay characteristics as those of the word lines, which have a small temperature dependency. . Therefore, the timing circuit 18
9 is set to a small value, the sense amplifier 19
There is no problem with the activation timing of 0, and high-speed access of the memory cell is enabled.

According to the configuration of FIG. 38, peripheral circuit 1
The constant voltage generation circuit 18
Since the output voltage Vint of No. 6 is supplied as the power supply voltage, the temperature dependence of the delay characteristics of the timing circuit 189 formed of a normal inverter chain is reduced. Therefore, the layout area of the peripheral circuit 187 can be reduced while obtaining the same effect as the case where the conventional CR delay circuit is used for the timing circuit.

The output voltage V of the constant voltage generation circuit 186
Even if int is supplied as the power supply voltage only to the second delay circuit 183 and the row decoder 188 in the peripheral circuit 187, the delay time of the timing circuit 189 can be reduced. In this manner, the supply of the output voltage Vint of the delay time correction circuit to the peripheral circuit 187 is performed by the row decoder 18.
If the number is limited to 8, the high speed access of the memory cell can be realized while suppressing an increase in current consumption of the entire semiconductor integrated circuit.

(6) Embodiment 6.6 (Multi-Power Supply Semiconductor Integrated Circuit) The configuration of FIG. 39 shows an example of a semiconductor chip such as a DRAM which requires a power supply of a plurality of voltage levels inside. In the figure, VPP generation circuits 211 and 212 are provided with a power supply voltage level VCC supplied from the outside and a ground potential VSS.
, A voltage of the word line boost level VPP is generated, and this voltage is supplied to specific circuit blocks 201 and 203 on the semiconductor substrate.
Circuit for supplying to VBB generation circuits 221 and 2
Reference numeral 22 denotes a circuit for generating a voltage of the substrate bias level VBB and supplying the voltage to the semiconductor substrate. However, these VPP generation circuits 211 and 212 and VBB generation circuit 2
21 and 222 do not require very large output currents. On the other hand, all circuit blocks 2 on the semiconductor substrate
Internal step-down level Vint to be commonly supplied to 01 to 204
Are generated and distributed on the semiconductor substrate so as to be close to each circuit block. This is to reduce the output currents of the individual Vint generating circuits 231 to 234. Each Vint generation circuit 231
234 have the configuration of the programmable constant voltage generating circuit (the configuration shown in FIG. 12 or the configuration shown by 82 or 85 in FIGS. 23 to 25).

The central control circuit 200 arranged substantially at the center on the semiconductor substrate has the following three functions.

The first function is a function as a VPP level detection circuit. The central control circuit 200 has the configuration of FIG. 14 or FIG. 16 for monitoring the word line boost level VPP, and outputs a boost level detection output φ2 when the word line boost level falls below a predetermined level. As a result, the VPP generation circuits 211 and 212 are operated, and when they are at a sufficient level, the operation is stopped.

The second function is a function as a VBB level detection circuit. The central control circuit 200 has the structure shown in FIG. 13 or FIG. 15 for monitoring the substrate bias level VBB.
Control the operation of.

The third function is a function of the active voltage control circuit 95 in FIG. That is, the central control circuit 2
00 is the pulse generation circuit 91, the first delay circuit 9
2. It has the configuration of a second delay circuit 93 and a delay time difference detection circuit 94. Then, a plurality of Vint generating circuits 23
Two signal lines for transmitting the promotion signal and the suppression signal are provided between the central control circuit 200 and the central control circuit 200, respectively. Thus, when the temperature rises,
A signal for setting an appropriate internal step-down level Vint corresponding thereto is transmitted by a small number of signal lines to Vint generating circuits 231 to 234 distributed on a semiconductor substrate. In addition, the Vint generating circuits 231 to 23 based on the average temperature on the semiconductor substrate by the central control circuit 200.
4 can be controlled. In addition, a signal line for transmitting the promotion signal and the suppression signal can be shortened.

By arranging the central control circuit 200 near the heat generation center on the semiconductor substrate, the temperature change can be immediately reflected on the outputs of the Vint generating circuits 231 to 234. However, there is no particular problem whether the power supply lines of each voltage level are connected to each other or not.

[0132]

As described above, according to the semiconductor integrated circuit of the present invention, the difference between the delay time of the first delay circuit and the delay time of the second delay circuit is eliminated. By controlling the output line voltage of the constant voltage generating circuit, fluctuations in the delay time of the peripheral circuit are effectively compensated through automatic control of the power supply voltage. In other words, even if a delay circuit composed of a normal inverter chain is used for a peripheral circuit, the temperature dependence of the delay time is corrected. Reduced. According to the second aspect of the present invention, it is not necessary to supply a special pulse signal for detecting the delay time difference from outside the semiconductor integrated circuit. According to the third and fourth aspects of the present invention, the difference between the delay times of the first and second delay circuits is converted into a difference in pulse width, and the difference in pulse width is converted into the number of logic signals having a predetermined logic level. Converted,
The output line voltage of the constant voltage generation circuit is changed according to the number of the logic signals. In addition, the use of the reference potential generating circuit of the present invention in the constant voltage generating circuit reduces the temperature dependence of the output line potential. According to the fifth and sixth aspects of the present invention, the presence or absence of the delay time difference between the first and second delay circuits is detected within a certain range of the dead band, so that the fluctuation of the output voltage of the constant voltage generation circuit can be prevented. it can. According to the seventh and eighth aspects of the invention, it is possible to detect a small delay time difference between the first and second delay circuits. According to the ninth aspect, the delay characteristic of the row decoder is matched with the delay characteristic of the word line, so that a semiconductor memory device capable of high-speed access with a reduced timing margin for activation of the sense amplifier can be realized.

According to the semiconductor integrated circuit of the tenth aspect, by controlling the potential of the output line as the stabilized output voltage based on the difference in delay time between the first and second delay circuits. The delay time of a plurality of circuit blocks using the stabilized output voltage as a power source is kept constant. Thus, a highly reliable semiconductor integrated circuit can be realized. According to the eleventh aspect of the present invention, since the constant voltage generating circuits are dispersedly arranged on the semiconductor substrate so as to be close to each of the plurality of circuit blocks, the output current of each constant voltage generating circuit can be reduced. . In addition, the outputs of the plurality of constant voltage generation circuits can be centrally controlled with only two signal lines for transmitting the promotion signal and the suppression signal output from one delay time difference detection circuit. Claim 12
According to the invention, since the first and second delay circuits are arranged substantially at the center on the semiconductor substrate, it is possible to control the output of each constant voltage generating circuit based on the average temperature on the semiconductor substrate. . In addition, a signal line for transmitting the promotion signal and the suppression signal can be shortened. According to the invention of claim 13, the first
Further, since the second delay circuit is arranged near the heat generation center on the semiconductor substrate, the temperature change can be immediately reflected on the output of each constant voltage generation circuit.

[0134]

[0135]

[0136]

According to the power supply circuit of the fourteenth aspect , by controlling the potential of the output line as the stabilized output voltage based on the difference in delay time between the first and second delay circuits, The delay time of the logic circuit using the stabilized output voltage as a power source is kept constant. According to the invention of claim 15 ,
The first delay circuit having small temperature dependence is realized as a CR delay circuit. According to the sixteenth aspect , it is possible to control the output line potential with only two signal lines for transmitting the promotion signal and the suppression signal output from the delay time difference detection circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first configuration example of a reference potential generation circuit according to a first example of the present invention.

FIG. 2 is a circuit diagram of a second configuration example of the reference potential generation circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a third configuration example of the reference potential generation circuit according to the first example of the present invention.

FIG. 4 is a circuit diagram of a fourth configuration example of the reference potential generation circuit according to the first example of the present invention.

FIG. 5 is a circuit diagram of a fifth configuration example of the reference potential generation circuit according to the first example of the present invention.

FIG. 6 is a circuit diagram of a sixth configuration example of the reference potential generation circuit according to the first example of the present invention.

FIG. 7 is a graph showing the effect of improving the temperature dependency of the output potential by the reference potential generation circuit according to the first example of the present invention.

FIG. 8 is a circuit diagram of a first configuration example of a constant voltage generation circuit according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram illustrating a configuration example of a comparator circuit in FIG. 8;

10 is an explanatory diagram showing that the comparator circuit of FIG. 9 may not perform a normal comparison operation in some cases.

FIG. 11 is a circuit diagram of a second configuration example of the constant voltage generation circuit according to the second embodiment of the present invention.

FIG. 12 is a circuit diagram of a third configuration example of the constant voltage generation circuit according to the second embodiment of the present invention.

FIG. 13 is a circuit diagram showing a first configuration example of a voltage level detection circuit according to a third example of the present invention.

FIG. 14 is a circuit diagram showing a second configuration example of the voltage level detection circuit according to the third embodiment of the present invention.

FIG. 15 is a circuit diagram showing a third configuration example of the voltage level detection circuit according to the third embodiment of the present invention.

FIG. 16 is a circuit diagram showing a fourth configuration example of the voltage level detection circuit according to the third embodiment of the present invention.

17 is a graph showing a hysteresis characteristic of the voltage level detection circuit of FIG.

FIG. 18 is a circuit diagram of a first configuration example of a temperature detection circuit according to a fourth embodiment of the present invention.

FIG. 19 is a circuit diagram of a second configuration example of the temperature detection circuit according to the fourth embodiment of the present invention.

FIG. 20 is a circuit diagram of a third configuration example of the temperature detection circuit according to the fourth embodiment of the present invention.

FIG. 21 is a circuit diagram of a fourth configuration example of the temperature detection circuit according to the fourth embodiment of the present invention.

FIG. 22 is a graph showing a hysteresis characteristic of the temperature detection circuit of FIG.

FIG. 23 is a circuit diagram showing a first configuration example of an active control type power supply circuit according to a fifth embodiment of the present invention.

FIG. 24 is a circuit diagram showing a second configuration example of the active control type power supply circuit according to the fifth embodiment of the present invention.

FIG. 25 is a circuit diagram showing a third configuration example of the active control type power supply circuit according to the fifth embodiment of the present invention.

FIG. 26 is a circuit diagram showing a first configuration example of a semiconductor integrated circuit according to a sixth embodiment of the present invention.

FIG. 27 is a circuit diagram showing a configuration of a delay time difference detection circuit in FIG. 26;

28 is a timing chart showing signal waveforms at various parts of the delay time difference detection circuit of FIG. 27;

FIG. 29 is a circuit diagram showing a configuration of a control circuit in FIG. 26;

FIG. 30 is a circuit diagram showing a configuration of a constant voltage generation circuit in FIG. 26;

FIG. 31 is a circuit diagram showing a second configuration example of the semiconductor integrated circuit according to the sixth embodiment of the present invention.

FIG. 32 is a timing chart showing signal waveforms at various points in FIG. 31 when τ1> τ2.

FIG. 33 is a view similar to FIG. 32, where τ1 <τ2;

FIG. 34 is a circuit diagram showing a third configuration example of the semiconductor integrated circuit according to the sixth embodiment of the present invention.

FIG. 35 is a timing chart showing input / output signal waveforms of the delay time difference detection circuit in FIG. 34 when τ1> τ2.

36 is a diagram similar to FIG. 35 when τ1 <τ2.

FIG. 37 is a circuit diagram showing a fourth configuration example of the semiconductor integrated circuit according to the sixth embodiment of the present invention.

FIG. 38 is a circuit diagram showing a fifth configuration example of the semiconductor integrated circuit according to the sixth embodiment of the present invention.

FIG. 39 is a circuit diagram showing a sixth configuration example of the semiconductor integrated circuit according to the sixth embodiment of the present invention.

FIG. 40 is a circuit diagram showing a configuration example of a semiconductor integrated circuit using a conventional CR delay circuit.

[Explanation of symbols]

Reference Signs List 1 power supply line (second voltage supply line) 2 output node 3 ground line (first voltage supply line, reference potential line) 4 resistor element 5 N-type MOSFET 6, 7, 8 N-type MOSFET (MOS diode) 9 P Type MOSFET 10 N-type MOSFET 11 Control input terminal 12, 13, 14, 15 Resistance element 16, 17, 18 P-type MOSFET 19, 20, 21 Control input terminal 22, 23 P-type MOSFET 24, 25 Control input terminal 31 Power supply line (First voltage supply line, reference potential line) 32 output node 33 ground line (second voltage supply line) 34 resistive element 35 P-type MOSFET 36, 37, 38 P-type MOSFET (MOS diode) 39 N-type MOSFET 41 Reference potential generation circuit (first reference potential generation circuit) 41a Output node (first node) of reference potential generation circuit 42 Comparator circuit 43 P-type MOSFET (driver circuit) 44 Output line 45 Capacitor element 46 Voltage shift circuit (second reference potential generation circuit) 46a Input node of voltage shift circuit 46b Output node (second node) of voltage shift circuit 47a , 47b Differential N-type MOSFET 48a, 48b Current mirror P-type MOSFET 49 Common N-type MOSFET 51 Reference potential generation circuit (first reference potential generation circuit) 52 Comparator circuit 53 P-type MOSFET (driver circuit) 54 Output line 55 Capacitor Element 56 Voltage shift circuit (second reference potential generation circuit) 57 Control circuit 61, 65 First reference potential generation circuit 61a, 65a First node 62, 66 Second reference potential generation circuit 62a, 66a Second Node 63, 67 Comparator circuit 6 , 70 hysteresis control circuit 71, 75 first reference potential generation circuit 71a, 75a first node 72, 76 second reference potential generation circuit 72a, 76a second node 73, 77 comparator circuit 79, 80 hysteresis control circuit 81a, 84a Constant voltage generation circuit 81b, 84b Control circuit 82, 85 Programmable constant voltage generation circuit 83, 86 Temperature detection circuit 91 Pulse generation circuit 92 First delay circuit 93 Second delay circuit 94 Delay time difference detection circuit 95 Active voltage Control circuit 101, 141, 161, 171, 181 Pulse generating circuit 102, 142, 162, 172, 182 First delay circuit 103, 143, 163, 173, 183 Second delay circuit 104, 144, 164, 174, 184 delay time difference detection circuit 105,145, 65, 175, 185 Control circuit 106, 146, 166, 176, 186 Constant voltage generation circuit 107, 147, 167, 177, 187 Peripheral circuit 111a, 111b, 115a, 115b Delay circuit section 112a, 112b, 113a, 113b, 114 , 1
16a, 116b NAND circuit 121, 122 Latch circuit 123, 124, 125, 126 Switching element 131 Reference potential generation circuit 131a Output node of reference potential generation circuit 132 Comparator circuit 133 Driver circuit 134 Output line of constant voltage generation circuit 151 NOR circuit ( OR circuit) 153 First latch circuit 158 Second latch circuit 168 Flip-flop 169 Monostable multivibrator 188 Row decoder 189 Timing circuit 190 Sense amplifier 200 Central control circuit (substrate potential control circuit, specific potential control circuit, active voltage) Control circuit) 201, 202, 203, 204 Circuit block 211, 212 VPP generation circuit (specific potential generation circuit) 221, 222 VBB generation circuit (substrate potential generation circuit) 231, 232, 23 , 234 Vint generation circuit R resistance means F feedback means D diode means S short circuit means C control signal VCC external power supply voltage level VSS ground potential VBB substrate bias level (substrate potential, voltage level to be measured) VPP word line boost level (voltage to be measured) Level) Vint Internal step-down level φ1 Board level detection output φ2 Step-up level detection output

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Fujiwara 1006 Kadoma, Kazuma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-2-306494 (JP, A) JP-A-1- 124011 (JP, A) JP-A-4-366492 (JP, A) JP-A-4-247714 (JP, A) JP-A-63-69315 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/407 H03K 19/0944

Claims (16)

(57) [Claims] 1. A semiconductor integrated circuit comprising: a peripheral circuit; and a delay time correction circuit for correcting a delay time of the peripheral circuit, wherein the delay time correction circuit includes a second delay circuit for delaying a pulse signal. 1 delay circuit; and a logic circuit for delaying the same pulse signal as the pulse signal supplied to the first delay circuit, wherein the logic circuit is the same as the peripheral circuit and is the first delay circuit. A second delay circuit having a delay time temperature dependence different from that of the first delay circuit and having a delay time of a pulse signal at a reference temperature set to coincide with the first delay circuit; A constant voltage generation circuit for holding a potential of an output line used as a supply line of a stabilized power supply voltage to each of the circuits at a constant value that can be changed according to a control signal; and the first and second delays Output signal of each circuit When the delay time of the second delay circuit is larger than the delay time of the first delay circuit, a promotion signal is output, and the delay time of the second delay circuit is equal to the first delay time. A delay time difference detection circuit for outputting a suppression signal when the delay time is smaller than the delay time of the delay circuit; and increasing the potential of the output line each time a promotion signal is received from the delay time difference detection circuit, and And a control circuit for outputting a control signal to the constant voltage generation circuit so as to decrease the potential of the output line each time the suppression signal is received from the delay time difference detection circuit. circuit. 2. The semiconductor integrated circuit according to claim 1, wherein said delay time correction circuit further includes a pulse generation circuit for supplying a common pulse signal to said first and second delay circuits. Characteristic semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 1, wherein the delay time difference detection circuit includes a circuit for outputting first and second detection signals as the promotion signal and the suppression signal. Each of the second detection signals has a pulse that transits at the same time, and when the delay time of the second delay circuit is longer than the delay time of the first delay circuit, the pulse of the second detection signal The pulse width of the second detection signal is greater than the pulse width of the first detection signal, and if the delay time of the second delay circuit is smaller than the delay time of the first delay circuit, A semiconductor integrated circuit, wherein the pulse width is smaller than a pulse width of a first detection signal. 4. The semiconductor integrated circuit according to claim 3, wherein said control circuit includes a circuit for outputting a plurality of logic signals as said control signal, and has a predetermined logic level among said plurality of logic signals. 2. The semiconductor integrated circuit according to claim 1, wherein the number of logic signals is changed according to a difference between pulse widths of the first and second detection signals output from the delay time difference detection circuit. 5. The semiconductor integrated circuit according to claim 1, wherein the second delay circuit is configured to receive a reference signal whose delay time at a reference temperature is set to coincide with an output signal of the first delay circuit. And a circuit for outputting a first output signal having a delayed phase and a second output signal having a leading phase with respect to the reference signal, respectively. The delay time of the first delay circuit and the delay time of the second delay circuit are determined according to the input timing of the first and second output signals of the second delay circuit with respect to the input timing of the output signal of the circuit. And a second detection signal indicating which one of the first and second delay circuits has a longer delay time is output as the promotion signal and the suppression signal. Equipped with circuits for When the delay time of the second delay circuit is longer than the delay time of the first delay circuit, a first detection signal indicating the existence of a delay time difference and a second detection signal having a first logic level are provided. If the delay time of the second delay circuit is smaller than the delay time of the first delay circuit, a second detection signal indicating the existence of a delay time difference and a second logic level having a second logic level are provided.
Wherein each of the detection signals is output from the delay time difference detection circuit. 6. The semiconductor integrated circuit according to claim 5, wherein said delay time difference detection circuit outputs an output signal of said first delay circuit and first and second output signals of said second delay circuit, respectively. An OR circuit serving as an input signal; a first latch circuit for outputting the first detection signal by latching an output signal of the OR circuit; and a first latch circuit from the first latch circuit. And a second latch circuit for outputting the second detection signal by latching an output signal of the first delay circuit at an output timing of the detection signal. 7. The semiconductor integrated circuit according to claim 1, wherein the delay time difference detection circuit is configured to respond to an input timing of an output signal of the second delay circuit with respect to an input timing of an output signal of the first delay circuit. A first detection signal indicating which one of the first and second delay circuits has a longer delay time, and a first detection signal indicating a delay time of the first delay circuit and a delay time of the second delay circuit. A circuit for outputting a second detection signal indicating the presence or absence of a difference as the promotion signal and the suppression signal, wherein a delay time of the second delay circuit is longer than a delay time of the first delay circuit Is when the first detection signal having the first logic level and the second detection signal indicating the existence of the delay time difference are different in that the delay time of the second delay circuit is smaller than the delay time of the first delay circuit Has a second logical level A second detection signal indicating the existence of the delay time difference from the first detection signal having the first detection signal.
Wherein each of the detection signals is output from the delay time difference detection circuit. 8. The semiconductor integrated circuit according to claim 7, wherein said delay time difference detection circuit converts said first detection signal by amplifying a potential difference between output signals of said first and second delay circuits. And a flip-flop for outputting the second detection signal having a constant pulse width triggered by a transition of one of the output signals of the first and second delay circuits. A semiconductor integrated circuit comprising a monostable multivibrator. 9. The semiconductor integrated circuit according to claim 1, wherein the peripheral circuit includes a row decoder for selecting a memory cell via a word line, and an output line of the constant voltage generation circuit is connected to the second line. A semiconductor integrated circuit used as a power supply voltage supply line to each of the delay circuit and the row decoder. 10. The plurality of circuits by increasing the potential of an output line as a stabilized output voltage used as a common power supply for a plurality of circuit blocks each constituted by a logic circuit on a semiconductor substrate as the temperature rises. A semiconductor integrated circuit configured to keep a delay time of each block constant, comprising: a first delay circuit having a small temperature dependency of a delay time of a pulse signal; and a delay of the pulse signal at a reference temperature. A second delay circuit having a logic circuit as a temperature monitor whose time is set to coincide with the first delay circuit; a delay time of the first delay circuit and a delay time of the second delay circuit When the delay time of the second delay circuit becomes longer than the delay time of the first delay circuit in accordance with the difference between the second delay circuit and the delay time of the second delay circuit, A delay time difference detection circuit for outputting a suppression signal when the delay time is smaller than the delay time of the first delay circuit; and a potential of the output line each time a promotion signal is received from the delay time difference detection circuit. A constant voltage generation circuit for raising and lowering the potential of the output line each time a suppression signal is received from the delay time difference detection circuit, and a stabilized output voltage on the output line from the constant voltage generation circuit. Is supplied as power to the second delay circuit. 11. The constant voltage generation circuit according to claim 10, wherein the first delay circuit, the second delay circuit, and the delay time difference detection circuit are each disposed on the semiconductor substrate. Are arranged on the semiconductor substrate so as to be close to each of the plurality of circuit blocks, respectively, and between each of the plurality of constant voltage generation circuits and the delay time difference detection circuit, the promotion signal is provided. And a semiconductor integrated circuit provided with two signal lines for transmitting a suppression signal. 12. The semiconductor integrated circuit according to claim 11, wherein said first and second delay circuits are arranged substantially at the center on said semiconductor substrate. 13. The semiconductor integrated circuit according to claim 11, wherein said first and second delay circuits are arranged near a heat generation center on said semiconductor substrate. 14. A power supply circuit for keeping a delay time of the logic circuit constant by increasing a potential of an output line as a stabilized output voltage used as a power supply of the logic circuit in accordance with a rise in temperature. A second delay circuit having a first delay circuit having a small temperature dependence of a signal delay time and a logic circuit serving as a temperature monitor set so that a delay time of a pulse signal at a reference temperature is equal to the first delay circuit; A delay circuit for detecting a difference between a delay time of the first delay circuit and a delay time of the second delay circuit; and a delay time of the second delay circuit. When the delay time of the second delay circuit is longer than the delay time of the first delay circuit, the potential of the output line is increased. Previous A constant voltage generation circuit for changing the potential of the output line according to the output of the delay time difference detection circuit so as to lower the potential of the output line; and stabilizing the output line from the constant voltage generation circuit. A power supply circuit, wherein the converted output voltage is supplied as power to the second delay circuit. 15. The power supply circuit according to claim 14 , wherein said first delay circuit is configured to use a time constant determined by a resistance element and a capacitor element. 16. The power supply circuit according to claim 14 , wherein said delay time difference detection circuit is configured to determine a difference between a delay time of said first delay circuit and a delay time of said second delay circuit.
If the delay time of the second delay circuit is longer than the delay time of the first delay circuit, a promotion signal is output;
And a function of outputting a suppression signal when the delay time of the second delay circuit is smaller than the delay time of the first delay circuit. Raises the potential of the output line each time a promotion signal of
And a power supply circuit having a function of lowering the potential of the output line each time a suppression signal is received from the delay time difference detection circuit.