KR0171310B1 - Growing method of epitaxial wafer for homo-junction infrared diode by double dipping - Google Patents
Growing method of epitaxial wafer for homo-junction infrared diode by double dipping Download PDFInfo
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- KR0171310B1 KR0171310B1 KR1019930021117A KR930021117A KR0171310B1 KR 0171310 B1 KR0171310 B1 KR 0171310B1 KR 1019930021117 A KR1019930021117 A KR 1019930021117A KR 930021117 A KR930021117 A KR 930021117A KR 0171310 B1 KR0171310 B1 KR 0171310B1
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- South Korea
- Prior art keywords
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- epitaxial wafer
- type layer
- homo
- double dipping
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 11
- 238000007598 dipping method Methods 0.000 title claims abstract description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052733 gallium Inorganic materials 0.000 claims description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- 238000007796 conventional method Methods 0.000 abstract description 3
- 239000010409 thin film Substances 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000155 melt Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
Abstract
본 발명은 균질접합 적외선 다이오우드용 에피택셜 웨이퍼 성장방법에 관한 것으로, 하나의 멜트를 이용하여 p형과 n형 박막을 순차적으로 성장시킬 경우 p형과 n형 계면에서 계단형 접합이 생성되지 못하고 캐리어 농도의 값이 제한되는 종래의 방법을 개선하여, 하나의 멜트를 이용하되 n형층을 성장시킨 후 다시 처음부터 p형층을 성장시키는 이중디핑(dipping) 방법이다.The present invention relates to an epitaxial wafer growth method for homogeneous bonded infrared diodes, wherein when a p-type and n-type thin film is sequentially grown using one melt, stepped junctions are not generated at the p-type and n-type interfaces. It is a double dipping method to improve the conventional method of limiting the value of the concentration, by using one melt but growing the n-type layer and then growing the p-type layer from the beginning.
Description
제1도는 균질접합(Homo-junction) 적외선 다이오우드의 구조를 나타내는 도면.1 shows the structure of a Homo-junction infrared diode.
제2도는 종래의 성장 공정 및 이에따른 온도조건을 나타내는 그래프도.2 is a graph showing a conventional growth process and the resulting temperature conditions.
제3도는 본 발명의 성장 및 이에따른 온도조건을 나타내는 그래프도.3 is a graph showing the growth of the present invention and the resulting temperature conditions.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 갈륨비소 기판 2 : n형층1: gallium arsenide substrate 2: n-type layer
3 : p형층 4 : 금속전극3: p-type layer 4: metal electrode
본 발명은 균질접합 적외선 다이오우드(IRED)용 에피택셜 웨이퍼 성장방법에 관한 것으로 특히, 에피택셜층 성장시 에피택셜층의 특성을 개선하기 위하여 이중디핑(Dipping)법에 의한 적외선 다이오우드용 에피택셜층 성장방법에 관한 것이다.The present invention relates to an epitaxial wafer growth method for homogeneous bonded infrared diodes (IRED), in particular to grow the epitaxial layer for infrared diodes by a double dipping method to improve the characteristics of the epitaxial layer during epitaxial layer growth. It is about a method.
일반적으로, 제1도에 도시한 바와같은 균질접합 적외선 다이오우드용 에피택셜층을 성장시키기 위하여는 도판트로 실리콘을 사용하여 1-멜트 성장(one-meltgrowth)을 하였는데, 실리콘은 성장시 온도에 따라 p형 도판트나 n형 도판트로 작용할 수 있기 때문에, 제2도에 도시한 바와같이 에피택셜층을 성장시키고자 하는 기판을 멜트에 담그고 온도를 내리면 순차적으로 n형 에피택셜층과 p형 에피택셜층이 성장되는 것이다.Generally, in order to grow an epitaxial layer for homogeneous bonded infrared diodes as shown in FIG. 1, one-meltgrowth was performed using silicon as a dopant. As it can act as a dopant or an n-type dopant, as shown in FIG. 2, when the substrate to be grown is melted and the temperature is lowered, the n-type epitaxial layer and the p-type epitaxial layer are sequentially It is growing.
그러나, 이와같은 종래의 방법으로 성장된 에피택셜층의 경계면은 실리콘 특성상 계단형 접합(abrupt junction)이 생성되지 못한다.However, the interface of the epitaxial layer grown by such a conventional method does not generate an abrupt junction due to the silicon properties.
왜냐하면, 성장초기 온도에서 실리콘은 n형 도판트로 작용하는 양이 더 많아서 n형층을 형성하나 온도가 점점 내려가면서 p형 도판트로 작용하는 양이 많아지면서 p형층을 형성하게 된다. 이때 n형층과 p형층의 경계가 접합(Juction)이 되는데, 이접합은 점전적인 경사형 접합이 되며 경계면은 에피택셜층이 성장되어 지는 전기로의 온도 안정도 여하에 따라 멀티-인터페이스(mult-interface)가 생기거나 불균일한 경계면이 형성되기 쉽다.Because, at the initial growth temperature, silicon forms an n-type layer because it acts as an n-type dopant, but as the temperature decreases, it acts as a p-type dopant and forms a p-type layer. At this time, the boundary between the n-type and p-type layers is a junction. The junction is an gradual gradient junction, and the interface is a multi-interface depending on the temperature stability of the electric furnace in which the epitaxial layer is grown. Or irregular surfaces are likely to be formed.
이러한 불균일한 경계면은 적외선 다이오우드를 만들었을때 발광효율이 저하되게 되는 직접적 원인이 된다.This non-uniform interface is a direct cause of lowering the luminous efficiency when the infrared diode is made.
또한, 발광효율에 영향을 주는 다른 변수는 에피택셜층에 존재하는 캐리어 농도(Carrier Concentration)인데, 상기한 종래의 방법으로 성장을 시키면 발광효율을 높이기 위한 농도조절이 용이하지 못하다.In addition, another variable affecting the luminous efficiency is a carrier concentration present in the epitaxial layer. When the growth is performed by the conventional method, it is not easy to adjust the concentration to increase luminous efficiency.
이것은 갈륨멜트에 존재하는 실리콘의 농도에 따라 n층에서 p층으로 바뀌는 전이온도가 변동되기 때문이며 이로인해 성장시키고자 하는 에피택셜층의 두께를 고정하면 얻을 수 있는 캐리어 농도의 값이 제한되기 때문이다.This is because the transition temperature, which changes from n to p layers, varies depending on the concentration of silicon present in the gallium melt, which limits the value of the carrier concentration that can be obtained by fixing the thickness of the epitaxial layer to be grown. .
본 발명은 상기한 문제점을 해결하기 위하여 창안한 것으로서, n형층과 p형층의 경계면이 균일한 경계면을 갖는 에피택셜층 성장방법을 제공하는 것을 목적으로 한다. 이와같은 목적을 달성하기 위하여 본 발명의 성장방법은 1-멜트를 사용하되, n형층과 p형층을 따로따로 독립적으로 성장시킴으로서 n형층과 p형층의 경계면이 명확하게 p형층의 정공(hole)의 농도를 원하는 수준으로 조절하는 것이다.The present invention has been made to solve the above problems, and an object of the present invention is to provide an epitaxial layer growth method in which an interface between an n-type layer and a p-type layer has a uniform interface. In order to achieve the above object, the growth method of the present invention uses 1-melt, but grows the n-type layer and the p-type layer independently, so that the interface between the n-type layer and the p-type layer is clearly defined by holes of the p-type layer. The concentration is adjusted to the desired level.
즉, 제3도에 도시한 바와같이, n형층을 성장시킨 후에 웨이퍼을 꺼내어 갈륨에칭과 세척을 한후, 상기 웨이퍼를 다시 장입하여 더 낮은 온도 (즉, p형 도판트로 들어가는 양이 n형 도판트로 들어가는 양보다 훨씬 더 많은 상태의 온도)에서 성장시키는 것이다.That is, as shown in FIG. 3, after the n-type layer is grown, the wafer is taken out, gallium etched and cleaned, and the wafer is charged again to lower temperature (that is, the amount of p-type dopant entering the n-type dopant). Growing at much higher temperatures than quantities).
이와같은 본 발명의 방법에 따르면 n형층과 p형층을 따로따로 성장시킴으로서 원하는 두께 및 원하는 캐리어 농도(Carrier Concentration)를 갖는 에피택셜층을 성장시킬수 있으며 접합면에서 계단형 접합을 만들 수 있는 동시에 균일한 접합면을 성장시킬 수 있는 것이다.According to the method of the present invention, by growing the n-type layer and the p-type layer separately, it is possible to grow an epitaxial layer having a desired thickness and a desired carrier concentration, and at the same time can make a stepped junction at the same time uniform It is possible to grow the joint surface.
[실시예]EXAMPLE
1)갈륨 : 300g, 갈륨비수 : 40g, 실리콘 : 600mg을 도가니에 장입하고 웨이퍼를 웨이퍼홀더에 장입한다.1) Load gallium: 300g, gallium ratio: 40g, silicon: 600mg into the crucible and load the wafer into the wafer holder.
2)온도를 950℃ 까지 올려서 멜트를 균질화하고 평형온도 까지 내린후 웨이퍼를 멜트에 담근다.2) Homogenize the melt by raising the temperature to 950 ℃, lower the equilibrium temperature, and soak the wafer in the melt.
3)웨이퍼 표면의 손상 제거를 위해 온도를 다시 올려 백멜팅(back melting)을 한다.3) In order to remove the damage on the surface of the wafer, increase the temperature again and perform back melting.
4)온도를 서서히 내리며 (0.4℃ / min) n층을 성장시킨다.4) Grow down the temperature slowly (0.4 ℃ / min) and grow n layers.
5)냉각과정을 거친후 웨이퍼를 꺼내어 갈륨을 제거하고 다시 세척을 한다.5) After cooling, remove the wafer, remove gallium and clean again.
6)갈륨 : 300g, 갈륨비소 : 40g, 실리콘 : 1300mg을 도가니에 장입하고 웨이퍼를 장입한 후 2-5번 까지의 과정을 반복한다.6) Load gallium: 300g, gallium arsenide: 40g, silicon: 1300mg into the crucible, load the wafer and repeat the process up to 2-5 times.
이렇게 해서 p형층과 n형층의 경계면이 양호하고 p형층 평면의 캐리어 농도가 2×1018/ ㎤ 인 특성이 좋은 에피택셜 웨이퍼를 얻을 수 있었다.In this way, an epitaxial wafer having a good interface between the p-type layer and the n-type layer and having a carrier concentration of 2 × 10 18 / cm 3 in the p-type layer plane was obtained.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930021117A KR0171310B1 (en) | 1993-10-12 | 1993-10-12 | Growing method of epitaxial wafer for homo-junction infrared diode by double dipping |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930021117A KR0171310B1 (en) | 1993-10-12 | 1993-10-12 | Growing method of epitaxial wafer for homo-junction infrared diode by double dipping |
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| Publication Number | Publication Date |
|---|---|
| KR950012777A KR950012777A (en) | 1995-05-17 |
| KR0171310B1 true KR0171310B1 (en) | 1999-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019930021117A KR0171310B1 (en) | 1993-10-12 | 1993-10-12 | Growing method of epitaxial wafer for homo-junction infrared diode by double dipping |
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1993
- 1993-10-12 KR KR1019930021117A patent/KR0171310B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR950012777A (en) | 1995-05-17 |
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