KR0170239B1 - Automatic gain control - Google Patents
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- KR0170239B1 KR0170239B1 KR1019910001510A KR910001510A KR0170239B1 KR 0170239 B1 KR0170239 B1 KR 0170239B1 KR 1019910001510 A KR1019910001510 A KR 1019910001510A KR 910001510 A KR910001510 A KR 910001510A KR 0170239 B1 KR0170239 B1 KR 0170239B1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
Abstract
본 발명은 무선통신수신기에 있어서 디지탈 신호처리기(DSP)를 이용하여 AGC증폭기의 이득제어전압을 발생시키는 자동이득제어장치에 관한 것이다. 종래의 자동이득제어장치는 아날로그회로로 구성되므로 하드웨어의 양이 많고 고주파신호로 동작하므로 집적회로의 제작이 어려워 소형화를 이룰 수 없었다. 따라서 본 발명은 AGC증폭부(10), 반송파복구부(20), 위상천이부(30), 제1, 2혼합부(40, 50), 제1, 2저역 통과필터(60, 70), 제1, 2아날로그/디지탈신호변환부(80, 90), 디지탈신호처리부(100), 디지탈/아날로그신호변환부(110) 및 제3저역통과필터(120)를 포함함으로써 AGC증폭부(10)를 제어하는 직류전압을 DSP로 구성된 디지탈신호처리부(100)의 소프트웨어 프로그램으로 발생시킴으로써 하드웨어를 줄여 집적회로의 제작이 용이하고 장비의 소형화를 이룰 수 있도록 하였다.The present invention relates to an automatic gain control apparatus for generating a gain control voltage of an AGC amplifier using a digital signal processor (DSP) in a wireless communication receiver. Since the conventional automatic gain control device is composed of analog circuits, since the amount of hardware is large and the high-frequency signals are operated, fabrication of integrated circuits is difficult and miniaturization cannot be achieved. Accordingly, the present invention provides the AGC amplifier 10, the carrier recovery unit 20, the phase shifter 30, the first and second mixing units 40 and 50, the first and second low pass filters 60 and 70, The AGC amplifier 10 includes the first and second analog / digital signal converters 80 and 90, the digital signal processor 100, the digital / analog signal converter 110, and the third low pass filter 120. By generating the DC voltage to control the digital signal processing unit 100 is composed of a software program of the DSP to reduce the hardware to manufacture the integrated circuit and to make the miniaturization of the equipment.
Description
제1도는 종래기술에 의한 자동이득제어장치의 구성도.1 is a block diagram of a conventional automatic gain control apparatus.
제2도는 본 발명에 의한 자동이득제어장치의 구성도.2 is a block diagram of an automatic gain control device according to the present invention.
제3도는 제2도에 도시된 자동이득제어장치의 흐름도.3 is a flowchart of the automatic gain control device shown in FIG.
제4도는 제3도에 도시된 프로그램 수행시 자동이득제어장치의 단계별 파형도.4 is a step-by-step waveform diagram of the automatic gain control device when performing the program shown in FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : AGC증폭부 20 : 반송파복구부10: AGC amplification part 20: carrier recovery part
30 : 위상천이부 40, 50 : 제1, 2혼합부30: phase shifter 40, 50: first, second mixing section
60, 70 : 제1, 2저역통과필터60, 70: 1st, 2nd low pass filter
80, 90 : 제1, 2아날로그/디지탈신호변환부80, 90: 1st, 2 analog / digital signal converter
100 : 디지탈신호처리부 110 : 디지탈/아날로그신호변환부100: digital signal processing unit 110: digital / analog signal conversion unit
120 : 제3저역통과필터120: third low pass filter
본 발명은 자동이득제어장치에 관한 것으로, 특히 무선통신수신기에 있어서 디지탈신호처리기(Digital Signal Processor; DSP)를 이용하여 AGC(Automatic Gain Control) 증폭기의 이득제어전압을 발생시키는 자동이득제어장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control apparatus, and more particularly, to an automatic gain control apparatus for generating a gain control voltage of an automatic gain control (AGC) amplifier using a digital signal processor (DSP) in a wireless communication receiver. will be.
통상적으로 아날로그회로를 사용하는 자동이득제어장치는 제1도에 도시된 바와 같이 AGC(Automatic Gain Control) 증폭기(1), 전파정류기(2), 저역통과필터(3), 직류증폭기(4) 및 복조기(5)로 구성된다. AGC증폭기(1)는 수신기에서 수신 IF(Intermediate Frequency) 신호의 크기를 일정하게 유지시키는 기능을 수행하는 바, 이 AGC증폭기(1)의 이득제어신호를 발생시키기 위하여 전파정류기(2), 저역통과필터(3) 및 직류증폭기(4)를 이용하였다. 그런데, 이와 같은 자동이득제어장치는 아날로그회로로 구성되므로 하드웨어의 양이 많고 고주파(RF; Radio Frequency)신호로 동작하므로 집적회로의 제작이 어려워 소형화를 이룰 수 없는 문제점이 있었다.In general, an automatic gain control apparatus using an analog circuit includes an AGC (Automatic Gain Control) amplifier 1, a full-wave rectifier 2, a low pass filter 3, a direct current amplifier 4, and the like. And a demodulator 5. The AGC amplifier 1 performs a function of maintaining a constant magnitude of an intermediate frequency (IF) signal at the receiver. The AGC amplifier 1 generates a gain control signal of the AGC amplifier 1 and a low pass. A filter 3 and a direct current amplifier 4 were used. However, since the automatic gain control device is composed of an analog circuit, the amount of hardware is large and the RF controller operates as a radio frequency (RF) signal, thus making it difficult to manufacture an integrated circuit, thereby making it impossible to achieve miniaturization.
따라서 본 발명은 상기 문제점을 해결하기 위하여 창출한 것으로서 DSP와 디지탈회로를 사용하는 복조방식의 자동이득제어에 이용함으로써 집적회로의 제작을 용이하게 하는 자동이득제어장치를 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide an automatic gain control device that facilitates fabrication of integrated circuits by using the demodulation method using automatic gain control using a DSP and a digital circuit.
상기 목적을 달성하기 위하여 본 발명은, 수신 IF 신호를 받아 그 신호레벨을 일정하게 유지시키는 AGC증폭부와, 상기 AGC증폭부에 입력되는 수신 IF신호의 반송파를 재생시키는 반송파복구부와, 상기 반송파복구부에서 전송되는 반송파의 위상을 소정각도로 천이시키는 위상천이부와, 상기 AGC증폭부의 출력신호를 반송파복구부와 위상천이부에서 각각 전송되는 반송파에 실어 보내는 제1, 2혼합부와, 상기 제1, 2혼합부에서 전송되는 각 신호의 고조파성분을 제거하여 소정채널의 기저대역신호를 출력하는 제1, 2저역통과필터와, 상기 제1, 2저역통과필터에서 각각 전송되는 소정채널의 기저대역신호를 디지탈신호로 샘플링하는 제1, 2아날로그/디지탈신호변환부와, 상기 제1, 2아날로그/디지탈신호변환부에서 샘플링된 디지탈신호를 받아 내장된 프로그램을 수행함으로써 디지탈 직류전압값 및 복조데이타를 출력하는 디지탈신호처리부와, 상기 디지탈신호처리부에서 전송되는 디지탈 직류전압값을 아날로그신호로 변환시켜 AGC증폭부를 제어하는 디지탈/아날로그신호변환부와, 상기 디지탈/아날로그신호변환부에서 디지탈직류전압값을 아날로그신호로 변환시킬 때 발생되는 양자화잡음을 제거하는 제3저역통과필터를 포함함을 특징으로 한다.In order to achieve the above object, the present invention provides an AGC amplifier for receiving a received IF signal and maintaining the signal level constant, a carrier recovery unit for reproducing a carrier of the received IF signal input to the AGC amplifier, and the carrier A phase shifter for shifting the phase of the carrier wave transmitted by the recovery unit at a predetermined angle, first and second mixing units which carry the output signals of the AGC amplifier part to the carriers transmitted from the carrier recovery unit and the phase shifter, respectively; First and second low pass filters outputting a baseband signal of a predetermined channel by removing harmonic components of each signal transmitted from the first and second mixing units, and a predetermined channel of the predetermined channel transmitted from the first and second low pass filters, respectively. A program embedded in the first and second analog / digital signal converters for sampling the baseband signal into a digital signal and a digital signal sampled by the first and second analog / digital signal converters A digital signal processor for outputting a digital DC voltage value and demodulated data, a digital / analog signal converter for controlling an AGC amplifier by converting the digital DC voltage value transmitted from the digital signal processor into an analog signal, and the digital / And a third low pass filter for removing quantization noise generated when the analog signal converter converts the digital DC voltage value into an analog signal.
이하 첨부한 도면을 참조하여 본 발명을 상세히 기술하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 의한 자동이득제어장치의 구성도이다.2 is a configuration diagram of an automatic gain control device according to the present invention.
제2도에 의하면, AGC증폭부(10)는 수신 IF신호를 받아 그 신호레벨을 일정하게 유지시킬 수 있도록 이루어져 있으며, 반송파복구부(20)는 AGC증폭부(10)에 입력되는 수신 IF신호의 반송파를 재생시킬 수 있도록 이루어져 있다.2, the AGC amplifier 10 receives the received IF signal and maintains the signal level constant. The carrier recovery unit 20 receives the received IF signal input to the AGC amplifier 10. Referring to FIG. It is made to reproduce the carrier of the.
위상천이부(30)는 반송파복구부(20)로부터 입력되는 반송파의 위상을 90°로 천이시킬 수 있도록 이루어져 있다.The phase shift unit 30 is configured to shift the phase of the carrier wave input from the carrier recovery unit 20 to 90 °.
AGC증폭부(10)의 출력은 제1, 2혼합부(40, 50)에서 반송파복구부(20)에 의해 재생된 반송파 및 이의 90°천이된 신호와 각각 곱해져서 제1, 2저역통과필터(60, 70)에 입력되고, 제1, 2저역통과필터(60, 70)는 제1, 2혼합부(40, 50)에서 전송되는 각 신호의 고조파성분이 제거되어 I채널(In-Phase Channel) 및 Q채널(Quad-Phase Channel)의 기저대역(Baseband)신호가 출력되도록 이루어져 있다.The output of the AGC amplifier 10 is multiplied by the carriers reproduced by the carrier recovery unit 20 in the first and second mixing units 40 and 50 and their 90 ° shifted signals, respectively, so as to first and second low pass filters. The first and second low pass filters 60 and 70 are input to (60 and 70), and the harmonic components of each signal transmitted from the first and second mixing units 40 and 50 are removed, thereby eliminating the I-channel (In-Phase). A baseband signal of a channel and a quad-phase channel are output.
제1, 2아날로그/디지탈신호변환부(80, 90)는 제1, 2저역통과필터(60, 70)에서 각각 전송되는 I채널 및 Q채널의 기저대역신호를 디지탈신호로 샘플링하도록 이루어져 있으며, 디지탈신호처리부(100)는 제1, 2아날로그/디지탈신호변환부(80, 90)에서 샘플링된 디지탈신호를 받아 내장된 프로그램을 수행함으로써 디지탈 직류전압값 및 복조데이타를 출력하도록 이루어져 있다.The first and second analog / digital signal converters 80 and 90 are configured to sample the baseband signals of the I and Q channels transmitted from the first and second low pass filters 60 and 70, respectively, as digital signals. The digital signal processing unit 100 receives the digital signals sampled by the first and second analog / digital signal converters 80 and 90 and executes an embedded program to output digital DC voltage values and demodulation data.
디지탈/아날로그신호변환부(110)는 디지탈신호처리부(100)에서 전송되는 디지탈 직류전압값을 아날로그신호로 변환시켜 AGC증폭부(10)를 제어하도록 이루어져 있으며, 그리고 제3저역통과필터(120)는 디지탈/아날로그신호변환부(110)에서 디지탈 직류전압값을 아날로그신호로 변환시에 발생되는 양자화 잡음을 제거하도록 이루어져 있다.The digital / analog signal conversion unit 110 is configured to control the AGC amplifier 10 by converting the digital DC voltage value transmitted from the digital signal processing unit 100 into an analog signal, and the third low pass filter 120. The digital / analog signal conversion unit 110 is configured to remove quantization noise generated when converting a digital DC voltage value into an analog signal.
상기한 바와 같은 구성을 갖는 본 발명을 보다 상세히 설명하면 다음과 같다.Hereinafter, the present invention having the configuration as described above will be described in detail.
수신된 IF신호는 AGC증폭부(10)에서 증폭되는데, AGC증폭부(10)는 제3저역통과필터(120)에서 전송되는 제어신호에 의해 이득이 제어되며 이 제어신호를 조절함으로써 출력을 일정하게 유지할 수 있다. 제1, 2혼합부(40, 50)는 AGC증폭기(10)의 출력에 반송파복구부(20)에 의해 재생된 반송파 및 위상천이부(30)에서 90°위상천이된 반송파를 각각 실어 제1, 2저역통과필터(60, 70)에 전송한다. 이때 제1, 2저역통과필터(60, 70)는 전송과정에서 발생하는 잡음 및 제1, 2혼합부(40, 50)에서 수신 IF신호와 재생된 반송파가 곱해질때 생기는 고조파성분을 제거하여 I채널 Q채널의 기저대역신호를 각각 제1, 2아날로그/디지탈신호변환부(80, 90)에 입력시킨다. 한편, I채널 및 Q채널의 기저대역신호는 제1, 2아날로그/디지탈신호변환부(80, 90)에 의해 각각 샘플링되어 제4도의 (a)파형 형태로 DSP로 구성된 디지탈신호처리부(100)에 입력되는 바, 디지탈신호처리부(100)는 내장된 프로그램을 이용하여 제3도에 도시된 본 발명에 의한자동이득제어장치의 흐름도를 수행한다. 제1, 2아날로그/디지탈신호변환부(80, 90)에서 각각 샘플링된 데이타값 IK및 QK를 디지탈신호처리부(100)가 읽어 들여(1단계) 제4도의 (b) 파형과 같이 두 샘플값의 합인 SK를 계산한다(2단계).The received IF signal is amplified by the AGC amplifier 10. The AGC amplifier 10 controls the gain by a control signal transmitted from the third low pass filter 120 and regulates the output by adjusting the control signal. I can keep it. The first and second mixing units 40 and 50 carry carriers reproduced by the carrier recovery unit 20 and carriers 90 ° out of phase shifter 30 at the output of the AGC amplifier 10, respectively. 2, low pass filter (60, 70). In this case, the first and second low pass filters 60 and 70 remove the noise generated during the transmission process and harmonic components generated when the received IF signal and the reproduced carrier wave are multiplied by the first and second mixing units 40 and 50, thereby eliminating I. The baseband signal of the channel Q channel is input to the first and second analog / digital signal converters 80 and 90, respectively. On the other hand, the baseband signal of the I-channel and Q-channel is sampled by the first and second analog / digital signal converters 80 and 90, respectively, and the digital signal processor 100 configured as DSP in the waveform form of FIG. The digital signal processing unit 100 performs a flowchart of the automatic gain control apparatus according to the present invention shown in FIG. 3 by using the built-in program. The digital signal processing unit 100 reads the data values I K and Q K sampled by the first and second analog / digital signal converters 80 and 90, respectively (step 1), as shown in the waveform (b) of FIG. Calculate S K , the sum of the sample values (step 2).
상기 제2단계를 수행하고 나서 전파정류를 하기 위해 SK값이 0보다 작은 값인지를 조사하여(3단계) 0보다 작으면 마이너스부호(-)를 취하여 SK의 절대값을 구한다(4단계). 상기 제4단계에서 구해진 SK의 절대값을 파형으로 나타내면 제4도의 (c) 파형과 같이 전파정류가 되며, 이 전파정류된 신호를 제3저역통과필터(120)에 통과시키면 제4도의 (d)와 같이 직류(DC) 전압을 샘플링한 것과 같은 신호가 된다(5단계).In order to perform full-wave rectification after performing the second step, it is examined whether the value of S K is smaller than zero (step 3). If it is less than 0, the negative sign (-) is taken to obtain the absolute value of S K (step 4 ). When the absolute value of S K obtained in the fourth step is represented as a waveform, full wave rectification is performed as shown in the waveform (c) of FIG. 4, and when the passed signal is passed through the third low pass filter 120, As in d), a signal obtained by sampling a direct current (DC) voltage is obtained (step 5).
상기 제5단계에서 전파정류된 신호가 직류전압으로 샘플링되면 AGC증폭부(10)의 이득을 제어하기 위한 직류전압을 스케일링(Scaling)한다(6단계). 통상의 AGC증폭부(10)의 다이내믹 레인지(Dymamic Range)는 약 60dB정도로서 1dB 간격으로 이득을 제어할 경우 디지탈신호처리부(100)에서 디지탈/아날로그신호변환부(110)로 출력되는 신호의 비트수가 6비트이면 충분하고 제어전압의 범위는 AGC증폭부(10)의 특성에 따라 결정된다. 제6단계에서 스케일링된 제어전압이 출력되면 디지탈/아날로그신호변환부(110)에 의해 제어전압이 발생된다(7단계). 이때 제3저역통과필터(120)는 디지탈/아날로그신호변환부(110)에 의한 양자화 잡음을 제거하기 위하여 RC회로로 구성된다.When the full-wave rectified signal is sampled with the DC voltage in the fifth step, the DC voltage for controlling the gain of the AGC amplifier 10 is scaled (step 6). In general, the dynamic range of the AGC amplifier 10 is about 60 dB, and the number of bits of the signal output from the digital signal processing unit 100 to the digital / analog signal conversion unit 110 when the gain is controlled at intervals of 1 dB. 6 bits is sufficient and the range of the control voltage is determined according to the characteristics of the AGC amplifier 10. When the scaled control voltage is output in step 6, the control voltage is generated by the digital / analog signal converter 110 (step 7). In this case, the third low pass filter 120 is configured with an RC circuit to remove the quantization noise by the digital / analog signal converter 110.
상술한 바와 같이 본 발명은 AGC증폭부를 제어하는 직류전압을 디지탈신호처리부의 소프트웨어 프로그램으로 발생시킴으로써 하드웨어를 줄여 집적회로의 제작이 용이하고 장비의 소형화가 가능한 이점이 있다.As described above, the present invention generates the DC voltage controlling the AGC amplifier by the software program of the digital signal processor, thereby reducing the hardware, making it easy to manufacture integrated circuits and miniaturizing equipment.
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| KR1019910001510A KR0170239B1 (en) | 1991-01-29 | 1991-01-29 | Automatic gain control |
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| KR1019910001510A KR0170239B1 (en) | 1991-01-29 | 1991-01-29 | Automatic gain control |
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| KR100446283B1 (en) * | 1997-08-13 | 2004-10-14 | 삼성전자주식회사 | Multi-stage programmable gain control amplifying apparatus including analog to digital converter and method for correcting gain error in response to the same, especially implementing pga and adc at the same time |
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| KR100388967B1 (en) * | 2001-04-30 | 2003-06-25 | 엘지전자 주식회사 | apparatus and method for AGC gain control embodiment using A/D convertor |
| KR100428716B1 (en) * | 2001-12-14 | 2004-04-28 | 한국전자통신연구원 | Apparatus and method for controlling automatic gain in wireless telecommunication system |
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| KR100446283B1 (en) * | 1997-08-13 | 2004-10-14 | 삼성전자주식회사 | Multi-stage programmable gain control amplifying apparatus including analog to digital converter and method for correcting gain error in response to the same, especially implementing pga and adc at the same time |
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