KR0170206B1 - Power factor compensation circuit for boost type converter - Google Patents

Abstract

The disclosed power factor correction circuit compensates for the variation of the output DC voltage to reduce current distortion and obtain high power factor, and the configuration of the circuit is simplified by maintaining the in-phase and increasing the level of the input current according to the input AC voltage without configuring the feedforward. Let's do it.

According to the present invention, a boost converter accumulates energy in a coil according to an on and off state of a switching transistor and superimposes an input DC voltage on the energy stored in the coil, and outputs a voltage signal corresponding to a current flowing when the switching transistor is turned on. The current sensing unit is generated, and the comparator voltage signal for compensating the variation of the output DC voltage and the comparison reference voltage signal whose level is varied according to the variation of the output DC voltage output by the boost converter is generated. The first signal synthesizing unit synthesizes the generated comparison reference voltage signal and the voltage signal sensed by the current sensing unit to generate a comparison signal, and the second signal synthesizing unit synthesizes the compensation voltage signal and the reverse sawtooth signal generated by the output sensing unit to output the direct current. Generates an inverted sawtooth signal in which voltage fluctuations are compensated for, and a comparison signal and a second signal of the first signal synthesis unit The comparator compares the compensated reverse sawtooth signal of the synthesizer to generate an off control signal of the switching transistor, and the driving unit turns on the switching transistor according to a clock signal synchronized with the rising edge of the reverse sawtooth signal and according to the off control signal of the comparator Turn off the switching transistor.

Description

Power factor correction circuit for boost converter with output voltage compensation

The present invention relates to a power factor correction circuit of a boost converter, and more particularly, to a power factor correction circuit of a boost converter with output voltage fluctuation compensation.

In general, DC voltage is widely used in a wide range of fields from industrial to home use.

In order to obtain the DC voltage from a commercial AC power source, a capacitor input type rectifier circuit having a simple circuit configuration is commonly used.

However, in the condenser input type rectifier circuit, since the input current flows only in the peak part of the AC voltage of the commercial AC power supply, the power factor is very pulsated because it is pulsed.

In addition, since various electrical devices have a combination of resistance, inductance, and capacitance components, the phase of the current is different from that of a commercial AC power source, resulting in a distorted output DC voltage.

In the industrial field, since a predetermined electric device is controlled using a high speed switching method, a lot of noise is generated by the high speed switching, and the electric devices connected to the same power supply line affect each other by the generated noise.

Industrial electrical devices are designed with high in-phase input power factor in order to minimize the effect of the current flowing into the electrical device itself on the commercial AC power source.

For example, inductance components have added a capacitance component to an input line of a commercial AC power source so that the input currents of the inductance and the capacitance from the power supply cancel each other.

However, there is a limit to the performance that can be achieved with these passive devices alone.

Therefore, in driving a converter system, a method of improving power factor by switching noises such as transistors at high speed, removing noise with smaller inductance and capacitance values, and suppressing voltage distortion has been studied. Various researches and integrated devices for making POWER FACTOR have been published.

In particular, the continuous current mode (hereinafter, abbreviated as 'CCM') is a method for realizing a high power factor and is known as the closest control method to obtain a unit power factor.

The CCM method includes a peak current detection method, a variable hysteresis control method, an average current control method, and the like.

These CCM schemes have the advantage of obtaining a high power factor.

However, among the above CCM methods, in the peak current detection method, current distortion and dead distortion of the current flowing to the external coil are generated, and the maximum duty cycle is maintained at 50% or less. Should not be able to compensate precisely.

In addition, the variable hysteresis control method is a variable frequency method according to the current sensing of the coil, so that when the input voltage is lowered, the frequency is infinitely increased to control the current flowing through the coil.

In addition, the average current control method has a very complicated configuration of a control method for realizing a unit power factor.

Accordingly, an object of the present invention is to provide a power factor correction circuit of a boost converter capable of compensating a variation of an output DC voltage to reduce current distortion and compensating an output voltage variation capable of obtaining a high power factor.

Another object of the present invention is to increase and decrease the level of the input current according to the AC voltage of the commercial AC power input without the configuration of the feed forward (step up) to maintain the in-phase, the output voltage fluctuation compensation to simplify the circuit configuration It is to provide a power factor correction circuit of a type converter.

According to the power factor correction circuit of a boost type converter capable of compensating the output voltage fluctuation of the present invention, energy is accumulated in the coil in the on state of the switching transistor and the energy stored in the coil in the off state of the switching transistor. A boost converter configured to superimpose and output an input DC voltage, and a current detector configured to generate a voltage signal according to a current flowing when the switching transistor is turned on, and the variation of the output DC voltage output by the boost converter and the current sense In a power factor correction circuit of a boost converter that controls the driving of the switching transistor with an additionally generated voltage signal, a comparison reference voltage signal whose level is changed in accordance with a change in an output DC voltage output by the boost converter is generated. Beam to compensate for fluctuations in output DC voltage An output detecting unit for generating a voltage signal; A first signal synthesizer configured to generate a comparison signal by combining the comparison reference voltage signal generated by the output detector and the voltage signal sensed by the current detector; A second signal synthesizing unit for synthesizing a compensation voltage signal generated by the output sensing unit and a reverse sawtooth wave signal to generate a reverse sawtooth wave signal having a variation in output DC voltage; A comparator for generating an off control signal of the switching transistor by comparing the comparison signal of the first signal synthesis unit with the compensated inverse sawtooth signal of the second signal synthesis unit; And a driving unit generating the reverse sawtooth signal and turning on the switching transistor according to a clock signal synchronized with the rising edge of the generated reverse sawtooth signal and turning off the switching transistor according to the off control signal of the comparator. do.

And the output detector; Voltage dividing means for dividing the output DC voltage of the boost converter with a resistance; An error amplifier which inputs an output voltage of the voltage dividing means and detects an error voltage according to the change of the output DC voltage to a predetermined first reference voltage source; Level reference means for generating a comparison reference voltage signal by combining the error voltage output from the error amplifier with a predetermined second reference voltage source; And compensating voltage generating means for generating a voltage signal by synthesizing the divided voltage output voltage of the voltage dividing means and the first reference voltage source and adjusting a level gain of the generated voltage signal according to the magnitude of the ripple. It features.

1 is a circuit diagram showing the configuration of a power factor correction circuit according to the present invention.

2A to 2C are waveform diagrams for explaining current distortion caused by variation in an output DC voltage.

3 is a waveform diagram illustrating the operation of the power factor correction circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

100: boost converter 200: power factor correction circuit

210: output detector 212: voltage dividing means

214: error amplifier 216: level reference means

218: compensation voltage generating means 220: current detection unit

230: first signal synthesizing unit 240: comparator

250: driving unit 260: second signal synthesizing unit

Hereinafter, a power factor correction circuit of a boost converter capable of compensating for output voltage fluctuation of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram showing a configuration of a power factor correction circuit of a boost converter according to the present invention.

As shown therein, the present invention includes a boost converter 100 and a power factor correction circuit 200.

In the boost converter 100, the commercial AC power input is rectified by the bridge rectifier 110, and the rectified power is smoothed by the smoothing capacitor C1 and converted into an input DC voltage Vin. .

The input DC voltage Vin is applied to the switching transistor MT and the rectifying diode D through the coil L.

The output power of the rectifying diode D is smoothed by the smoothing capacitor C3 and converted into an output DC voltage V0, and a load is connected to both ends of the smoothing capacitor C3, thereby outputting the output DC. The voltage V0 is applied to the operating power source.

In the CCM booster type converter 100, the commercial AC power input AC is rectified by the bridge rectifier 110, smoothed by the smoothing capacitor C1, and converted into an input DC voltage Vin.

The energy of the input DC voltage Vin is stored in the coil L when the switching transistor MT is in the on state, and the energy is stored in the coil L when the switching transistor MT is in the off state. Is superimposed on the input DC voltage Vin, rectified by the rectifying diode D, output as an output DC voltage V0 by the smoothing capacitor C3, and applied to a load. The output DC voltage V0 having a level higher than the voltage Vin may be obtained and supplied to the load.

The power factor correction circuit 200 may include an output detector 210, a current detector 220, a first signal synthesizer 230, a second signal synthesizer 260, a comparator 240, and a driver 250. It is provided.

The output detection unit 210 generates a comparison reference voltage signal V2 and a compensation voltage signal K2 · V4 whose level is changed in accordance with a change in the output DC voltage V0 of the boost converter 100. A voltage divider 212 for dividing the output DC voltage V0 of the boost converter 100 into resistors R2 and R3, and an output voltage of the voltage divider 212 to be input in advance. Operational amplifier U1, resistor R4, R5, condenser C4, and first reference voltage source, which detects an error voltage Ve0 according to the variation of the output DC voltage V0 as a first reference voltage source Vref. An error amplifier 214 composed of Vref and an error voltage Ve0 output from the error amplifier 214 are synthesized by a predetermined second reference voltage source Vref1 and the synthesizer SM1, and the comparison reference voltage signal ( Level reference means 216 for generating V2), the divided output voltage of the voltage dividing means 212 and the first reference voltage source Vref. To the compensating voltage generating means 218 for generating the compensating voltage signals K2 and V4 by adjusting the level gain of the synthesized voltage signal V4 synthesized by the genital generator SM2 according to the magnitude of the ripple. Is done.

The output detector 210 detects the ripple (ΔV0) of the output DC voltage V0 of the boost converter 100 by the error amplifier 214 as the output voltage of the voltage dividing means 212, thereby causing the error voltage Ve0. When the output DC voltage V0 is increased, the error voltage Ve0 is decreased, and when the level of the output DC voltage V0 is decreased, the error voltage Ve0 is increased.

The level reference means 216 serves to determine the reference of the comparison reference signal V3 compared with the reverse sawtooth wave signal V5 compensated by the comparator 240 to be described later. V2 = Vref1-ΔVe0 When the output DC voltage V0 increases, the comparison reference voltage signal V2 increases to increase the comparison reference signal V3. When the output DC voltage V0 decreases, the comparison reference voltage signal V2 decreases. This decreases the comparison reference signal V3.

The second reference voltage source Vref1 is a reference voltage source for inputting a ripple ΔV0 proportional to a change in the output DC voltage V0 of the boost converter 100 to the comparator 240.

The compensation voltage generator 218 compensates for the occurrence of distortion of the input control current caused by the variation of the output DC voltage V0.

Compensating accurately according to the gain K2 of the adjusting means CT and the magnitude of the ripple ΔV0 of the output DC voltage V0 generated by the capacitor C3 provided on the output side of the boost converter 100. By adjusting the gain K2, the input control current is in phase with the input DC voltage Vin regardless of the magnitude of the ripple ΔV0 of the output DC voltage V0.

Here, the operation of the compensation voltage generating means 218 will be described in more detail with reference to the drawing of FIG.

FIG. 2A shows waveforms of a change in the output DC voltage V0, an input DC voltage Vin, an input current Iin and an input control current in phase with the input DC voltage Vin.

When the switching transistor MT is turned off in the period t1, the voltage at the node N1 of the boost converter 100 is expressed by Equation 1 below.

In Equation 1, the current iL flowing to the coil L decreases by −ΔV0 due to −ΔV0, and distortion occurs in the desired input current Iin.

In order to compensate for this distortion, in the present invention, the first reference voltage source Vref and the output DC voltage V0 are added or subtracted by the synthesizer SM2 to obtain a voltage signal V4 that senses ΔV0 as shown in Equation 2 below. .

The voltage signal V4 thus obtained is multiplied by the gain K2 by the adjusting means CT and output as the compensation voltage signal K2 · V4.

The current sensing unit 220 detects a current flowing through the switching transistor MT and generates a voltage signal V1 when the switching transistor MT is turned on. The current sensing resistor RS and the resistor R1 are configured to generate a voltage signal V1. ) And a capacitor C1.

The first signal synthesizer 230 synthesizes the comparison reference voltage signal V2 of the output detector 210 and the voltage signal V1 of the current detector 220 by using a synthesizer SM3. It is configured to generate a signal V3.

The second signal synthesizing unit 260 synthesizes the compensating voltage signal K2 · V4 of the output sensing unit 210 and the inverse sawtooth signal B output from the oscillator 252 described later with a synthesizer SM4. Generates a compensated inverse sawtooth signal V5.

The comparator 240 compares the comparison reference signal V3 of the signal synthesizer 230 and the compensated inverse sawtooth signal V5 output from the second signal synthesizer 260 with an operational amplifier U2. Thus, the off control signal of the switching transistor MT is generated.

The driver 250 turns on the switching transistor MT in response to a clock signal CLOCK synchronized with the rising edge of the inverse sawtooth signal B, and responds to an off control signal of the comparator 240. The switching transistor MT is turned off to include an oscillator 252, a flip-flop 254, an inverted logic sum gate 256, and a driver 258.

The oscillator 252 generates the reverse sawtooth wave signal B and the clock signal CLOCK having the same frequency, and the flip-flop 254 rises the clock signal CLOCK output from the oscillator 252. The pulse width modulation signal is set at an edge and reset at the rising edge of the off control signal output by the comparator 240 to generate a pulse width modulation signal having a width between the rising edge of the clock signal CLOCK and the rising edge of the off control signal.

The inverted logic sum gate 256 supplies a pulse width modulated driving signal having a high potential section when both the clock signal CLOCK and the pulse width modulated signal output from the flip-flop 254 are in a low potential state. In response to the pulse width modulation driving signal output from the inverted logic sum gate 256, the driver 258 turns on the switching transistor MT in the high potential period and turns off the low potential period. Drive it up.

The operation and effects of the power factor correction circuit of the boost converter of the present invention configured as described above will be described with reference to the waveform diagrams of FIGS. 2 and 3.

When the input DC voltage (Vin) increases, the input current also increases in proportion to the input DC voltage (Vin), so that the voltage and current must be in phase.

As shown in FIG. 3, as the input DC voltage Vin increases, the current IL flowing to the coil L increases or decreases as shown in Equations 3 and 4 below.

Here, VL is the voltage of the coil (L).

That is, the comparison reference voltage signal V2 sensed by the output detector 210 and the voltage signal V1 corresponding to the current flowing when the switching transistor MT sensed by the current detector 220 are turned on The synthesized reference signal V3 is synthesized by the synthesizer 230.

When the comparison reference signal V3 becomes at the same level as the corrected inverse sawtooth signal V5, the output signal of the comparator 240 is inverted to high potential, so the flip-flop 254 is reset to switch transistor MT. Is turned off, and the output signal of the comparator 240 is inverted to a low potential again.

Therefore, as shown in FIG. 3, in the comparator 240, the comparison reference signal V3 and the compensated inverse sawtooth signal B are compared with each other to generate the pulse width modulated signal GATE of FIG. The driving of the switching transistor MT is controlled by the pulse width modulation signal GATE.

Here, the corrected reverse sawtooth signal V5 is V5 = B + K2 · V4, so that the increase in ΔiL generated by K2 · V4 compensates for the decrease in ΔiL in FIG. 2b.

As can be seen from the waveforms shown in FIGS. 2A and 2B, the waveform of the input control current is distorted by increasing the input current Iin as the output DC voltage V0 decreases in the period t1.

FIG. 2C is a waveform diagram showing an operation of compensating for distortion of a waveform of an input control current, and will be described separately when there is no compensation of? V0 and when there is compensation of? V0.

1) When ΔV0 ≠ 0 and there is no compensation for ΔV0

Since the variation of the output DC voltage (V0) is always present, ΔiL occurs, and thus the slope of the current changes, and the comparison reference signal V3 and the reverse sawtooth signal B are compared with each other in the comparator 240 so that the interval ( high potential state during t ').

2) When ΔVo ≠ 0 and there is a compensation of ΔV0 as in the present invention

The reverse sawtooth wave signal B generated by the oscillator 252 and the compensation voltage signal K2 · V4 generated by the compensation voltage generating means 218 are compensated for compensating? IL due to the variation of the output DC voltage V0. A signal synthesizer 260 synthesizes and generates a compensated reverse sawtooth signal (V5 = B + K2 · V4), and compares the compensated reverse sawtooth signal V5 to the comparator 240 with a comparison reference signal V3. The period t is high.

Therefore, the same waveform as in the case where there is no variation in the output DC voltage V0 is obtained.

The present invention can obtain a higher power factor by compensating for the current distortion caused by the variation of the output DC voltage V0.

In addition, according to the present invention, the current and voltage waveforms are in phase and become proportional in magnitude without a feed forward according to the input DC voltage Vin. This is because the current sensing unit 220 already has information on the input DC voltage Vin by the sensing resistor RS.

As described above, according to the present invention, it is possible to solve many disadvantages of the power factor correction circuits of the conventional CCM method, achieve a high power factor close to the unit power factor with a power factor of 0.99 or more, and much simpler than the existing methods. The circuit can be configured.

Claims (2)

A boost converter that accumulates energy in the coil in the on state of the switching transistor and superimposes an input DC voltage on the energy accumulated in the coil in the off state of the switching transistor, and a voltage signal according to the current flowing when the switching transistor is turned on. A power factor correction circuit for a boost converter, comprising: a current detector for generating a voltage; and controlling a driving of the switching transistor with a change in an output DC voltage output by the boost converter and a voltage signal generated by the current detector. An output detector for generating a comparison reference voltage signal whose level is changed in accordance with a change in the output DC voltage output from the type converter, and a compensation voltage signal for compensating for the variation in the output DC voltage; Comparative reference voltage signal and the current sensing unit A first signal combiner for combining generates a comparison signal to a voltage signal; A second signal synthesizing unit for synthesizing a compensation voltage signal generated by the output sensing unit and a reverse sawtooth wave signal to generate a reverse sawtooth wave signal having a variation in output DC voltage; A comparator for generating an off control signal of the switching transistor by comparing the comparison signal of the first signal synthesis unit with the compensated inverse sawtooth signal of the second signal synthesis unit; And a driving unit generating the reverse sawtooth signal and turning on the switching transistor according to a clock signal synchronized with the rising edge of the generated reverse sawtooth signal and turning off the switching transistor according to the off control signal of the comparator. Power factor correction circuit for boost converters that can compensate output voltage fluctuations. The apparatus of claim 1, wherein the output detection unit; Voltage dividing means for dividing the output DC voltage of the boost converter with a resistance; An error amplifier which inputs an output voltage of the voltage dividing means and detects an error voltage according to the change of the output DC voltage to a predetermined first reference voltage source; Level reference means for generating a comparison reference voltage signal by combining the error voltage output from the error amplifier with a predetermined second reference voltage source; And compensating voltage generating means for generating a voltage signal by combining the divided output voltage of the voltage dividing means and the first reference voltage source and adjusting a level gain of the generated voltage signal according to the magnitude of the ripple. A power factor correction circuit for a boost converter capable of compensating for output voltage fluctuations.