KR0168461B1 - Fabricating method of semiconductor device - Google Patents

Abstract

The manufacturing method of a semiconductor device applies the solution of specific polycarbosilane in the solvent on the board | substrate from which an electrically conductive component is manufactured, hardens the application layer of polycarbosilane to the temperature of at least 350 degreeC under an oxidizing atmosphere, and polycarbosilane layer Is converted into a silicon oxide layer. Since the obtained silicon oxide layer has a flat surface and no cracks, it is useful as a dielectric layer and a protective layer in the manufacture of highly reliable semiconductor devices.

Description

Manufacturing Method of Semiconductor Device

1 is a cross-sectional view of a prior art semiconductor device having an uneven dielectric layer.

2 is a cross-sectional view of a semiconductor device of the present invention having a planar dielectric layer.

3 is a cross-sectional view of a semiconductor device of the present invention having a multi-level or multilevel metallization structure.

4A through 4E are cross-sectional views sequentially illustrating the fabrication of a semiconductor device according to a preferred embodiment of the present invention.

5A to 5D are cross-sectional views sequentially illustrating the formation of a dielectric layer from fluorine-substituted polycarbosilanes according to a preferred embodiment of the present invention.

6A to 6C are cross-sectional views schematically illustrating the substitution of hydrogen atoms with fluorine atoms in the formation of the dielectric layer as shown in FIGS. 5A to 5D.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an electrically insulating layer, that is, a dielectric layer, between a metal or another conductive layer in a semiconductor device. The dielectric layer is hereinafter referred to as interlayer dielectric layer. In addition, the dielectric layer can act as a protective layer to protect the device from the environment when applied to the top surface of the device.

As can be seen from the following description of the present invention, the semiconductor device terminology used in the present invention includes a semiconductor integrated circuit (IC), a large integrated circuit (LSI), an ultra-large scale integrated circuit (VLSI), an ultra-large scale integrated circuit (ULSI), and the like. It means a variety of devices having a substrate made of a semiconductor material, as well as other electronic devices using the semiconductor material.

In recent years, integration of semiconductor devices has been remarkably developed to achieve rapid processing of vast amounts of information. LSI and VLSI circuits are in commercial operation, and ULSI circuits will soon be operational. The development of integrated circuits is achieved by miniaturization and increase of components manufactured within the chip, rather than depending on the expansion of the device, ie the scale or dimensions of the chip, thereby reducing the dimensions of the chip. As a result, the minimum size of the line and space of the wiring of the chip is about submicron, and the wiring structure adopted in the recent chip as needed is a multilayer or multilevel wiring or metallization structure.

In the fabrication of conventional integrated semiconductor devices, the micropatterns, electrodes, wirings and other components of the semiconductor region are manufactured in semiconductor substrate yarn using conventional process steps such as ion implantation, thin film deposition, and photolithography of impurities. . The patterned wiring layer thus obtained includes a number of topography features (unevenness) and stairs.

After the formation, an interlayer dielectric layer is formed on the patterned wiring layer, and then a hole is formed in a predetermined position of the dielectric layer. A next wiring layer is deposited over the dielectric layer to be patterned and the upper and lower wiring layers are electrically connected using the process steps described above. In this way, a desired integrated semiconductor device is provided.

A dielectric layer sandwiched between two patterned wiring layers must meet the following requirements.

1. Dielectric, ie, electrical insulation should be excellent.

2. Good heat resistance.

3. The surface must be smooth. That is, the planarization should be good.

4. Good crack resistance.

Although a number of dielectric materials have been proposed for interlayer dielectric layers, they are not considered to fully meet all of the above requirements. The dielectric layer forming material includes both inorganic and organic dielectric materials, which are applied on the wiring layer by, for example, a chemical vapor deposition (CVD) process, a sputtering process or a spin coating process.

Representative examples of useful inorganic dielectric materials include silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), and phosphosilicate glass (PSG). The dielectric layers formed from these inorganic materials show excellent dielectric and heat resistance, but when they are formed by thin film deposition techniques such as CVD or sputtering processes, the dielectric layers can be precisely reproduced because of the uneven and stepped profiles of the underlying wiring layers. In this uneven state, the wiring is disconnected.

On the other hand, representative examples of useful organic dielectric materials include polyimide resins and so-called organic spun-on-glass (SOG). Polyimide resins, especially recently developed photosensitive polyimide resins, are usefully used in that their workability is good because they can be subjected to photolithography without using a resist material as a patterning mask. However, due to the presence of a highly polarized imide ring of the molecular structure, the polyimide resin has high hygroscopicity or water absorption, thereby causing a problem that the dielectric constant of the obtained layer is lowered due to an increase in dielectric constant which increases with water absorption. Let's do it.

The SOG material is prepared from a silicon alkoxide of formula Si (OR) ₄ (R: alkyl group) and then hydrolyzed to obtain equilibrium conditions of the following reaction.

Si (OR) ₄ + 4H ₂ O = Si (OH) _n (OR) _4-n + nROH

The use of SOG material allows spin coating to provide a thin dielectric layer with a smooth surface, and the dielectric and heat resistance of the resulting dielectric layer are not as high as the dielectric and heat resistance of the inorganic dielectric material described above and are as high as practical. However, the SOG layer forms fine pores and cracks. That is, when heating the SOG layer coated on the substrate, the hydroxyl group (OH) constituting SI (OH) _n (OR) _4-n is condensed by dehydration reaction and is effective as a dielectric film having excellent heat resistance. To produce a cross-linkde product having a. However, due to the evaporation and decomposition of ROH during heating, it is easy to produce fine processing in SOG layers other than the evaporation of H ₂ O generated from condensation in the dehydration reaction, and also to a hardening treatment that acts to fill the pores. Are likely to occur.

Based on the above facts, further progress has been made in the formation of interlayer dielectric layers in semiconductor devices, in particular the use of organosilicon polymers as organic dielectric materials has been taught in patent publications and other publications. The organosilicon polymer can be applied by a spin coater, so that it is possible to manufacture a high yield semiconductor device with a thin dielectric layer having a smooth surface. However, conventional organosilicon polymers still have cracking problems. Furthermore, conventional organosilicon polymers used in particular can be spincoated flat on the surface of the layer, but the planarization effect is insufficient to achieve global planarigation in the dielectric layer obtained.

Global planarization will be described in more detail with reference to the accompanying drawings.

3 is a cross-sectional view of a semiconductor device having a multilayer or multilevel metallization (three level metallization) structure in which three metal layers 2, 12 and 22 are applied to one silicon substrate. Aluminum is used here as a metal.

As shown, the metal layers 2 and 12 are separated from each other through the interlayer dielectric layer 3 and the interconnects or electrodes of these layers are interconnected by aluminum filled in the pores formed between the layers 2 and 12. Similarly, interlayer dielectric layer 13 is sandwiched between two metal (A1) layers 12 and 22. A protective layer 23 having dielectric properties as dielectric layers 3 and 13 is disposed on the metal layer 22. In the semiconductor device shown, each of dielectric layers 3 and 13 must be globally planarized. That is, it has a global flat surface so that the next metal layer can be formed on the dielectric layer without any difficulty.

According to the conventional method described above, it is difficult to achieve global planarization of a multilevel metallization structure. In conjunction with FIG. 1, FIG. 1 is a cross sectional view of a conventional semiconductor device having a defective dielectric layer. The patterned metal layer 2 formed on the silicon substrate 1 has two kinds of patterned step portions, that is, a step portion 2a having a relatively wider electrode and the like and a relatively narrow step portion 2b such as wiring. After formation of the metal layer 2, the dielectric layer 3 is spin coated onto the metal layer 2 using the organosilicon polymer described above. As shown, the resulting dielectric layer 3 has an uneven surface due to the low coverage of the organosilicon polymer used as the dielectric material. In the region having the wide stepped portion 2a, the layer thickness of the dielectric layer is actually the same as in the spatial region having no electrode or wiring. Preferably, the resulting dielectric layer should have a flat surface throughout the region of the underlying metal layer, with or without stepped portions or patterns. In other words, it is desirable to implement an improved method of forming interlayer dielectric layers from organosilicon polymers that do not cause cracking problems and also ensure global planarization.

The inventors of the present application can be mixed with an organic solvent so that a specific polyorganosilsesquioxane (PMMS) is dissolved in an organic solvent and the viscosity thereof is controlled to a desired level, and a coating layer of polyorganosilsesquioxane It has been found that it is useful as an interlayer dielectric layer because it can meet the above-mentioned requirements for crack resistance, planarization, heat resistance, dielectric properties, and the like. Polyorganosilsesquinoxane can be prepared by hydrolysis of organotrichlorosilane or organotrialcoholsilane as starting material. The preparation and use of polyorganosilses quinoxanes as interlayer dielectric layers in semiconductor devices is described in US Pat. No. 4,670,299, which is described herein by reference. However, the newly developed polyorganosilsesquinoxane is advantageously used as an interlayer dielectric in the manufacture of semiconductor devices, but there is a problem in that satisfactory global planarization cannot be obtained.

Furthermore, when the above-described organic dielectric material such as polyimide and silicone resin is used in forming the interlayer dielectric layer, the dielectric layer is an organic group included in the layering material during coral (O ₂ ) plasma treatment in a multilevel metallization process. It is easy to release the gas due to the oxidation of. The gas generated in the dielectric layer generates defective areas in the device obtained, and also thermal decomposition of the dielectric material by exposure to high temperatures of about 400 ° C. causes the dielectric layer to break, causing cracking.

On the other hand, the use of organic dielectric materials such as silicon dioxide and silicon nitride requires the use of expensive devices such as CVD devices with vacuum systems. Moreover, the use of inorganic materials has the disadvantage that explosive and toxic materials must be used as the deposition source.

Combined use has been adopted in the formation of the dielectric layer as a laminated structure of organic dielectric materials such as polyimide and polyorganosiloxane resin and inorganic dielectric materials such as silicon dioxide, silicon nitride, and phosphorus silicate glass. Generally, a layer of organic dielectric material is used as the main portion of the dielectric layer and a layer of inorganic dielectric material is applied over the organic dielectric layer as a protective layer from oxygen plasma treatment. However, because each dielectric material used has an inevitable disadvantage, the resulting dielectric layer has not been satisfactory for use in semiconductor devices. In fact, it is difficult to avoid damage to the underlying organic layer due to the application of high temperature in the formation of the inorganic layer by the CVD process.

In order to prevent oxidative decomposition during oxygen plasma treatment, it is contemplated to use thin coatings of fluorocarbon resins such as Teflon ^™ . Since such a resin is not excellent in heat resistance and is about 350 DEG C, these resins have an additional problem of decomposing the resin coating during heat treatment in the method of manufacturing a semiconductor device.

For cracks caused in an interlayer dielectric layer, another way that a spin coatable silicone-based hard coat material can be used as the dielectric material and provide a dielectric layer with a low coefficient of thermal expansion similar to that of the silicon oxide layer upon curing However, the dielectric layer cannot avoid cracks caused by internal deformation and thermal shock of the layer even when the layer thickness of 5000 GPa or less is significantly reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that does not cause cracks and also secures global planarization of an interlayer dielectric layer when the dielectric layer is deposited on a patterned metal layer using an organosilicon polymer as the dielectric material. .

Another object of the present invention is that the dielectric material used can be spin coated to avoid the use of CVD and other expensive devices, while at the same time preventing cracking of the dielectric layer and undesired release of gas from the dielectric layer during plasma treatment. The present invention provides a method for manufacturing a semiconductor device.

It is still another object of the present invention to provide a method for manufacturing a semiconductor device in which the dielectric material used ensures excellent planarization of the dielectric layer without causing cracks and other defects in heat treatment such as curing.

A further object of the invention can be seen from the content as described below with respect to preferred embodiments of the invention.

According to the present invention, the above object is applied to a substrate of which the conductive component is prepared inside of the solution of polycarbosilane of the following general formula (1), and the polycarbosilane is applied at a temperature of at least 350 ° C. in an oxidizing atmosphere. It can be achieved by a method of manufacturing a semiconductor device consisting of the step of curing the layer to convert the polycarbosilane layer into a silicon oxide layer.

(Wherein R ₁ is a hydrogen atom, a substituted or unsubstituted alkyl group having 1 to 4 carbon atoms or a substituted or unsubstituted aryl group, R ₂ is a substituted or unsubstituted methylene or methine group, m and n are each 10m + n1000) Is a positive integer satisfying n and the ratio n / m is less than 0.3).

The present invention is directed to global flattening because conventional SOG materials are spin coated onto a topographic substrate to form a smooth surface layer, and then the coated layer is heated to cause curing thereof, thereby producing a melt product of the SOG material. It is based on the finding that it is not suitable to achieve. The residual product is very hard and its fluidity on the substrate is not sufficient to achieve global planarization. In contrast, the polycarbosilanes newly discovered by the inventors do not produce this solid product. Polycarbosilane first provides a low viscosity melt product and then provides a solid product upon curing and oxidation. The polycarbosilane does not contain any alkyl groups or silanols and can flow relatively easily after spin coating onto the substrate until its temperature is raised to a temperature sufficient to initiate condensation polymerization in the next heating step. Polycarbosilanes are distinguished from conventional polyorganosilsesquioxanes (PMSS) previously developed by the inventors in that they lower their viscosity. PMSS can be cured after reducing its viscosity from a predetermined level of temperature. However, the degree of viscosity reduction in polycarbosilane is more pronounced than that of PMSS. That is, polycarbosilanes may exhibit significantly reduced viscosity, i.e. significantly increased melt properties. Polycarbosilane can finally exhibit high viscosity after curing.

The production method according to the present invention is carried out by adding a solution of polycarbosilane of formula (1) described above as a dielectric layer forming material in a suitable solvent on a substrate on which a conductive component is produced.

In the formula (1) of the polycarbosilane used as a layer forming material, R ₁ is a substituted or unsubstituted alkyl group or a substituted or unsubstituted aryl group, a hydrogen atom, a group having 1 to 4 carbon atoms. Alkyl groups are methyl, ethyl, propyl or butyl groups which may be substituted or unsubstituted. Preferably, the alkyl group is an unsubstituted methyl group. Aryl groups are phenyl, tolyl or naphthyl groups which may be substituted or unsubstituted. Preferably, the aryl group is an unsubstituted phenyl group. Substituent R ₂ represents a substituted or unsubstituted methylene or methine group.

The polycarbosilane component used in the present invention can be prepared from commercially available starting materials from several domestic or foreign manufacturers. These can be prepared using conventional polymerization processes. For example, the starting material may be prepared by heating a mixture of polyborosiloxane and polysilane in an inert atmosphere to produce a corresponding polymer, or in the presence of a catalyst such as inert atmosphere and polyborodiphenylsiloxane, thereby lowering the molecular weight of carbosilane and polysilane. Can be prepared from polysilane as starting material by heating the mixture of.

The polycarbosilane of formula (1) above is applied onto a substrate from which a conductive component is made from a suitable solvent. Various organic solvents can be used in the present invention as long as it can dissolve the polycarbosilane and at the same time effectively control the viscosity of the polymer solution obtained as the coating solution. Suitable solvents include hydrocarbon solvents such as methyl isobutyl ketone (MIBK), xylene, toluene, hexane, cyclohexane, octane, decane and the like.

The application of the polycarbosilane onto the topographic substrate can be done using any conventional device such as a spin coater, dip coater, roller coater, and the like. Preferably, the spin coater is used because the polycarbosilane used in the present invention has a control viscosity suitable for the spin coater.

The topographic substrate including an electrical component prepared by applying a polycarbosilane solution includes various metals or conductive layers found in a conventional semiconductor device. Representative examples of such layers include circuit or wiring layers, electrode layers, and the like, and materials of these layers include, for example, A1, Ti, Tin, W, TiW, CVD-SiO ₂ , SiON, PSG, and the like.

The thickness of the polycarbosilane coating can vary depending on a number of factors, including the details of the polycarbosilane used, the shape of the base layer, the details including the baking temperature, and the like. In general, the thickness of the polycarbosilane is preferably in the range of about 0.1 to 3 mu m, more preferably in the range of 0.5 to 2 mu m.

After formation of the polycarbosilane coating, it is heated to a temperature of about 100 to 350 ° C. and melted to the lowest level of viscosity. In this heating step, excess solvent is evaporated from the coating.

The polycarbosilane coating is then cured at a temperature of at least 350 ° C. under an oxidizing atmosphere. As a result of the curing, the polycarbosilane is subjected to condensation polymerization, and the alkyl and / or aryl groups are cleaved into the main chain of the polycarbosilane as a branched chain, and at the same time, the main chain is decomposed into silane (SiH ₄ ) and methylene (CH ₂ ). do. Since curing is performed under an oxidizing atmosphere, decomposition products can contribute to the formation of a silicon oxide (SiO ₂ ) layer. The resulting silicon oxide layer significantly reduced the occurrence of internal strain of the layer and no crack was observed in the dielectric layer when the silicon oxide layer was bonded to the semiconductor device as an interlayer dielectric layer.

However, although curing can be carried out at any suitable temperature and time to complete the conversion from polycarbosilane to silicon oxide layer, the curing temperature will be below 350 ° C. because low temperatures are insufficient to initiate the condensation polymerization reaction of polycarbosilane. Should not be. The upper limit of the curing temperature is not set to a predetermined level, and may vary depending on the details of the polycarbosilane used in practice, the details of the layers constituting the apparatus and other factors, in particular the material of the base layer. Generally, curing is preferably performed at a temperature of 350 ° C. to about 500 ° C., in particular from about 400 ° C. to about 450 ° C. Similarly, the curing time may vary depending on the curing temperature and other conditions, and in general, the curing time is preferably in the range of about 30 minutes to about 60 minutes.

Curing can be done in conventional curing chambers such as electric ovens, hot plates, and the like.

Preferably, the curing may be carried out under an oxidizing atmosphere in the curing chamber. The oxidation atmosphere used here is preferably coral or coral-containing atmosphere, steam atmosphere, or the like. In the present invention, it can be used when other atmospheres are effective for curing the polycarbosilane.

The silicon oxide layer 3 obtained as the dielectric layer is shown in FIG. 2 for comparison with the defective dielectric layer in FIG. As shown in FIG. 2, the silicon oxide layer 3 has a flat surface which does not reproduce the stepped portions 2a (wide stepped portions) and 2b (narrowed stepped portions) of the base metal layer 2. The flat side of layer 3 means that global planarization can be achieved according to the invention.

Other steps of fabricating a semiconductor device in accordance with the present invention can be performed with procedures well known in the semiconductor art. For patents on semiconductor devices and their manufacture, reference should be made to patent publications and other publications.

In connection with the above description, the manufacture of a semiconductor device according to a preferred embodiment of the present invention will be further described with reference to FIGS. 4A to 4E, which show two levels of metallization schemes.

First, as shown in FIG. 4A, an aluminum layer 2 having a thickness of about 1.0 mu m is sputtered and deposited on the silicon substrate 1. Next, aluminum layer 2 is selectively etched to form first aluminum wiring layer 2. As shown in FIG. 4B, the wiring layer 2 stepped the pattern of aluminum. The solution of polycarbosilane in xylene was spin-coated on the stepped wiring layer at a speed of about 3000 rpm to form a layer having a thickness of about 2 μm, heated at 250 ° C. for 2 minutes to melt the resin, and then at 450 ° C. under a coral (O ₂ ) atmosphere. Allow to cure for 30 minutes at temperature. The resulting dielectric layer 3 having a flat surface is shown in FIG.

Following formation of the dielectric layer, a second patterned aluminum interconnect layer 12 is deposited over the dielectric layer. First, the dielectric layer is selectively etched according to a conventional photolithography process to form a through hole for connecting the previously formed first wiring layer and the second wiring layer deposited in the next step. As shown in FIG. 4D, the second wiring layer 12 is electrically connected to the first wiring layer 2 by the filled holes. Finally, as shown in FIG. 4E, the phosphorous silicate glass is deposited on the second wiring layer 12 by a CVD process to form a protective layer 5 having a thickness of about 3 mu m. Although not shown in the drawings, a contact hole or window for manufacturing the electrode is opened at a predetermined position of the obtained protective layer.

In a preferred embodiment of the present invention, a solution of the polycarbosilane of the general formula (1) wherein R ₁ is a hydrogen atom or a methyl group and R ₂ is a methylene or methine group is spin coated onto a topographic substrate, and at least 400 ° C. under an oxidizing atmosphere. Cure at a temperature of

Preferably, the coating solution controls the viscosity of the solution obtained by dissolving a selected polycarbosilane having a low molecular weight in an organic solvent such as MIBK. The coating of polycarbosilane is preferably cured at a temperature of 400-450 ° C. to initiate condensation polymerization of the polycarbosilane. As a result, the polycarbosilane is decomposed so that the alkyl group is cleaved from the side chain of the polycarbosilane and at the same time the main chain is separated into silane (SiH ₄ ) and methylene (CH ₂ ). Since curing is performed under an oxidizing atmosphere, growth of the silicon oxide layer on the metal layer is promoted. Moreover, since decomposition products of polycarbosilane can be easily evaporated, it is possible to prevent the occurrence of internal deformation and cracking in the obtained dielectric layer. In addition, planarization can be achieved in the dielectric layer. Moreover, these features mean that according to the present invention, the semiconductor device can be manufactured with high reliability.

In another preferred embodiment of the present invention, a polycarbosilane solution of the general formula (1) wherein R ₁ is a hydrogen atom or a methyl group and R ₂ is a methylene or methine group is spin coated on a topographic substrate to obtain a temperature of at least 350 ° C. After heating to produce the melt, the temperature of at least 400 ° C. is cured in an oxidizing atmosphere, preferably in a coral containing atmosphere.

The above-described method is advantageously applicable to the formation of relatively thick dielectric layers having a thickness of 0.5 mu m or more, which layer thickness is useful for flattening the stepped portions of the underlying metal layer.

Since the polycarbosilane used in the above-described method can oxidize not only methyl groups but also organic groups such as backbone and side chain portions at the same time, it does not show a decrease in density in the obtained dielectric layer. Therefore, the dielectric layer can be used in the manufacture of a semiconductor device without being damaged by heat or plasma of the applied processing method or the like.

As mentioned above, the spin coated layer is cured at a temperature above 350 ° C. for oxidation. More preferably, hardening is performed at the temperature of 400 degreeC or more, most preferably in the temperature range of 400-450 degreeC. At the same time, the application of the coral-containing atmosphere is effective because it enables an effective oxidation process. The heat resistance in the next heat treatment step is considered to be caused based on these curing conditions.

Moreover, the polycarbosilanes used can be melted at relatively low temperatures, which allows for good planarization. This means that the obtained dielectric layer is effective as an interlayer dielectric layer in a semiconductor device having a multilevel metallization structure.

As can be seen from the above description, the use of the specified polycarbosilane softens the stepped surface of the base metal layer, and maintains excellent dielectric properties compared to conventional dielectric layers using organic dielectric materials. It is possible to manufacture a reliable semiconductor device having a level metallization structure. In addition to the manufacture of semiconductor devices, polycarbosilanes are also useful for planarizing the surface of thin layer circuit boards and forming dielectric layers therein. In addition, the dielectric layer thus formed can be used as a protective layer for semiconductor devices and other devices.

In another preferred embodiment of the invention, after spin coating, the polycarbosilane of formula (1) is subjected to two different heat treatment steps, namely a first step of melting the coated layer and a second step for oxidation. Preferably, the solution of polycarbosilane of formula (1) is spin coated onto a topographic substrate and heated to a temperature of 300 ° C. and then cured at least 350 ° C. under an oxidizing atmosphere.

In view of this process, the polycarbosilane of the general formula (1) is an insoluble recovered from the solution of the polycarbosilane represented by the formula (1), but is different in a solvent selected from a halogenated hydrocarbon or an aprotic polar solvent. n / m ratio.

In another aspect of this process, the polycarbosilane of the general formula (1) is the fraction recovered from the polycarbosilane of the formula (1) by gel permeation and chromatography (GPC). This fraction has a weight average molecular weight of 2000 at most when calculated in terms of molecular weight of polystyrene. GPC is used to obtain certain polycarbosilanes with a suitable distribution of molecular weight, and the solvent used here is, for example, terahydrofuran (YHF).

Using the above-described method, it is possible to form a relatively thick dielectric layer useful for flattening the stepped portion of the base metal layer or having a thickness of 0.5 mu m.

The polycarbosilane used in the above-described method exhibits less deformation due to oxidation and cracking in the dielectric layer obtained because the methyl groups in its side chain decompose into protons and methylene as a result of the formation of carbosilane. Moreover, since it has a total oxidation temperature, polyorganosilane is very effective for use in its oxide.

The oxidation of the polycarbosilane is preferably performed by curing the polycarbosilane at a temperature of 350 ° C or higher. More preferably, hardening is performed at the temperature of 400 degreeC or more, Most preferably, 400-450 degreeC. At the same time, in order to achieve effective oxidation, it is considered to apply a coral-containing atmosphere in the curing treatment. As a result, a siloxane skeleton is formed in the polycarbosilane that may contribute to increasing the heat resistance in the next heat treatment step.

Moreover, the polycarbosilane used can be melted at a relatively low temperature, thereby enabling excellent planarization, providing a dielectric layer effective as an interlayer dielectric layer in semiconductor devices.

Moreover, the polycarbosilane used is capable of reducing the etching back to a minimum level due to the excellent global planarization achieved by using the polycarbosilane, and thus the manufacturing process of the semiconductor device using the etching back process. Is also valid.

As can be seen from the above description, the above-described polycarbosilane is used, softens the stepped surface of the base metal layer, and maintains excellent dielectric properties as compared to conventional dielectric layers using inorganic dielectric materials. It becomes possible to manufacture a reliable semiconductor device having a level metallization structure. In addition to the manufacture of semiconductor devices, the polycarbosilanes described above are also useful for planarizing the surface of thin-layer circuit boards and for forming dielectric layers therein.

In another preferred embodiment, the production process according to the invention comprises at least one hydrogen atom of R ₁ , R ₂ and R ₃ groups after coating of polycarbosilane and before curing of the coated layer. A further step of performing a plasma treatment of the coated layer using halogen as the reaction gas to substitute a halogen atom may be included.

That is, this embodiment of the present invention, after depositing or applying a layer of polycarbosilane, i.e., an organosilicon polymer having an alkyl group and / or an alkylene group, onto a metal layer, the hydrogen atoms contained in the molecules of the polymer are halogenated from the plasma. Substitution with atoms reduces the dielectric constant of halogen-substituted polycarbosilanes and is based on the finding that the physical properties such as planarization and crack resistance of unsubstituted polycarbosilanes are maintained. Reduced dielectric constant and good physical properties mean that the process of this embodiment is advantageously applied to the manufacture of high speed devices. It is also noted that halogen-substituted polycarbosilanes cannot be oxidized when the coral plasma is performed in the resist removal step or in the related step because the hydrogen atoms of the alkyl groups and / or alkylene groups of the polycarbosilanes have been previously substituted with halogen atoms.

In the practice of this embodiment, the steps until the polycarbosilane is applied onto the metal layer and the curing step can be performed according to the method described above for the preferred embodiment of the present invention. Similarly, the polycarbosilane used as the electrical material may be any one of the polycarbosilanes represented by the formula (1) above. The polycarbosilanes used herein are not limited further unless they contain any siloxane linkages.

The process including the halogen alicyclic step described above is performed by spin coating a solution of polycarbosilane of the general formula (1) excluding a siloxane group on a metal layer, and then performing plasma treatment using fluorine as a reaction gas to obtain polycarbosilane molecules. It can be preferably carried out by substituting one or more hydrogen atoms with one or more fluorine atoms and then curing the fluorine-substituted polycarbosilane in an oxidation atmosphere at a temperature of at least 350 ° C.

Halogen-substituted polycarbosilanes can be applied on a relatively thin layer of base metal layer because they have a chemical resistance effect caused during treatment with high active species in multilevel metal processes such as oxidation during O ₂ plasma ashing. Since the dielectric layer can be applied with a large thickness sufficient to protect the base layer, damage to the layer can be completely prevented in the multilevel wiring process.

Furthermore, according to this process, since the physical properties of the dielectric layer can be changed depending on the details of the polycarbosilane used, it is possible to freely control the physical properties of the final layer by appropriately selecting the polycarbosilane to be applied. As described above, since the polycarbosilane can be spin coated, there is no need to use an expensive processing apparatus such as a CVD apparatus. It is also noted that the micropattern of the apertures can be made using the dry method.

Further, the substitution of a hydrogen atom with a halogen atom in the polycarbosilane according to the preferred embodiment of the present invention will be described with reference to FIGS. 5A to 5D and FIGS. 6A to 6C.

The semiconductor substrate used here is the silicon substrate 1 which applied the patterned aluminum (A1) wiring layer 2 to the surface. In order to form the dielectric layer, a solution of the selected polycarbosilane represented by the formula (1) in MISK or the like in an organic solvent is added in the dropping direction on the wiring layer 2 from the dropping nozzle 7. In order to form the layer 3 of the polycarbosilane solution, spin coating is performed using an ordinary spin coater. The solvent contained in layer 3 is then evaporated by heating the substrate 1 to a temperature above the boiling temperature of the solvent used by the heater 8. As shown in Figure 5b, evaporated solvent 9 is released in layer 3.

After forming the dried polycarbosilane layer, the hydrogen atom of the polycarbosilane is replaced by a halogen atom in the radical reactor. In the example shown, fluorine is used as the halogen. As shown in FIG. 5C, the radical reactor includes a reaction chamber 14 having a high frequency power source 10 thereon. Substrate 1 is placed in stage 11 with a built-in heater and chamber 14 is evacuated with a vacuum of 5 × 10 ⁻⁶ Torr. After the exhaust is completed, fluorine gas is injected into the reaction chamber 14 through the gas pipe 15 at a flow rate of 200 sccm. The pressure in the chamber is increased to 0.3 Torr. By injection of the fluorine gas, the high frequency power source 10 is operated to generate the fluorine plasma 16 and then generate chemically active species (fluorine radicals). RF power applied from the power source is 300W. The resulting fluorine radicals 17 reach the surface of the polycarbosilane layer (not shown) deposited on the substrate 1. The radical 17 migrates from the surface portion of the polycarbosilane layer to the inner portion thereof, so that the desired substitution reaction takes place upon radical movement. Substitution reaction is carried out for 30 minutes at a substrate temperature of 200 ℃. After the substitution reaction is completed, the injection of fluorine gas is cut off or stopped, the chamber 14 is evacuated to 0.003 Torr, the heating of the substrate 1 is stopped, and the chamber 14 is cooled under dark pressure.

Finally, the fluorine-substituted polycarbosilane is cured for 30 minutes at a temperature of 450 ° C., for example under a coral (O ₂ ) atmosphere. The resulting dielectric layer 3 has a flat surface as shown in FIG. 5D.

The principle or mechanism of the above-described substitution reaction will be further described with reference to FIGS. 6A to 6C.

As shown in FIG. 6A, silicon substrate 1 has layer 3 of polycarbosilane of formula (1). Although not shown to simplify the layer structure, layer 3 is applied over the patterned wiring layer laminated on the substrate 1. Fluorine radicals 17 generated in the reaction chamber (not shown) are injected into the polycarbosilane layer 3 as shown in FIG. 6B. As shown in FIG. 6C, the substitution of a hydrogen atom with a fluorine atom in the polycarbosilane layer 3 takes place. The generated hydrogen gas 18 is developed in layer 3 to form fluorine substituted polycarbosilane.

The manufacturing method according to the present invention can be advantageously used for the formation of an interlayer dielectric layer. In such a case, it is contemplated to deposit a metal layer, on which a conductive component is made, on the formed dielectric layer, as is commonly practiced.

Similarly, the production method according to the invention can be advantageously used for the formation of the protective layer. In this case, the metal layer in which the conductive component is produced is the uppermost layer and the obtained silicon oxide layer can serve as a protective layer to the surrounding environment.

It can be seen that the dielectric layer manufactured by the manufacturing method of the present invention may be used in a semiconductor device for other purposes, unlike the interlayer dielectric layer and the protective layer.

The invention is further illustrated by the following examples. However, the present invention is not limited to these examples.

Example 1

An aluminum layer having a thickness of 1 탆 is deposited on the silicon substrate by a sputtering process. The obtained aluminum layer is etched in the pattern direction by a photolithography process to form a first wiring layer having a minimum line width of 1 μm and a minimum space width of 1 μm.

The polycarbosilane is dissolved in xylene to prepare a 50% solution of polycarbosilane to control the viscosity. The solution of polycarbosilane is spincoated to a thickness of 2 μm and heated to 150 ° C. for 2 minutes to evaporate the solvent from the layer. Thereafter, the polycarbosilane is cured at 450 ° C. for 30 minutes in an oxygen atmosphere to prepare an interlayer dielectric layer. The dielectric layer has a flat surface and indicates that global planarization has been achieved. The height of the remaining stepped portion observed on the layer surface is 0.1 탆 or less.

Thereafter, the through hole is opened at a predetermined position of the obtained dielectric layer, and a second wiring layer of aluminum is deposited in a manner similar to the formation of the first wiring layer described above. A protective layer of 1.3 μm thick phosphorus silicate glass is deposited on the second wiring layer by a CVD process. The protective layer is selectively etched to open the electrode manufacturing contact hole. The semiconductor device thus manufactured is heated at 450 ° C. for 1 hour in an air atmosphere, and then subjected to a thermal cycle test (great cycle test) in 10 repetitions in the range of -65 to + 150 ° C.

Example 2

An aluminum layer having a thickness of 1 탆 is deposited on the silicon substrate by a sputtering process. The obtained aluminum layer is etched in the pattern direction by a photolithography process to form a first wiring layer having a minimum line width of 1 m and a minimum space width of 1 m.

The polycarbosilane is dissolved in xylene to prepare a 30% solution of polycarbosilane to control the viscosity. The solution of polycarbosilane is spin coated to a thickness of 1 μm and heated at 250 ° C. for 2 minutes to evaporate the solvent in the layer. Thereafter, the polycarbosilane layer is cured for 30 minutes at 450 ° C. under a coral atmosphere to prepare an interlayer dielectric layer. The dielectric layer has a flat surface and indicates that global planarization has been achieved. The height of the remaining stepped portion observed on the layer surface is 0.1 탆 or less.

Thereafter, the apertures are opened on predetermined portions of the dielectric layer obtained with the resist process. No cracking due to oxidation of the resist process in the dielectric layer is observed. The dielectric layer is treated with 2.5% hydrofluoric acid to fill the aperture with aluminum. A second wiring layer of aluminum is deposited in a manner similar to the formation of the first wiring layer described above. A protective layer of 1.3 μm thick phosphorus silicate glass is deposited on the second wiring layer by a CVD process. In this way, a semiconductor device is manufactured. The semiconductor device is heated in an air atmosphere at 450 ° C. for 1 hour, and then a thermal cycle test is performed 10 times in a range of −65 to + 150 ° C. Disconnection of wiring is not observed.

Example 3

The procedure of Example 2 is repeated except that a P-CVD silicon oxide layer having a thickness of about 0.5 탆 is sandwiched between the first wiring layer and the polycarbosilane layer. The resulting dielectric layer has a flat surface and indicates that global planarization has been achieved. The height of the remaining stepped portion observed at the layer surface is 0.2 탆 or less. Moreover, no cracking due to oxidation of the resist process is observed in the dielectric layer. The semiconductor device is heated at 450 ° C. for 1 hour in an air atmosphere, and then subjected to a thermal cycle test in 10 iterations within the range of -65 to + 150 ° C. Disconnection of wiring is not observed.

Example 4

Polycarbosilane (Tilanocoat, commercially available from Ubd Industries, Co, Ltd) (carbosilane product of polydimethylsilane) is dissolved in diethyl ether and the solution is maintained to separate it into soluble and insoluble materials. The insoluble matter was recovered and the state of the coating obtained by spin-coating the MIBK solution on a silicon substrate with a thickness of about 1.5 mu m was evaluated. The coating is uniform and does not contain the microcrystals observed in the polycarbosilane (without the above treatment).

Example 5

The procedure of Example 4 is repeated except that chloroform is used instead of diethyl ether. A uniform coating is obtained as compared to that of Example 4.

Example 6

GPC using tetrahydrofuran (THF) was used in place of solvent extraction using diethyl ether, and gel permeation chromatography was performed on a liquid chromatography apparatus prepared with a solution of polycarbosilane to perform fractionation of molecular weight of polycarbosilane. The procedure of Example 4 is repeated except that. The recovered fraction has a weight average molecular weight of 2000 at most in terms of molecular weight of polyethylene. The fraction is dissolved in MBK and spin coated onto a silicon substrate. The coating is homogeneous and does not contain the microcrystals observed in the starting polycarbosilane.

Example 7

An aluminum layer having a thickness of 1 탆 is deposited on the silicon substrate by a sputtering process. The obtained aluminum layer is etched in the pattern direction by a photolithography process to form a first wiring layer having a minimum line width of 1 m and a maximum space width of 1 m.

The polycarbosilane prepared in each of Examples 4 to 6 was dissolved in a MIBK solvent to prepare a 40% solution of polycarbosilane to control the viscosity. The solution of polycarbosilane is spin coated to a thickness of 2 μm and heated at 150 ° C. for 5 minutes to evaporate the solvent in the layer. Thereafter, the polycarbosilane layer is cured at 450 DEG C for 30 minutes in a coral atmosphere to prepare an interlayer dielectric layer. The dielectric layer has a flat surface and indicates that global planarization has been achieved. The height of the remaining stepped portion observed on the layer surface is 0.1 탆 or less.

Thereafter, a hole is opened at a predetermined position of the obtained dielectric layer and a second wiring layer of aluminum is deposited in a manner similar to the formation of the first wiring layer described above. A protective layer of 1.3 μm thick phosphorus silicate glass is deposited on the second wiring layer by a CVD process. The protective layer is selectively etched to open the electrode manufacturing contact hole. The semiconductor device is heated at 450 ° C. for 1 hour in an air atmosphere, and then subjected to a thermal cycle test in 10 iterations within the range of -65 to + 150 ° C. Disconnection of wiring is not observed.

Example 8

This example is a comparative example.

The procedure of Example 4 is repeated except that methanol is used instead of diethyl ether. Separation of polycarbosilane is not achieved because an undesirable reaction between polycarbosilane and silicon hydride (SiH) occurs.

Example 9

A 1 μm thick aluminum layer is deposited on the silicon substrate by a sputtering process. The obtained aluminum layer is etched in the pattern direction by a photolithography process to form a first wiring layer having a minimum line width of 1 m and a minimum space width of 1 m.

The polycarbosilane is dissolved in xylene to prepare a 30% solution of polycarbosilane to control the viscosity. The solution of polycarbosilane was spin-coated at 3000 rpm for 30 seconds to form a layer having a thickness of 1 μm, and heated at 250 ° C. for 10 minutes under an inert gas atmosphere to remove the solvent from the layer.

Thereafter, the polycarbosilane layer is subjected to a fluorination process according to the manner described in Kokai No. 5-262819 (incorporating the description in the present invention for reference). The conditions of this fluorination process are described above with reference to FIG. 5C.

Fluorinated polycarbosilane was cured at 450 ° C. for 30 minutes in a coral atmosphere to prepare an interlayer dielectric layer. The dielectric layer has a flat surface and indicates that global planarization has been achieved. The height of the remaining stepped portion observed on the layer surface is 0.3 탆 or less. The dielectric constant is measured at 2.5. Thereafter, the through hole is opened at a predetermined position of the dielectric layer obtained by the usual resist process. No cracks due to oxidation of the resist process such as removal by plasma ashing are observed in the dielectric layer. After forming the pores, the dielectric layer is treated with 2.5% hydrofluoric acid to fill the pores with aluminum. That is, the second wiring layer of aluminum is deposited in a manner similar to the formation of the first wiring layer described above. A protective layer of 1.3 μm thick phosphorus silicate glass is deposited on the second wiring layer by a CVD process. The protective layer is selectively etched to open the electrode manufacturing contact hole. In this way, a semiconductor device is manufactured. The semiconductor device is heated under an air atmosphere at 450 ° C. for 1 hour, and then subjected to a thermal cycle test in 10 iterations within the range of -65 to + 150 ° C. Disconnection of wiring is not observed.

Example 10

The procedure of Example 9 is repeated except that polycarbosilane styrene is used instead of polycarbosilane. The result is compared with the result of Example 9. For example, the dielectric layer has a flat surface and indicates that global planarization has been achieved. The height of the remaining stepped portions observed at the layer surface is 0.3 탆 or less. The dielectric constant is measured at 2.8. Cracks due to oxidation of the resist process are not observed in the dielectric layer after the formation of the pores.

Example 11

This example is a comparative example.

Conventional organic SOG including siloxane bonds and methyl side chains; The procedure of Example 9 is repeated except that polymethylsilsesquinoxane is used instead of polycarbosilane. In the fluorination process, a semiconductor device cannot be manufactured because the SOG layer is completely etched from the first wiring layer based on the fluorine plasma.

Example 12

This example is a comparative example.

The procedure of Example 9 is repeated except that a commercial polyethylene resin is used instead of polycarbosilane. Since cracking occurs in the dielectric layer due to decomposition of the organic group, a defective semiconductor device is manufactured. It is noted that the polyethylene resins used do not meet the requirements for high heat resistance.

Claims (10)

The solution of polycarbosilane of the general formula (1) (Wherein R ₁ is a hydrogen atom, a substituted or unsubstituted alkyl group having 1 to 4 carbon atoms, or a substituted or unsubstituted aryl group, R ₂ is a substituted or unsubstituted methylene or methine group, m and n are each 10 m + n1000 A positive water purifier satisfying the conditions and n / m is less than 0.3) is coated on the substrate on which the conductive component is made, and the polycarbosilane coating layer is cured at an temperature of 350 ° C. or higher under an oxidizing atmosphere, thereby reducing the polycarbosilane to silicon. A method for manufacturing a semiconductor device, comprising the step of changing to an oxide layer. The method according to claim 1, wherein the alkyl group is a methyl group. The production method according to claim 1, wherein the aryl group is a phenyl group. The method of claim 1, wherein the solution of polycarbosilane is spin coated onto the topographic substrate. The solution of polycarbosilane of the general formula (1) (R ₁ is a hydrogen atom or a methyl group and R ₂ is a methylene or methine group) is spin coated onto a topographic substrate and heated to a temperature of 350 ° C. or less. Then, the production method is cured at a temperature of 400 ℃ or more under an oxidizing atmosphere. The solution of polycarbosilane according to claim 5, wherein the polycarbosilane represented by the general formula (1) is represented by the general formula (1), provided that the ratio of n / m in a solvent selected from an aprotic polar solvent or a halogenated hydrocarbon is different. A process for producing an insoluble matter recovered from. The polycarbosilane of the general formula (1) is a fraction recovered from the polycarbosilane of the formula (1) by gel permeation chromatography, and the fraction is 2000 or less in terms of the molecular weight of polystyrene. Manufacturing method having an average molecular weight. 2. The plasma treatment of claim ₁ , wherein a solution of polycarbosilane of the general formula (1) (R ₁ , R ₂ , m and n are as defined above) is spin-corned onto the topographic substrate to use fluorine as the reactor. And replacing at least one hydrogen atom of the polycarbosilane with at least one fluorine atom, and then curing the fluorine-substituted polycarbosilane at a temperature of 350 ° C. or higher under an oxidizing atmosphere. The manufacturing method according to any one of claims 1 to 8, further comprising the step of forming another element on which the conductive component is manufactured, on the obtained silicon oxide layer. The manufacturing method according to any one of claims 1 to 8, wherein the layer in which the conductive component is made is an uppermost layer and the obtained silicon oxide layer acts as a protective layer to the surrounding environment.