KR0166650B1 - Microcomputer having multiplexible input/output port - Google Patents

Abstract

Microcomputers or one-chip computers have separate address pins and data pins, and when a specific control signal is supplied, the address pin acts as a multiplex pin for address and data signals.

Further, the combination of bits for the address signal and bits for the data signal to be supplied to the multiplex pin is changed in accordance with the bit width of the external bus.

For example, as previously used, data bit D _i is combined with address bit A _i .

Further, data bits D _-1 are combined with address bits A _i by shifting one bit relative to the address bits.

One of these two combinations can be selected.

If the microcomputer has a 16-bit address pin, it can be connected to an 8-bit memory with independent address and data pins, while it has 8 multiplex pins without using external circuitry to separate the address and data signals. It can also be connected to parts around the beat.

Description

Microprocessor with I / O Port for Multiplex

1 is a schematic diagram of a microcomputer.

2 is a schematic diagram of a microcomputer system having peripheral components.

3 is a circuit diagram showing a part of an input / output port for the multiplex pin shown in FIG.

4A to 4D are circuit diagrams of the control signal generator shown in FIG.

5 is a circuit diagram showing a part of an input / output port for a data signal.

6A and 6B are timing charts of an address signal and a data signal for a bit width of 8 bits.

7A and 7B are timing charts of an address signal and a data signal for a bit width of 16 bits.

8 is a connection diagram of a microcomputer having an external memory component.

9 is a timing chart of an address signal and a data signal illustrating the modified case.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one chip microcomputer of a microcomputer, and more particularly, to an input / output port thereof.

The microcomputer may be connected to an external memory such as read only memory (ROM) or random access memory (RAM).

One-chip computers have a memory expansion mode, and external memory is used such as static RAM (SRAM) and electrically erasable ROM (EEROM).

The one chip computer has an input / output port including pins for address signals and data signals to be connected to an external address bus and an external data bus so that address signals and data signals are transmitted through the external bus.

The memory has separate pins for address signals and pins for data signals.

Thus, the pins for the address signal and the pins for the data signal of the microprocessor or microcomputer are respectively connected to the corresponding portions of the memory via the external address bus and the external data bus.

Thus, the number of pins allocated for the address and data signals of the one chip microcomputer is large, which limits the number of input / output ports that can be included in the one chip microcomputer.

It is desirable that one-chip computers have as many input and output ports as possible.

Therefore, in order to reduce the number of address and data pins, multiplex pins for transferring address and data in time division are provided, and they are connected to the multiplex bus.

Thus, the number of pins required for the address and data signals can be reduced, while the number of input and output ports can be increased.

On the other hand, the memory has a pin for the address signal and a pin for the data signal separately.

Therefore, in order to separate the address and data signals, external circuitry needs to be connected between the multiplex bus and the memory, which increases the cost of the system.

This is a drawback of such a multiplex bus.

Peripherals, such as gate arrays or Application Specific Standard Products (ASSPs), sometimes employ multiplexed pins for address and data signals to increase the number of input and output ports.

In such cases, external circuitry is required to connect the address and data buses from the microcomputer to the multiplex bus, which increases the cost of the computer system.

It is an object of the present invention to provide a microcomputer or one-chip microcomputer that can be connected to an external device without using an external circuit that separates the address and data signals, with or without multiplex pins for the address signal and the data signal. It is.

The microcomputer according to the present invention includes a CPU (Central Processing Unit), an internal bus connected to the CPU and an input / output port connected to the CPU through the internal bus. Include.

The input / output port is provided with a first input / output circuit connected to a first external bus and connected to a second external bus, and a second input / output circuit for a data signal.

The first input / output circuit may operate as a multiplex input / output circuit when a specific control signal is received from a controller for supplying a control signal.

The controller may include a control signal, for example, a signal indicating whether it is multiplexed or non-multiplexed, and a timing signal used for the multiplex. A control signal is generated in accordance with the signal and the signal representing the bit width of the first external bus.

For example, an address signal or data signal A _i / D _i-1 (where i = 1 to 8, A _i denotes an i-th bit address signal, and D _i-1 denotes a data signal of i-1 th bit). ) Is output in time division when the bit width of the first external bus is equal to the number of bits of data processed by the circuit unit.

The advantage of the present invention is that since the microcomputer has pins for multiplexing, it can be connected to various kinds of peripheral devices with various external bus widths, for example, without using external circuitry for separating address and data signals. Is that there is.

These and other objects of the present invention will become apparent from the following description taken through the preferred embodiments thereof in conjunction with the accompanying drawings.

Referring to the drawings, like reference numerals designate like or corresponding parts in various aspects.

First, the microcomputer 10 of the embodiment of the present invention is described.

1 shows the internal structure of the microcomputer 10, where the CPU 1, the ROM 2, the RAM 3, and the input / output port 4 are connected to the internal bus.

In FIG. 1, an internal address bus 5 and an internal data bus 6 for address and data signals are shown.

Control signals are also supplied via the internal bus, but here the bus is not shown for clarity.

I / O port 4 Pin (11), And a pin 12, a first pin 13, a second pin 14, and a BYTE pin 15.

Pins 11 and 12 are read control signals And write control signal To supply.

The first pin (indicated by A (A / D) in the figure) is a multiplex pin, which acts as a time division multiplex pin (A / D) for address and data signals under certain conditions, or otherwise It can operate as pin A. FIG.

On the other hand, the second pin 14 acts as a data pin.

The feature of the microcomputer is that the multiplex pin 13 is provided as an address and a data pin.

Signal BYTE (byte) is supplied to set the number of bits of the bus to be connected to pin 13.

In this example, the signal BYTE is supplied from the BYTE pin 15.

However, it is also possible to set the BYTE signal by the CPU 1.

When the 8-bit bus is connected to pin 13, the signal BYTE is set at the 'H' level, whereas when the 16-bit bus is connected to the pin 13, the signal BYTE is set at the 'L' level.

2 is a computer system having a microcomputer 10, an external memory 20, and an ASSP 30.

As described above, the microcomputer 10 has sixteen first pins or multiplex pins 13 and sixteen second pins 14.

Memory 20 has eight address pins 21 for address signals and eight data pins 22 for data signals, while ASSP 30 has eight multiplex pins for address and data signals. Has 31.

The first bus 41 connects the first pin 13 of the microcomputer 10 to the address pin of the memory 20, while the second bus 42 connects the second pin 14 to the data pin ( 22).

Furthermore, the first bus 41 is connected to the multiplex pin 31 of the ASSP 30 via the third bus 43.

Read and write control signals Wow Is the output enable pin ( ) And write enable pin ( If the memory 20 or ASSP is a read-only device, Need not be supplied).

The microcomputer 1 has a mode in which only an address signal is output to the bus 41, and a multiplex mode in which address signals and data signals are alternately transmitted via the bus 41, as described later.

In Figure 2 the signal BYTE is set to ground level, which means that the bit width of bus 41 is 16.

Therefore, the microcomputer can be connected to a memory having address pins and data pins installed separately, but also to a peripheral device having many pins without using an external circuit for separating the address and data signals. .

Another characteristic of the microcomputer 10 is that, when the first pin 13 operates as a multiplex pin, the order of the address signals appearing on the first pin 13 is determined according to the bit width of the bus 41. It may be set to have a specified relationship with the counterpart.

The microcomputer 10 may be connected to a memory or other peripheral device that stores 8-bit data, or to a device that stores 16-bit data.

In this embodiment, for example, if the number of pins 13 is eight and the number of pins 31 is eight, then the same bits are arranged to correspond to each other.

That is, the address bits A0, A1, A2, ..., A7 are arranged to correspond to the data bits D0, D1, D2, ..., D7.

For example, address bits A0 are assigned to pins 13 for multiplex, such as data bits D0.

This type of address bit-to-data bit correspondence in the correspondence of address signals to data signals at multiplex pins has already been adopted in the prior art.

On the other hand, if the number of pins 31 is eight while the number of pins 13 is 16, the bit positions of the address signal and the data signal can be changed.

For example, the address bits A1, A2, A3, ..., A8 are arranged to correspond to the data bits D0, D1, D2, ..., D7, or the bit positions are shifted one by one.

In this case, data bits D0 and address bits A1 are assigned to the same multiplex pin 13.

By using this new type of bit array, memory for 8-bit data can be used as 16-bit data.

The example of the microcomputer system shown in FIG. 8 to be described next takes advantage of this embodiment.

In this embodiment, although the bit positions are shifted by one digit, any correspondence between the data signal and the address signal can be employed.

3 shows a part of the input / output circuit 100 of the input / output port 4 including the circuit unit 130 composed of the first (or multiplexed) pin 13 controller 108 and a logic circuit, the circuit portion of which is shown in FIG. 130 includes elements 101 to 107 and 109 to 111, where the bit arrangement may vary depending on the bit width of the bus 41. As described above, pin 13 may operate as a multiplex pin for address and data signals A / D under certain conditions.

FIG. 3 shows only a part of one pin related to the address bits A1 and the data bits D0 and D1 among the pins 13 for ease of illustration, and the input / output circuit 100 includes the control signal generator 108. In addition to the above, each of the sixteen pins 13 includes such a portion. In the input / output circuit 100, the circuit unit 130 shown in FIG. 3 is connected to the internal address line A1 on the internal address bus 5 and the internal data lines D0 and D1 on the internal data bus 6. On the other hand, it is also connected to the external bus 41 via a pin 112 which is also part of the multiplex pin 13.

The control signal generator 108 shown in Figs. 4A to 4D is a control signal generated by the microcomputer 10 (internal timing signal E, chip select signal CS, read / write signal). ) And control signals 'a' to 'f' for the input / output circuit 100 according to the externally supplied signal BYTE.

Signal CS is used to select whether non-multiplexed or multiplexed.

The signal BYTE is used to set the number of bits of the bus 41 to be connected to eight or sixteen.

The timing signal E is used to multiplex the address and data signals to be alternately output.

Read / write signal Means read cycle at H level and write cycle at L level.

When the control signal 'b' is received, the first transmission gate 109 transmits a signal from the internal address bus line A1, while the second and third transmission gates 110 and 111 respectively control signal ' When c 'and' d 'are received, it transmits signals from the internal data bus lines D0 and D1.

Only one of the control signals 'b', 'c' and 'd' is supplied at any time, and only one output signal from one of the transmission gates 109 to 111 is NAND gate 102 and NOR gate 103. The control signal 'a' is supplied to the other input of the NAND gate 102 and to the other input of the NOR gate 103 via the inverter 101.

The outputs of the NAND gate 102 and the NOR gate 103 are connected to the gates of the P channel MOS transistor 104 and the N-channel MOS transistor 105, respectively.

Transistors 104 and 105 are connected in series with each other and their connection point is connected to pin 112.

Transistors 104 and 105 are also connected between Vcc and ground.

Thus, the transistors 104 and 105 transmit a signal from the internal lines A1, D0 and D1 to the pin 112 when the control signal 'a' is supplied.

On the other hand, the pin 112 is connected to the tri-state buffers 106 and 107 so that when the control signals 'e' and 'f' are received, the signals are sent from the pin 112 to the internal data bus lines D0 and D1. To send.

A part of the controller 108 that generates the fourth to fourth or bus control signals 'a' to 'f' is shown.

As shown in FIG. 4A, the inversion signal of the internal timing signal E, the chip select signal CS and the read / write signal. Is input to the NAND gate 200 to generate a control signal 'a'.

As shown in FIG. 4B, the inversion signal of the internal timing signal E and the chip select signal CS are input to the NAND gate 201 to generate the control signal 'b'.

As shown in FIG. 4C, the inversion signal of the internal timing signal E, the chip select signal CS and the signal BYTE are input to the AND gate 202 to generate the control signal 'c'.

Control signal 'c' and read / write signal Is input to the NAND gate 203 to generate the control signal 'e'.

As shown in FIG. 4D, the inverted signals of the internal timing signal E, the chip select signal CS and the signal BYTE are input to the NAND gate 204 to generate the control signal 'd'.

The signal 'd' and a read / write signal Is input to the NAND gate 205 to generate a control signal 'f'.

Table 1 shows bus control signals 'a' to 'f' according to various conditions set by the microcomputer 10.

5 is an example of an input / output circuit for supplying each data bit to the input / output port 4 at the pin 14 for the address signal.

This is a read / write signal It is a conventional input / output circuit including a bidirectional buffer for the 16 address bits D0 to D15 controlled by the controller.

Next, when an 8-bit bus or 16-bit bus is connected to pin 13, input / output port 4 has memory 20 without multiplex pins and multiplex address / data pins (A / D). How to operate for the ASSP 30 will be described.

There are four cases.

In the first case, the signal BYTE is set to the 'H' level or the pin 13 is connected to an 8-bit bus, the chip select signal CS is set to the 'L' level or the memory 20 is accessed.

The timing chart for this case is shown in FIG. 6A.

In this case, the address bits A0 to A7 correspond to the data bits D0 to D7, as shown in the left side of Fig. 6A.

The input / output circuit 4 outputs the 1-bit address signal A1 from the internal address bus 5 to the pin 112.

That is, the control signal generator 108 supplies the control signals 'a' at the 'H' level and 'c' to 'f' at the 'L' level.

Since signal 'b' is set to the 'H' level and 'c' and 'd' are set to the 'L' level, the transfer gate 109 is open, while the other transfer gates 110 and 111 are It is closed.

Since the control signal 'a' is set at the 'H' level, the output circuit composed of the parts 101 to 105 is turned on so that the signal A1 is output to the pin 112.

Furthermore, since the control signals 'e' and 'f' are set to the 'L' level, the buffers 106 and 107 are not activated or the pins 112 are not connected to the internal bus lines D1 and D2. .

In general, the address data A0 to A7 are output to the memory 20 via the bus 41.

In the second case, signal BYTE is set to 'H' level or pin 13 is connected to an 8-bit data bus and chip select signal CS is set to 'H' level or accessed by ASSP 30 with multiplex pins. do.

Fig. 6b shows the timing chart for this case.

In this case, the address bits A0 to A7 correspond to the data bits D0 to D7, respectively, as shown on the left side of FIG. Display the signal appearing at each of the

The input / output circuit 4 operates differently as shown in FIG. 6B depending on whether the timing signal E is set to the 'H' level or the 'L' level for the multiplex function.

When the timing signal is set at the 'H' level, the address signal A1 is sent to pin 112.

That is, the control signal generator 108 supplies the control signals 'a' at the 'H' level, 'b' and 'c' to 'f' at the 'L' level in the same manner as described above.

Since signal 'b' is set to the 'H' level and 'c' and 'd' are set to the 'L' level, the transfer gate 109 is open, while the other transfer gates 110 and 111 are It is closed.

Since the control signal 'a' is set at the 'H' level, the output circuit composed of the parts 101 to 105 is turned on so that the signal A1 is output to the pin 112.

Furthermore, since the control signals 'e' and 'f' are set to the 'L' level, the buffers 106 and 107 are not activated or the pins 112 are not connected to the internal bus lines D1 and D2. .

In general, address data A0 to A7 are output to the ASSP 30 via the bus 41.

On the other hand, when the timing signal E is set to the 'L' level, the internal read / write signal There are two cases where is set to the 'H' level or the 'L' level.

When the internal read signal R is set to the 'H' level or the CPU 1 reads data from the ASSP 30, the data signal shown on the pin 112 is sent to the first line D1 of the internal data bus. .

That is, the control signal generator 108 supplies the control signals 'c' of the 'H' level and the control signals 'a' 'b' 'd' 'e' of the 'f' and 'L' levels.

Since the signal 'c' is set to the 'H' level and the 'b' and 'd' are set to the 'L' level, the transfer gate 110 is open, while the other transfer gates 109 and 111 are It is closed.

Since the control signal 'a' is set at the 'L' level, the output circuit composed of the parts 101 to 105 is turned off.

On the other hand, since the signal 'e' is set to the 'H' level and the signal 'f' is set to the 'L' level, the buffer 106 is turned on while the other buffer 107 is not activated.

Therefore, the pin 112 is not connected to the internal bus line D1.

In general, data bits D0-D7 are received from the ASSP 30.

Furthermore, the internal write signal Is set to the 'L' level or the CPU 1 writes data to the ASSP 30, the data signal shown on the first bus line (D1) is sent to the pin (112).

That is, the control signal generator 108 supplies the control signals 'a' at the 'H' level, 'b', 'd' to 'f' at the 'L' level.

Since the signal 'c' is set to the 'H' level and the 'b' and 'd' are set to the 'L' level, the transfer gate 110 is open, while the other transfer gates 109 and 111 are It is closed.

Since the control signal 'a' is set at the 'H' level, the output circuit composed of the parts 101 to 105 is turned on to supply data from the bus line D1 to the pin 112.

On the other hand, since the control signals 'e' and 'f' are set to the 'L' level, the buffers 106 and 107 are not activated.

In general, data bits D0 to D7 are sent to the ASSP 30.

Next, as another case, the case where the signal BYTE is set to the 'L' level or the pin 13 is connected to the 16-bit bus.

In the third case, the chip select signal CS is set to the 'L' level or the memory 20 is accessed. Fig. 7A shows a timing chart for this case.

The input / output circuit 4 outputs the 1-bit address signal A1 from the internal address bus 5 to the pin 112.

That is, the control signal generator 108 supplies the control signals 'a' at the 'H' level and the control signals 'c' to 'f' at the 'L' level.

Since signal 'b' is set to the 'H' level and 'c' and 'd' are set to the 'L' level, the transfer gate 109 is open, while the other transfer gates 110 and 111 are It is closed.

Since the control signal 'a' is set at the 'H' level, the output circuit composed of the parts 101 to 105 is turned on so that the signal A1 is output to the pin 112.

Furthermore, since the control signals 'e' and 'f' are set to the 'L' level, the buffers 106 and 107 are not activated or the pins 112 are not connected to the internal bus lines D1 and D2. do.

In general, the address bits A0 to A16 are sent to the memory 20.

In the fourth case, signal BYTE is set to 'L' level or pin 13 is connected to a 16-bit bus and chip select signal CS is set to 'H' level or ASSP 30 with multiplex pins is accessed. .

7B shows a timing chart for this case.

In this case, the address bits A1 to A8 correspond to the data bits D0 to D7, as shown in the left side of Fig. 7B.

The input / output circuit 4 operates differently to perform multiplexing depending on whether the timing signal E is set to the 'H' level or the 'L' level.

When the timing signal E is set at the 'H' level, the address signal A1 is sent to the pin 112.

That is, the control signal generator 108 supplies the control signals 'a' at the 'H' level and the control signals 'c' to 'f' at the 'L' level.

Since signal 'b' is set to the 'H' level and 'c' and 'd' are set to the 'L' level, the transfer gate 109 is open, while the other transfer gates 110 and 111 are It is closed.

Since the control signal 'a' is set at the 'H' level, the output circuit composed of the parts 101 to 105 is turned on and output to the pin 112 which is the signal A1.

Furthermore, since the control signals 'e' and 'f' are set to the 'L' level, the buffers 106 and 107 are not activated or the pins 112 are not connected to the internal bus lines D1 and D2. do.

In general, the address bits A0 to A16 are sent to the ASSP 3.

In contrast, the internal read / write signal when the timing signal E is set to the 'L' level. There are two cases where is set to the 'H' or 'L' level.

When the internal read signal R is at the 'H' level or the CPU 55 reads data from the ASSP 12, the data signal appearing on the pin 112 is sent to the 0th line D0 of the internal data bus.

That is, the control signal generator 108 supplies the control signals 'd' and 'f' of the 'H' level and the control signals 'a' through 'c' and 'e' of the 'L' level.

Since the signal 'd' is set to the 'H' level and the 'b' and 'c' are set to the 'L' level, the transfer gate 111 is open, while the other transfer gates 109 and 110 are It is closed.

Since the signal 'a' is set at the 'L' level, the output circuit composed of the parts 101 to 105 is turned off.

On the other hand, since the control signal 'f' is set at the 'H' level and 'e' is set at the 'L' level, the buffer 107 is turned on while the other buffer 106 is not activated.

Therefore, the pin 112 is not connected to the internal bus line D0.

Generally, the data bits D0 to D7 are read, but the bit correspondence is different from what can be understood by comparing the sixth and seventh degrees.

Internal write signal Is at the 'L' level or when the CPU 55 writes data to the ASSP 12, the data signal appearing on the 0th bus line D0 is sent to pin 112.

That is, the control signal generator 108 supplies the control signals 'a' and 'd' of the 'H' level and the control signals 'b', 'c' 'd' and 'f' of the 'L' level.

Since the signal 'd' is set to the 'H' level and the 'b' and 'c' are set to the 'L' level, the transfer gate 111 is open, while the other transfer gates 109 and 110 are It is closed.

Since the signal 'a' is set at the 'L' level, the output circuit composed of the parts 101 to 105 is turned on to supply data from the bus line D0 to the pin 112.

On the other hand, since the signals 'e' and 'f' are set at the 'L' level, the buffers 106 and 107 are not activated.

As such, in general, data bits D0 to D7 are recorded.

In the fourth case, when the data signal is output to the bus, the data signal behaves differently as shown in FIG. 7B with respect to the 16-bit bus. You must convert it so that it can be received normally.

Table 1 shows the conversion by the microcomputer 10 for reading data signals '0' to '5' from or writing to the ASSP 30.

For example, 10 is output as data 1 by the CPU 1.

That is, the data signal is shifted by one bit, while the zeroth bit is used as A0 or 0 in Table 2.

This data conversion can be easily handled by the CPU 1.

Table 2. Data for bit arrays for combinations of address and data bits

CPU ASSP

0 000000000 00000000

1 000000010 00000001

2 000000100 00000010

3 000000110 00000011

4 000001000 00000100

5 000001010 00000101

8 shows two memory devices in which a microcomputer 10 having a 16-bit multiplex pin 13 and a 16-bit data pin 14 has an 8-bit address pin 21 and an 8-bit data pin 22, respectively. A system connected to a memory system 20 including (23, 24) is shown.

Although the memory devices 23 and 24 store 8-bit data, they are combined to store 16-bit data by storing the lower 8 bits and the upper 8 bits, respectively.

In this case, the pin 13 operates as the multiplex pins A0 to A15.

The microcomputer 10 can supply a signal bus high enable (BHE) for outputting the upper 8-bit data at the pins for the signals D15-D8 (microcomputers for 16-bit data are usually BHE signals). Supply a signal similar to

Then, signal BYTE and address bit A0 are used for chip selection.

That is, the address pin A0 is connected to the chip select input CS1 of the memory device 23, and the signal BHE is supplied to the chip select input CS2 of the other memory device 24.

The address bits A1 to A8 are commonly connected to the address pins of the two memory devices 23 and 24, while the lower 8 bit data bus 421 and the upper 8 bit data bus 422 of the data bus are connected to each other. D0 to D7 and D8 to D15 data pins and memory devices 23 and 24 are connected.

The address signal A0 is set to the H level to receive an 8-bit address from pins A1 to A8 of the microcomputer 10 at pins A0 to A7 and the lower 8 bit data to that data pin via the data bus 421. When receiving the memory device 23 for the lower 8 bits is activated.

Furthermore, the signal BHE is set to the H level so that the upper 8-bit data from the pins A1 to A8 of the microcomputer 10 to the 8-bit address and the data bus 422 to the data pins at pins A0 to A7. When receiving, another memory device 24 for the upper 8 bits is activated.

In this way, 16-bit data can be accessed at the addresses indicated by bits A8 to A1.

In this embodiment, memory 20 and ASSP 30 process 8-bit data, while microcomputer 10 has pins 31 depending on whether the number of bits on buses 41 and 42 is 8 or 16. The output timings of the address signal A and the data signal D for time division can be changed.

The combination of address bits and data bits in the input / output port 4 can be changed in various ways.

9 shows timing charts for other combinations in which address bits A1 to A7 are combined with data bits D1 to D7.

On the other hand, as shown in FIG. 6B, the address bit A0 is not combined with the data bits, and the address bit A8 is combined with the data bits D0.

Table 3 shows data for '0' to '5' supplied by the CPU 1.

Table 3. Data in bit arrays for different combinations of address bits and data bits

CPU ASSP

0 000000000 00000000

1 100000000 00000001

2 000000010 00000010

3 100000010 00000011

4 000000100 00000100

5 100000100 00000101

The microcomputer 10 for the 16-bit bus can be connected to peripherals for 16-bit data and 8-bit data.

Furthermore, if a microcomputer for a 32 bit bus is used, it is also possible for peripherals for 32, 16 or 8 bit data to be connected to it.

Although the present invention has been fully described in connection with the preferred embodiments with reference to the accompanying drawings, various changes and modifications will be readily apparent to those skilled in the art.

It is to be understood that such changes or modifications are intended to be included in the spirit of the present invention as defined by the appended claims unless they depart significantly.

Claims (7)

A central processing unit, an internal bus connected to the central processing unit and connected to the central processing unit through the internal bus and to the central processing unit; A first input / output circuit connected to a first external bus and connected to a second external bus, and a second input / output circuit connected to a second external bus and configured to provide a data signal. A microcomputer comprising a controller for supplying a control signal and a circuit portion for outputting an address signal or a data signal when a specific signal is received from the controller, wherein the combination of the address signal and the data signal output by the circuit portion is the controller. Microcomputer, which can be changed by. The signal of claim 1, wherein the signal indicates whether the signal is multiplexed or non-multiplexed, a timing signal used for the multiplex, And the controller generates a control signal in accordance with a signal and a signal representing the bit width of the first external bus. 3. The microcomputer according to claim 2, wherein said central processing unit includes a pin for setting a signal representing a bit width of said first external bus. 2. The circuit according to claim 1, wherein when the bit width of the first external bus is equal to the number of bits of data processed by the circuit portion, the circuit portion outputs an address signal or data signal A _i / D _i-1 (where i = 1 to 8, A _i represents the i-th bit address signal, and D _i-1 represents the data signal of the i-1 th bit). The microcomputer as claimed in claim 4, wherein the circuit unit is capable of processing 16-bit data when the first external bus to be connected to the circuit unit is a 16-bit bus. 5. The microcomputer according to claim 4, wherein the zeroth address signal A ₀ and the byte high enable signal are used as the chip select signal. The microcomputer according to claim 1, wherein when the first external bus to be connected to the circuit part is an 8-bit bus, the circuit part can process 16-bit data.