KR0165816B1 - Recess etching apparatus of semiconductor process - Google Patents
Recess etching apparatus of semiconductor process Download PDFInfo
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- KR0165816B1 KR0165816B1 KR1019950047362A KR19950047362A KR0165816B1 KR 0165816 B1 KR0165816 B1 KR 0165816B1 KR 1019950047362 A KR1019950047362 A KR 1019950047362A KR 19950047362 A KR19950047362 A KR 19950047362A KR 0165816 B1 KR0165816 B1 KR 0165816B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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Abstract
본 발명에 의한 반도체 제조공정의 퇴행식각방법은 반도체기판 상에 순수 다결정실리콘층을 형성시키고, 순수 다결정실리콘층을 사진식각하여 주변회로 영역과 소자영역 간에 단차가 형성되도록 하는 단계와, 단차가 형성된 순수 다결정실리콘층이 모두 산화될 때까지 산화시켜서 실리콘산화막이 형성되도록 하는 단계와, 실리콘산화막을 제거하여, 반도체기판의 주변회로 영역과 소자영역 간에 단차가 형성되도록 하는 단계를 포함하여 이루어진다.In the method of regression etching of a semiconductor manufacturing process according to the present invention, forming a pure polycrystalline silicon layer on a semiconductor substrate and photoetching the pure polycrystalline silicon layer to form a step between the peripheral circuit region and the device region, and the step is formed. Oxidizing until all of the pure polysilicon layers are oxidized to form a silicon oxide film, and removing the silicon oxide film to form a step between the peripheral circuit region and the device region of the semiconductor substrate.
Description
제1도는 종래의 반도체 제조공정의 퇴행식각방법의 일실시예을 도시한 단면도.1 is a cross-sectional view showing an embodiment of a degenerate etching method of a conventional semiconductor manufacturing process.
제2도는 본 발명에 의한 반도체 제조공정의 퇴행식각방법의 일실시예를 도시한 단면도.2 is a cross-sectional view showing an embodiment of a degenerate etching method of a semiconductor manufacturing process according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10.10'.20.20' : 반도체기판 11.11' : 산화막10.10'.20.20 ': Semiconductor substrate 11.11': Oxide film
12 : 질화막 패턴 13 : 얇은 산화막12: nitride film pattern 13: thin oxide film
21.21' : 순수 다결정실리콘층 22 : 실리콘산화막21.21 ': pure polysilicon layer 22: silicon oxide film
A.A' : 주면회로 영역 B,B' : 소자영역A.A ': Main circuit area B, B': Device area
본 발명은 반도체 제조공정의 퇴행식각(recess etching)방법에 관한 것으로, 특히 반도체기판 상에서 반도체 기억소자가 형성되는 소자(cell)영역과 주변회로 (peri)영역 간에 발생되는 단차 감소에 적당하도록 한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recess etching method of a semiconductor manufacturing process, and more particularly, to a semiconductor suitable for reducing a step difference generated between a cell region in which a semiconductor memory element is formed and a peripheral circuit region on a semiconductor substrate. It relates to a method for manufacturing a device.
반도체 제조에 있어서, 고집적 디램(DRAM) 소장의 제조에 있어서는 캐패시터(capacitor)의 정전용량 증대의 필요성에 따라 캐패시터전극의 표면적을 증가시키기 위한 한 방법으로 캐패시터전극 자체의 높이를 점차로 증가시키고 있으며, 이로 인하여 캐패시터가 형성된 소자영역(메모리셀 형성영역)과 주변회로 영역간의 단차가 점차로 심화되었고, 이러한 단차 발생은 이후의 공정 진행에 많은 어려움을 야기시키고 있다. 따라서 반도체기판의 초기 실리콘 웨이퍼(silicon wafer)상태에서 미리 소자영역과 주변회로영역 간의 단차를 감소시키기 위한 소자영역의 퇴행식각방법이 제안되고 있다.In the manufacture of semiconductors, in the manufacture of highly integrated DRAMs, the height of the capacitor electrode itself is gradually increased as a way to increase the surface area of the capacitor electrode in accordance with the necessity of increasing the capacitance of the capacitor. As a result, a step between the capacitor region (memory cell formation region) and the peripheral circuit region where the capacitor is formed is gradually deepened, and the generation of such a step causes many difficulties in the subsequent process. Therefore, a degenerate etching method of the device region has been proposed to reduce the step difference between the device region and the peripheral circuit region in the initial silicon wafer state of the semiconductor substrate.
제 1도는 종래의 반도체 제조공정의 퇴행식각방법의 일실시예를 도시한 단면도로서, 질화막을 이용한 종래의 반도체 제조공정의 퇴행식각방법의 단계를 도시한 단면도이다. 이하 첨부된 도면을 참고로 종래의 반도체 제조공정의 퇴행식각방법를 설명하면 다음과 같다.FIG. 1 is a cross-sectional view showing an embodiment of a degenerate etching method of a conventional semiconductor manufacturing process, and is a cross-sectional view showing steps of a degenerate etching method of a conventional semiconductor manufacturing process using a nitride film. Hereinafter, the degenerate etching method of the conventional semiconductor manufacturing process will be described with reference to the accompanying drawings.
종래의 반도체 제조공정의 퇴행식각방법에서는 우선, 제1도의 (a)와 같이, 반도체기판(10) 상면에 산화막(oxide)(11)을 형성시키고, 산화막 위에 주변회로영역(A 부위)을 정의하는 질화막 패턴(nitride pattern)(12)을 형성시킨다.In the conventional etching process of the semiconductor manufacturing process, first, an oxide film 11 is formed on the upper surface of the semiconductor substrate 10 as shown in FIG. 1A, and the peripheral circuit region A is defined on the oxide film. A nitride pattern 12 is formed.
즉, 반도체기판 상에 산화막과 질화막을 적층하여 형성시키고, 소자영역(B 부위)의 질화막을 건식식각의 방법으로 사진식각하여 소자영역의 산화막을 노출시키고, 주변회로영역(A부위)에만 질화막이 남도록 하여 주변회로영역을 정의하는 질화막 패턴을 형성시키는 것이다.That is, an oxide film and a nitride film are stacked on a semiconductor substrate, and the nitride film of the device region (site B) is photo-etched by dry etching to expose the oxide film of the device region, and the nitride film is formed only in the peripheral circuit region (site A). It is left to form a nitride film pattern defining a peripheral circuit region.
이때, 반도체기판은 반도체 제조공정에 있어서, 초기 상태의 실리콘 웨이퍼이다.At this time, the semiconductor substrate is a silicon wafer in an initial state in the semiconductor manufacturing process.
이어서 제1도의 (b)와 같이, 주변회로영역을 정의한 질화막 패턴과 소자영역의 노출된 산화막을 산화(oxidation)시킨다. 이로 인하여 주변회로영역(A 부위)에서는 질화막 패턴(12) 위에 얇은 산화막(13)이 형성되고, 소자영역(B 부위)에는 노출된 산화막(11')이 반도체기판(10') 내부로 성장되어 두껍게 형성되며, 또한 소자영역과 주변회로영역 경계부위에서는 소자영역의 노출된 산화막이 산화되어 두꺼운 산화막으로 형성될때에 주변회로영역 쪽으로 침투하면서 반도체기판의 실리콘과 방응하게 되어서, 소자영역쪽으로 점차로 두꺼워 지는 산화막이 형성된다.Subsequently, as illustrated in FIG. 1B, the nitride film pattern defining the peripheral circuit region and the exposed oxide film of the device region are oxidized. As a result, a thin oxide film 13 is formed on the nitride film pattern 12 in the peripheral circuit area A part, and the exposed oxide film 11 'is grown in the semiconductor substrate 10' in the device area B part. At the boundary between the element region and the peripheral circuit region, when the exposed oxide film of the device region is oxidized and formed into a thick oxide film, it penetrates into the peripheral circuit region and reacts with the silicon of the semiconductor substrate to gradually thicken toward the device region. An oxide film is formed.
그리고 제1도의 (c)와같이, 질화막 패턴 위에 형성된 얇은 산화막과 질화막 패턴과 질화막 패턴 하단의 산화막을 제거하여, 반도체기판(10')에서 주변회로영역(A 부위)과 소자영역(B 부위)간에 단차가 형성되도록 한다.As shown in (c) of FIG. 1, the thin oxide film, the nitride film pattern, and the oxide film under the nitride film pattern formed on the nitride film pattern are removed to remove the peripheral circuit region (site A) and device region (site B) from the semiconductor substrate 10 '. Steps are formed in the liver.
즉, 종래의 반도체 제조공정의 퇴행식각방법에서는 반도체기판 상에 산화막을 형성시키고, 산화막 위에 주변회로 영역을 정의하는 질화막 패턴을 형성시킨 후에, 노출된 소자영역의 산화막을 산화시켜서 두껍게 되도록 하고, 두껍게 형성된 산화막을 제거하여 반도체기판에서 주변회로영역과 소자영역 간에 단차가 형성되도록 하고 있다.That is, in the conventional etching method of the semiconductor manufacturing process, an oxide film is formed on a semiconductor substrate, a nitride film pattern defining a peripheral circuit region is formed on the oxide film, and the oxide film of the exposed device region is oxidized to become thick and thick. The formed oxide film is removed so that a step is formed between the peripheral circuit region and the element region in the semiconductor substrate.
그러나 종래의 반도체 제조공정의 퇴행식각방법은 반도체기판 상에 단차를 형성시키기 위한 공정이 복잡하고, 공정 콘트롤(process control)이 용이하지 않았다.However, the conventional etching method of the semiconductor manufacturing process has a complicated process for forming a step on the semiconductor substrate, and process control is not easy.
즉, 종래의 반도체 제조공정의 퇴행식각방법에서 질화막 패턴을 형성시키기 위한 질화막의 건식식각시에 공정 콘트롤이 용이하지 않았으며, 또한 질화막 패턴을 주변회로영역을 보호하는 마스크(mask)로 사용하여 그 외의 산화막을 산화시킬때에, 소자영역의 반도체기판 위에 형성된 산화막의 과다 산화가 발생하게 되면 반도체기판 자체가 손상을 입게 되는 경우가 발생되었다.That is, in the conventional etching method of the semiconductor manufacturing process, the process control is not easy during dry etching of the nitride film for forming the nitride film pattern, and the nitride film pattern is used as a mask to protect the peripheral circuit area. When the other oxide film is oxidized, excessive oxidation of the oxide film formed on the semiconductor substrate in the element region may cause damage to the semiconductor substrate itself.
본 발명은 이러한 문제점을 해결하기 위해 안출된 것으로, 공정이 간단하면서, 공정 콘트롤이 용이한 반도체 제조공정의 퇴행식각방법을 제공하고자 하는 것이 그 목적이다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to provide a method of regression etching of a semiconductor manufacturing process with a simple process and easy process control.
본 발명에 의한 반도체 제조공정의 퇴행식각방법은 반도체기판 상에 순수 다결정실리콘층을 형성시키고, 순수 다결정실리콘층을 사진식각하여 주변회로 영역과 소자영역 간에 단차가 형성되도록 하는 단계와, 단차가 형성된 순수 다결정실리콘층이 모두 산화될 때까지 산화시켜서 실리콘산화막이 형성되도록 하는 단계와, 실리콘산화막을 제거하여, 반도체기판의 주변회로영역과 소자영역 간에 단차가 형성되도록 하는 단계를 포함하여 이루어진다.In the method of regression etching of a semiconductor manufacturing process according to the present invention, forming a pure polycrystalline silicon layer on a semiconductor substrate and photoetching the pure polycrystalline silicon layer to form a step between the peripheral circuit region and the device region, and the step is formed. Oxidizing until all of the pure polysilicon layers are oxidized to form a silicon oxide film, and removing the silicon oxide film to form a step between the peripheral circuit region and the device region of the semiconductor substrate.
제2도는 본 발명에 의한 반도체 제조공정의 퇴행식각방법의 일실시예를 도시한 단면도로서, 이하 첨부된 도면을 참고로 본 발명에 의한 반도체 제조공정의 퇴행식각방법을 설명하면 다음과 같다.2 is a cross-sectional view showing an embodiment of a degenerate etching method of a semiconductor manufacturing process according to the present invention. Hereinafter, the degeneration etching method of a semiconductor manufacturing process according to the present invention will be described with reference to the accompanying drawings.
본 발명에 의한 반도체 제조공정의 퇴행식각방법에서는 우선, 제2도의 (a)와 같이, 반도체기판(20)상에 불순물이 도핑(doping)되지 않은 순수 다결정실리콘층(21)을 형성시키고, 순수 다결정실리콘층 위에 주변회로영역(A' 부위)을 정의하는 감광막 패턴(PR;photoresist pattern)을 형성시킨다.In the degenerate etching method of the semiconductor manufacturing process according to the present invention, first, as shown in FIG. 2A, a pure polysilicon layer 21 in which impurities are not doped is formed on a semiconductor substrate 20, and A photoresist pattern (PR) defining a peripheral circuit region (A ′ portion) is formed on the polysilicon layer.
이때, 반도체기판 상에 형성되는 순수 다결정실리콘층은 반도체기판 상에서 주변회로영역(A' 부위)와 소자영역(B' 부위)간의 확보 예상 단차에 대응되는 두께로 형성시키며, 반도체기판은 반도체 제조공정에 있어서, 초기 상태의 실리콘웨이퍼이다.At this time, the pure polysilicon layer formed on the semiconductor substrate is formed to a thickness corresponding to the expected step between the peripheral circuit region (A 'region) and the device region (B' region) on the semiconductor substrate, the semiconductor substrate is a semiconductor manufacturing process In the initial state of the silicon wafer.
이어서, 제2도의 (d)와 같이, 감광막 패턴을 마스크로하여 순수 다결정실리콘층을 습식식각하여 주변회로영역(A' 부위)과 소자영역(B' 부위)경계에서는 소자영역 쪽으로 기울어진 경사를 가지도록 하면서, 소자영역에는 순수 다결정실리콘층에 의해 반도체기판의 표면이 보호되는 최소의 두께가 남도록 하여, 순수다결정실리콘층(21')의 주변회로 영역과 소자영역 간에 단차가 형성되도록 하고, 감광막 패턴을 제거한다.Next, as shown in (d) of FIG. 2, the pure polysilicon layer is wet-etched using the photoresist pattern as a mask to incline the inclination toward the device region in the peripheral circuit region (A 'region) and the device region (B' region) boundary. In the device region, a minimum thickness of the surface of the semiconductor substrate is protected by the pure polysilicon layer, so that a step is formed between the peripheral circuit region and the device region of the pure polysilicon layer 21 'and the photoresist film is formed. Remove the pattern.
그리고 제2도의 (c)와 같이, 단차가 형성된 순수 다결정실리콘층을 산화시켜서 실리콘산화막(22)이 형성되도록 한다.As shown in FIG. 2 (c), the silicon oxide film 22 is formed by oxidizing the pure polysilicon layer in which the step is formed.
이때, 순수 다결정실리콘층의 산화시에는 주변회로영역(A' 부위)의 순수 다결정실리콘층이 완전히 산화되도록 하며, 이로 인하여 소자영역(B' 부위)에서는 잔재된 순수 다결정실리콘층이 산화되면서 반도체기판(20')의 내부 쪽으로 확산되어서, 실리콘산화막은 비슷한 두께를 가지면서 주변회로영역에서 소자영역 쪽으로 하향으로 기울어져서 형성된다.At this time, when the pure polysilicon layer is oxidized, the pure polysilicon layer in the peripheral circuit region (A 'region) is completely oxidized. As a result, in the device region (B' region), the remaining pure polysilicon layer is oxidized and the semiconductor substrate is oxidized. Diffused toward the inside of 20 ', the silicon oxide film is formed at an inclined downward direction from the peripheral circuit region to the element region with a similar thickness.
이어서 제2도의 (라)와 같이, 실리콘산화막을 제거하여 반도체기판(20')의 주변회로영역(A' 부위)과 소자영역(B' 부위) 간에 단차가 형성되도록 한다.Subsequently, as shown in FIG. 2D, the silicon oxide film is removed to form a step between the peripheral circuit region (A 'portion) and the device region (B' portion) of the semiconductor substrate 20 '.
즉, 본 발명에 의한 반도체 제조공정의 퇴행식각방법에서는 반도체기판 상에 순수 다결정실리콘층을 형성시키고, 순수 다결정실리콘층에 단차를 형성시키고, 단차가 형성된 순수 다결정실리콘층을 완전히 산화시켜서 실리콘산화막이 형성되도록 한 후에, 실리콘산화막을 제거하여 반도체기판의 주변회로영역과 소자영역간에 단차가 형성되도록 하고 있다.That is, in the receding etching method of the semiconductor manufacturing process according to the present invention, a pure polycrystalline silicon layer is formed on a semiconductor substrate, a step is formed in the pure polycrystalline silicon layer, and the pure polycrystalline silicon layer having the step is completely oxidized to form a silicon oxide film. After forming, the silicon oxide film is removed to form a step between the peripheral circuit region and the element region of the semiconductor substrate.
본 발명에 의한 반도체 제조공정의 퇴행식각방법은 종래의 기술에 비하여 공정이 간단해 지며, 또한 종래의 기술로서 제시된 방법에서 질화막 패턴을 형성시키기 위한 건식식각에 비하여 시간 제어가 용이한 습식식각의 방법으로 다결정실리콘층에 단차가 형성되도록 하고 있으므로 공정 콘트롤이 종래의 기술에 비하여 용이하며, 또한 주변회로영역의 순수 다결정실리콘층이 완전히 소모되도록 산화시킴으로 인하여, 소자영역에서는 잔재된 순수 다결정실리콘층이 산화되면서 반도체기판의 실리콘과 같이 산화되어 반도체기판의 내부 쪽으로 확산된 실리콘산화막 형성되도록 하고 있으므로, 과다 산화에 의한 반도체기판의 손상을 최소화시킬 수 있다.The receding etching method of the semiconductor manufacturing process according to the present invention has a simpler process compared to the conventional technique, and a wet etching method which is easier to control the time than the dry etching for forming the nitride film pattern in the method proposed as the conventional technique. As a step is formed in the polysilicon layer, the process control is easier than in the prior art, and since the pure polysilicon layer in the peripheral circuit region is oxidized to be completely consumed, the pure polysilicon layer remaining in the device region is oxidized. As the silicon oxide film is oxidized like silicon of the semiconductor substrate and diffused toward the inside of the semiconductor substrate, damage to the semiconductor substrate due to excessive oxidation can be minimized.
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