KR0165431B1 - Method and apparatus for encoding and decoding a digital data - Google Patents

Abstract

The present invention relates to a method and apparatus for encoding and decoding digital data so as to have a condition of (d, k = d + 2 ^m −1, m, n = d + v (m) +1).

The present invention employs a precoder, sums up a predetermined number of code values input to the precoder in block units, and if the input value is larger than the expected value, inverts the input code and inputs the real code to the real coder. The number of zeros obtained by adding the minimum zero run length to the code value of the input code is encoded by attaching it to 1 and decoding it. In addition, in the present invention, a precoder adds a plurality of offset values to an input code value, accumulates the result of each sum in units of blocks, selects an offset value having the largest value among the accumulated values, and selects an input code and a selected offset value. It is added and input to the real coder. The real coder encodes and decodes the number of zeros plus one zero run length plus the code value of the input code supplied from the precoder.

Description

Digital data encoding and decoding method and apparatus therefor

1 is a block diagram according to an embodiment of a digital data encoding apparatus according to the present invention.

2 is a block diagram according to an embodiment of a digital data decoding apparatus according to the present invention.

3 is a block diagram according to another embodiment of a digital data encoding apparatus according to the present invention.

4A and 4B are detailed views of the offset accumulator and offset operator shown in FIG. 3, respectively.

5 is a block diagram according to another embodiment of a digital data decoding apparatus according to the present invention.

6 is a detailed view of the offset operator shown in FIG.

7 is a diagram showing the relationship between the minimum zero run length of a code supplied from the encoding apparatus of the present invention and the recording density.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data encoding and decoding method and apparatus, and more particularly, to a method and apparatus for encoding and decoding for implementing a highly efficient encoding in a simple configuration while satisfying a predetermined code condition.

Recently, a method of converting video and audio signals into digital signals and then transmitting them by source encoding and channel encoding or storing them in a storage unit such as a magnetic recording medium or an optical recording medium, and channel decoding and source decoding are reproduced. have.

The source encoding method is a technique of compressing the source data amount by removing the redundancy of the source data. However, the channel encoding differs from the robustness of the system against the occurrence of errors on the channel by adding redundancy to the data. It is a technique to increase. Channel encoding is also called modulation.

Among these channel encoding methods, channel data (hereinafter referred to as RLL data) encoded by the RLL (Run Length Limited) encoding method mainly used in the optical recording / reproducing apparatus has a condition of (d, k, m, n).

In the condition (d, k, m, n), d is the minimum number of consecutive zeros (hereinafter referred to as the minimum zero run length), k is the maximum number of consecutive zeros (hereinafter referred to as the maximum zero run length), m Denotes the number of bits of the code input to the encoder (hereinafter referred to as the number of input code bits), and n denotes the number of bits of the transmission code after being modulated (hereinafter referred to as the number of transmission code bits). This RLL data is also referred to as (d, k) -constrained RLL data because the number of consecutive zeros is at least d and is suppressed to zero number not greater than k. Codes using this RLL encoding method include (1,7) code, (2,7) code, EFM code, and Modified EFM code.

On the other hand, magnetic recording density techniques for recording signals on magnetic recording media with high density have been developed, but the limitations of magnetic recording density techniques, for example, the size of the head gap should be at least smaller than λ / 2 of the recording wavelength λ. Due to the limitation of the present invention, there are many difficulties in recording a large amount of digital video signals for a long time.

In addition, in the encoder of the optical recording and reproducing apparatus for recording and reproducing digital signals on optical recording media such as compact discs and laser discs, the recording density ratio becomes an important parameter for high density recording. This is because the size of the minimum feet is physically limited in the optical recording and reproducing apparatus, and the recording density ratio indicates the number of bits of the input code that can be recorded in the minimum feet. The larger the value of this recording density ratio is, the higher the density can be.

The inventor has devised a high-efficiency encoding method using the RLL encoding method, and can be employed in not only an optical recording / reproducing apparatus but also a digital data recording and reproducing apparatus using a magnetic recording medium, and a digital data transmitting / receiving apparatus.

Accordingly, it is an object of the present invention to provide an encoding and decoding method that realizes highly efficient encoding while satisfying a predetermined code condition using an RLL encoding method.

Another object of the present invention is to provide an encoding and decoding apparatus for realizing high efficiency encoding with a simple configuration.

The present invention includes a precoder and adds a predetermined number of code values input to the precoder in a block unit, and when the input code value is larger than the expected value, the input code is inverted and the real coder inputs the input code. The number of zeros corresponding to the sum of the sign value of the sign and the minimum zero run length is added to the circle 1 for encoding and decoding.

In the present invention, the pre-encoder combines m-bit input codes with each offset value corresponding to 0 to 2 ^m -1 in block units, divides them by 2 ^m , accumulates the remaining values in block units, and accumulates them. The offset value which has the largest value among the selected values is selected and the selected offset value is added to the code value of the input code and input to the real coder. It is characterized by coding the number of zeros corresponding to the sum of the lengths to the circle 1 and encoding them.

First, the encoding method according to the present invention will be described.

According to the encoding method of the present invention, a transmission code is encoded by attaching 0 to 1 corresponding to the number of the minimum zero run length d plus the code value of the input code.

For example, when d = 3 and m = 3, the transmission code for the input code is configured as shown in Table 1 below.

The encoding method proposed in the present invention is (d, k = d + 2 -1, m, n = d + v (m) + 1), where v (m) means the sign value of the input code, the number of transmission code bits (n) is not fixed Is variable.

Therefore, for an m-bit input, the transmission code changes the length of the transmission code from time to time in the encoding method in which the number of zeros is added to 1 by adding the minimum zero run length d to the code value of the input code. For example, if the input code with the minimum code value is continuous, the transmission code has the minimum code length. If the input code with the maximum code value is continuous, the transmission code has the maximum code length. As such, since the length of the transmission code is variable, it is difficult to process the transmission code in real time.

In order to process the data encoded by the encoding method proposed by the present invention in real time, the bit amount of the result of encoding the input code having the maximum code value in block units by using a predetermined input code in block units (also called coding units). If the actual bit amount of the block unit is less than the allowable bit amount, and there is a method to enable real-time processing using a method of carrying the dummy data or burst signal for the remaining bit amount. However, in this method, since the actual amount of bits in a block unit is always smaller than the allowable bit amount, the coding efficiency is lowered.

Therefore, in the present invention, the above-mentioned (d, k = d + 2 while improving the coding efficiency The precoder is used to implement an encoder having a condition of -1, m, n = d + v (m) +1). For example, you can configure a precoder that performs the method shown below.

The first method is to add the code value of the code input to the precoder in a predetermined unit corresponding to the block unit, and if the input code value is larger than the expected value, the input code is inverted and input to the real coder.

The second method is 0 to 2 for m bits of input code in the precoder. After adding the offset value corresponding to -1 to the input code value, 2 After dividing by, accumulate the remaining values in block units, select the offset value with the largest value among the accumulated values, and add the input offset value to the actual encoder.

Next, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram according to an embodiment of a digital data encoding apparatus according to the present invention employing a precoder that performs the first method.

The configuration of the apparatus shown in FIG. 1 includes a buffer 11 for storing input code in block units, an accumulator 12 for accumulating code values of input code data in block units, and an accumulator 12. A precoder (10) comprising a discrimination controller (13) for recognizing the result of and outputting an inversion control signal based on the recognized result, and an inverter (14) for inverting data stored in the buffer (11) in accordance with the inversion control signal. ), The assembler 20 for assembling the sync data, the burst signal, the inverted part information, etc. to the code data supplied from the inverter 14, the code value of the code supplied from the assembler 20, and the minimum zero run. An adder 31 that adds the length, a counter 33 that counts the sum of the input code value and the minimum zero run length, and the added value from the adder 31 and the count value from the counter 33 are compared. An actual encoder 30, which is a comparator 33, Is the output of the equalizer 30 to the NRZI conversion section 40 for generating a signal array by converting NRZI (Non Return to Zero Inverted). Here, the NRZI converter 40 may be referred to as a modulator.

Next, the operation of the apparatus shown in FIG. 1 will be described.

According to FIG. 1, input data, for example, 3-bit coded data is stored in the buffer 11 in units of blocks. If the input data is video data, the block unit may be a frame, a field, a track, or a segment.

The accumulator 12 accumulates input 3-bit code data in block units. The discrimination controller 13 outputs the reset signal to the accumulator 12 when the number of bits in the block unit is stored in the accumulator 12, and compares the code value of the accumulated block unit with the predetermined expected value. If the sign value is equal to or larger than the expected value, the inversion control signal is supplied to the inverter 14 and the assembler 20 so as to invert the data stored in the current buffer 11. Here, the expected value may be set to, for example, an average value of input codes in block units.

If the sum of the code values of the input codes in the block unit is larger than the expected value, it means that the number of the input codes having a larger value than the average value among the input codes is larger than the number of codes having a value below the average value.

If the sum of the input code values in the block unit is smaller than the expected value, the number of bits of the transmission code in the block unit also becomes smaller than the expected value. Therefore, if the input code in the block unit is larger than the expected value, simply inverting the input code always satisfies the condition of the transmission code smaller than the expected value.

Therefore, the inverter 14 inverts the code data of the block unit stored in the buffer 11 in accordance with the inversion control signal supplied from the discrimination controller 13.

The assembler 20 inserts a sink at a predetermined position into code data in units of blocks supplied through the inverter 14, and according to the inversion control signal, additional information indicating that the code data of the block is inverted data (hereinafter, inverted). And the burst signal for the smooth operation of a phase locked loop (PLL) on the decoding side by inserting an additional bit amount after encoding the allowable bit amount corresponding to the expected value. The burst signal is set to a signal having a minimum period as long as possible but longer than the system clock ratio to compensate for the frequency characteristics of the channel deteriorated during transmission or a signal that can be accommodated in the transmission line. Here, the position of the assembler 14 may be configured at the rear end of the actual encoder 30.

In the adder 31 of the actual encoder 30, the minimum zero run length d is added to the code value of the m-bit code data supplied through the assembler 20. For example, the 0 sign data adds the sign value 0 corresponding to 0 and the minimum zero run length d in the adder 31. Then, the comparator 32 compares 3 supplied from the adder 31 with the count value from the counter 33, and outputs 0 if not equal, and 1 if equal. When the comparison result is the same, the output of the comparator 32 becomes 1, and when 1 occurs, the counter 33 is reset. In the actual encoder 30, since the output of the comparator 32 is 1, a configuration for converting to 1000 may be added. However, since the decoding result is the same, the actual encoding may be performed as it is.

Here, since the actual encoder 30 generally uses a lookup table using a ROM, the lookup table may be used. However, in the present invention, the circuit may be configured more simply as a logic circuit.

Therefore, the number of bits of the transmission code in block units supplied from the actual encoder 30 is the value obtained by multiplying the number of input codes by the minimum zero run length (d + 1) plus 1 and the input code value in block units. do. The number of predetermined input codes in blocks and the value of the minimum zero run length d are set in advance.

The NRZI converter 40 converts the data encoded by the real coder 30 to NRZI for efficient recording and transmission through a recording medium or channel. That is, the inversion of the recording waveform is performed only at the boundary of the bit information and inverts the state of the information only when the bit information is one. NRZI conversion used for such recording and NRZI conversion used for reproduction are disclosed in US Pat. No. 5,122,912.

2 is a block diagram according to an embodiment of a digital data decoding apparatus according to the present invention for decoding data encoded by the encoding apparatus shown in FIG.

The configuration of the apparatus shown in FIG. 2 is characterized by the NRZ conversion unit 50 for NRZ conversion of data transmitted or reproduced through a channel or recording medium, and until 1 is detected in the signal sequence supplied from the NRZ conversion unit 50. The decoder 61 which consists of the counter 61 which counts the number of zeros, the code generator 62 which outputs the count result of the counter 61 with the original m-bit code, and the decoder 60 decoded. A disassembler 70 that separates the sync, burst signal and inverted information from the data, and an inverter 81 that inverts again when the decoded data output from the disassembler 70 is inverted data. The post processor 80 is a buffer 82 for storing the data decoded through the block unit.

Referring to the operation of the apparatus shown in FIG. 2, the NRZ converter 50 converts the NRZI-converted data transmitted or reproduced through a channel or a recording medium from 0 to 1, and outputs 1 to NRZ. Generate a signal sequence.

In the counter 61 of the decoder 60, when 1 is detected from the NRZ converter 50, the counter 61 inputs it as a reset signal and counts the next input number of zeros. For example, if the number of zeros counted by the counter 61 is three, the code generator 62 outputs three bits of sign data zero. Here, the code generator 62 may be referred to as a decoding circuit composed of logic circuits, or may be configured as a lookup table using a ROM.

The deassembler 70 separates the sink, burst signal, and inverting information from the decoded data output from the decoder 60.

The inverter 81 inverts the decoded data according to the inversion unit information and stores the decoded data in the buffer 82 in units of blocks.

Here, the buffer 11 shown in FIG. 1 and the buffer 82 shown in FIG. 2 are necessary for real time processing. In addition, when an error correcting encoder is configured at the front of the buffer 11 shown in FIG. 1, the buffer 11 may be shared as a memory required for error correcting encoding, and the buffer 82 of FIG. When the error correction decoder is configured at the back, the buffer 82 may be shared as a memory required for error correction decoding.

FIG. 3 is a block diagram according to another embodiment of the digital data encoding apparatus according to the present invention employing a precoder for implementing the second method, and detailed description of the same configuration as that shown in FIG. 1 will be omitted.

In comparison with FIG. 1, the arrangement of the apparatus shown in FIG. Cumulative circuit 112 comprising two offset accumulators; Select the offset value of the offset accumulator which has the largest value among the outputs of the two offset accumulators. A discrimination controller 113 for outputting a reset signal for resetting two offset accumulators to each offset accumulator, and an offset operator for adding a sign supplied from the buffer 111 and a selected offset value supplied from the discrimination controller 113 ( 114) is different.

The operation of the apparatus shown in FIG. 3 will be described in the case where the number of bits m of the input code is 3 by combining FIGS. 4A and 4B. According to FIG. 3, the accumulator circuit 112 is composed of eight offset accumulators because the number of bits of the input code is three bits. In each of these eight offset accumulators, offset values from 0 to 7 are set.

Each offset accumulator is composed of an adder, a calculator, and an integrator, as shown in FIG. 4A. The adder 112.1 adds a corresponding offset value with a 3-bit input code and adds the result of the divider 111.2. Dividing by 8 detects the remainder and inputs only the lower 3 bits to the integrator (111.3). In the integrator 111.3, the output value of the divider 111.2 is integrated in units of blocks.

The discrimination controller 113 selects an offset accumulator having a maximum value among the values accumulated in each integrator of the eight offset accumulators, and outputs an offset value corresponding to the offset accumulator 114 and the assembler 120.

In the offset operator 114, as shown in FIG. 4B, the adder is configured, and the offset value supplied from the discrimination controller 113 is added to the code data supplied from the buffer 111 to output only the lower 3 bits.

The assembler 120 assembles additional information (hereinafter, referred to as offset additional information) about the sink, the burst signal, and the offset value. The real coder 130 adds 0 to the NRZI converter 140 by adding 0 to the number of the sum of the minimum zero run lengths and the code value of the code supplied from the assembler 120.

Accordingly, the encoding apparatus shown in FIG. 3 adds offset values from 0 to 7 to the input code values for each input code, divides by 8, accumulates the remainder in block units, and has the largest value among the accumulated values. The offset value is selected and the selected offset value is added to the input code value and recorded or transmitted.

By doing this, the code value of the input code can be adjusted to the smallest value when the unit of the block is added, because the number of bits per block of the transmission code can be made the smallest.

FIG. 6 is a block diagram according to another embodiment of a digital data decoding apparatus according to the present invention for decoding data encoded by the encoding apparatus of FIG. 3, and detailed configuration description thereof will be omitted. .

Compensated offset value 2 supplied from the disassembler 170 instead of the inverter 81 compared to the apparatus shown in FIG. -Offset value) and offset operator 181 for adding the decoded data.

The operation shown in FIG. 6 will be described with reference to FIG.

Referring to FIG. 6, the NRZ conversion unit 150 generates a signal sequence by converting the NRZI converted data transmitted or reproduced through a channel or a recording medium into a NRZ that outputs 1 at the time of converting 0 to 1 data.

In the counter 161 of the decoder 160, if the data supplied from the NRZ converter 150 is 1, it is input as a reset signal, and the number of the next input 0 is counted. Generates sign data.

The deassembler 170 separates the sink, burst signal, and offset additional information from data supplied from the decoder 160.

The offset operator 181 of the post processor 180 is configured with an adder as shown in FIG. 6, and adds the complement (8-offset value) of the offset value used in encoding from the assembler 170 to the decoded data. To restore the original code. The decoded data supplied through the offset operator 181 is supplied to the buffer 181, and the buffer 182 stores the decoded data in units of blocks.

The relationship between the minimum run length d and the recording density ratio DR of the data encoded by the encoding apparatus shown in FIGS. 1 and 3 is as shown in FIG.

As shown in FIG. 7, it can be seen that the recording density ratio DR of the code increases as the minimum zero run length d increases, and when the number of bits m of the input code is larger than 4, the recording becomes relatively. It can be seen that the density ratio DR rapidly decreases. In addition, the relationship between d and DR can be seen that DR converges to the value of m as the value of d increases infinitely. Therefore, in the present invention, it is preferable to set m to be smaller than 4 and d to be smaller than 20.

In addition, in order to compare the recording density ratio of the data encoded by the present invention with the recording density ratio DR of the existing RLL data, the recording density ratio of the existing RLL data can be expressed by the following expression (1).

The larger the value of the recording density ratio DR, the higher density recording is possible. As an example, in the case of widely used (1,7) codes, the code ratio is 2/3, so DR is 4/3, and in the case of (2,7) codes, the code ratio is 1/2, Becomes 3/2.

The encoder proposed in the present invention has a condition of (d, k = d + 2 ^m -1, m, n = d + v (m) + 1), where v (m) is a code value of the input code Therefore, since n is not a fixed value but a variable that is always changing, the average value of the number of transmission code bits (n _AVG ) is

Becomes

The average value of the recording density ratio (DR _AVG ) determined according to the above conditions is

And the average value of the diesel fuel DR with d = 3 and m = 3 is 12 / 7.5.

In the present invention, for example, the DR becomes 2 for a condition of m = 3 and d = 6, so that two bits per pit can be recorded. Therefore, the present invention has an effect of increasing the recording density by 40% when the encoding is performed under the condition of m = 3 and d = 6, compared to 1.411 when the EFM code widely used in the conventional optical disc recording apparatus is encoded.

In addition, the present invention can be configured as a simple logic circuit without using a lookup table using a ROM, and the buffer can be shared with the buffer required for error correction and decoding, so that the circuit can be easily configured. .

Claims (26)

Encoding to data having (d, k, m, n) conditions representing the minimum zero run length (d), the maximum zero run length (k), the number of input code bits (m), and the number of transmission code bits (n), respectively. In the method: (a) an inversion control signal based on a result determined by accumulating the code values of the input code in block units of a predetermined number of codes and determining whether the accumulated values are larger than a predetermined expected value; Generating a; (b) inverting the input code in block units according to the inversion control signal; And (c) adding to the circle 1 a number of zeros corresponding to the sum of the sign value of the input code and the minimum zero run length for the input code obtained in the step (b). Digital data coding method. The method of claim 1, wherein the data encoded in step (c) has a condition of (d, k = d + 2 ^m −1, m, n = d + v (m) +1), where v (m ) Denotes a code value of an input bit, and the number of transmission code bits (n) is variable. The digital data encoding method of claim 2, wherein the number of input code bits (m) is set to 4 or less, and the minimum zero run length (d) is set to 20 or less. The digital data encoding method of claim 1, wherein the predetermined expected value is an average value of input codes in the block unit. Encoding to data having the conditions (d, k, m, n) indicating the minimum zero run length (d), the maximum zero run length (k), the number of input code bits (m), and the number of transmission code bits (n), respectively. In the method: (a) For an m-bit input code, the offset value corresponding to 0 to 2 ^m -1 is added to the input code value, and the result of each sum is divided by 2 ^m, and the remainder is converted into a predetermined number of codes. Accumulating in units of blocks and selecting an offset value having the largest value among the accumulated values; (b) adding the selected offset value and the input code to output the lower m bits of the added result; And (c) adding to the circle 1 a number of zeros corresponding to the sum of the sign value and the minimum zero run length of the result obtained in the step (b). Way. The method of claim 5, wherein the data encoded in the step (c) has a condition (d, k = d + 2 ^m -1, m, n = d + v (m) + 1), where v (m ) Denotes a code value of an input code, and the number of transmission code bits (n) is variable. The digital data encoding method according to claim 6, wherein the number of input code bits (m) is 4 or less and the minimum zero run length (d) is set to 20 or less. The data is encoded with data having the conditions (d, k, m, n) indicating the minimum zero run length (d), the maximum zero run length (k), the number of input code bits (m), and the number of transmission code bits (n), respectively. A method of decoding coded data, comprising: (a) accumulating a code value of an input code in a block unit of a predetermined number of codes and determining whether the accumulated value is larger than a predetermined expected value. Generating an inversion control signal on the basis of; (c) inverting the input code in block units according to the inversion control signal; (c) encoding and adding to the circle 1 a number of zeros corresponding to the sum of the code value of the input code and the minimum zero run length for the input code obtained in the step (b); (d) NRZI-converting the data encoded in the step (c) to generate a code string and transmitting the code string through a channel; (e) NRZ converting NRZI data transmitted through the channel to detect a code string; (f) decoding the original m-bit code from the detected code string; And (g) inverting again if the decoded data is the code inverted in the step (b). The data is encoded with data having the conditions (d, k, m, n) indicating the minimum zero run length (d), the maximum zero run length (k), the number of input code bits (m), and the number of transmission code bits (n), respectively. CLAIMS 1. A method for decoding coded data; (a) For each m-bit input code, add an offset value from 0 to 2 ^m -1 to the input code value, and divide the result of each summation by 2 ^m and divide the remainder in block units of a predetermined number of codes. Accumulating and selecting an offset value having the largest value among the accumulated values; (b) adding the selected offset value and the input code and outputting the lower m bits of the result of the addition; (c) encoding by adding a number of zeros corresponding to the sum of the sign value and the minimum zero run length of the result obtained in the step (b) to the circle (1); (d) NRZI-converting the data encoded in the step (c) to generate a code string and transmitting the code string through a channel; (e) NRZ converting NRZI data transmitted through the channel to detect a code string; (f) decoding the original m-bit code from the detected code string; And (g) a step of performing complement and offset operation on the decoded data in the offset value selected in the step (a). Encoding to data having the conditions (d, k, m, n) indicating the minimum zero run length (d), the maximum zero run length (k), the number of input code bits (m), and the number of transmission code bits (n), respectively. An apparatus comprising: pre-coding means for inverting an input code if the code value of an input code in a block unit having a predetermined number of codes is larger than a predetermined expected value and outputting it as it is; And actual encoding means for encoding by adding a number of zeros corresponding to the sum of the input code value and the minimum zero run length to the circle 1 with respect to the input code supplied through the precoding means. Digital data encoding apparatus characterized by the above-mentioned. 11. The apparatus of claim 10, wherein the precoding means comprises: an accumulator accumulating the code values of the input code in units of blocks; A discrimination controller for outputting an inversion control signal when the accumulated value is larger than a predetermined expected value; A buffer for storing the input code in block units; And an inverter for inverting the input code supplied through the buffer in units of blocks according to the inversion control signal. 12. The apparatus of claim 11, wherein the actual encoding means comprises: an adder for adding a sign value and a minimum zero run length of an input code supplied through the inverter; A counter that counts until a reset signal is input; And a comparator for comparing the added result with the count value and outputting 0 if the comparison result is not the same, and outputting 1 if the comparison result is the same and outputting this 1 as a reset signal of the counter. Digital data coding apparatus. 13. The apparatus of claim 12, further comprising: an assembler for assembling additional information about the sink and the inversion control signal to an input code output through the precoding means; And conversion means for NRZI transforming the output of the actual encoding means. The digital data encoding apparatus of claim 13, wherein the assembler further inserts a burst signal for smoothly operating the PLL during decoding. Encoding to data having the conditions (d, k, m, n) indicating the minimum zero run length (d), the maximum zero run length (k), the number of input code bits (m), and the number of transmission code bits (n), respectively. In the apparatus; Pre-coding means for adding the input codes to a plurality of offset values, respectively, accumulating each added result in block units, selecting an offset value having the largest value among the accumulated results, and adding the input code and the selected offset value. ; And an actual encoding means for encoding by adding a number of zeros corresponding to the sum of the input code value and the minimum zero run length to the circle 1 with respect to the m-bit input code supplied through the precoding means. Digital data encoding apparatus characterized in that. 16. The apparatus of claim 15, wherein the precoding means comprises: a buffer for storing an input code in block units; A cumulative circuit comprising 2 ^m offset accumulators for adding the sign value of the input code and each offset value corresponding to 2 ^m −1 from 0, and dividing the added result by 2 ^m and accumulating the remainder in block units; Determination of selecting the offset value in the offset accumulator having the largest value of the output of the 2 ^m of offset accumulator, and when the input of the block unit code value is the cumulative output of the reset signal to 2 ^m of offset stacked groups reset Controller; And an offset operator for adding the input code supplied from the buffer and the selected offset value. 17. The apparatus of claim 16, wherein each offset accumulator of the accumulation circuit comprises: an adder for adding an input code of m bits and the selected offset value; A divider for dividing the result added by the adder by 2 ^m and outputting the remainder of the lower m bits; And an integrator for integrating the remainder output from the divider in units of blocks. 17. The apparatus of claim 16, wherein the actual encoding means comprises: an adder for adding a sign value and a minimum zero run length of an input code supplied through the offset operator; A counter that counts until a reset signal is input; And a comparator for comparing the added result with the count value and outputting 0 if the comparison result is not the same, and outputting 1 if the comparison result is the same and outputting this 1 as a reset signal of the counter. Digital data coding apparatus. 19. The apparatus of claim 18, further comprising: an assembler for assembling the sink and additional information about the selected offset to a code supplied through the offset operator; And conversion means for generating a signal sequence by NRZI conversion of the output of the actual encoding means. 20. The digital data encoding apparatus of claim 19, wherein the assembler further inserts a burst signal for smoothing the operation of the PLL during decoding. If the cumulative result of accumulating the code of m-bits input in blocks is larger than the expected value, the input code is inverted to decode the coded data by adding the number of input code values plus the minimum zero run length to 1 and decoding the encoded data. In the apparatus; Decoding means for decoding the coded data into an original m-bit code; And inverting means for inverting again if the decoded data is inverted code data at the time of encoding. Add the m-bit code and a plurality of offset values to be input, respectively, accumulate a plurality of added results in units of blocks, select an offset value having the largest value among the accumulated values, and add the selected offset value to the input code. An apparatus for decoding data encoded by adding the number of zeros including an added code value and a minimum zero run length to 1; Decoding means for decoding the coded data into an original m-bit code; And means for restoring original code data by adding the complement of the selected offset value to the decoded code. An apparatus for encoding and decoding data having (d, k, m, n) conditions representing minimum minimum run length, maximum zero run length, input code bits, and transmission code bits, respectively; Pre-coding means for inverting the inputted code if the coded value of the input code in block units having a predetermined number of codes is larger than the predetermined expected value, and otherwise outputting it as it is; An assembler for assembling a burst signal for controlling a PLL operation during sinking and decoding to a code supplied from the precoding means and additional information on the inversion information; Actual encoding means for encoding by adding a number of zeros corresponding to the sum of the input code value and the minimum zero run length to the circle 1 with respect to the input code supplied from the assembler; Conversion means for NRZI-converting the encoded data to generate a code string and to transmit the coded data through a channel; Detection means for NRZ transforming NRZI data transmitted through the channel to detect a code string; Decoding means for counting the number of zeros before one is detected from the detected signal sequence and generating an m-bit code having a code value corresponding to zero number; A deassembler for separating side information of the sink, the burst signal, and the inversion from the data decoded by the decoding means; And inverting means for inverting the decoded data again according to the inverting additional information. 24. The apparatus of claim 23, wherein said decoding means comprises: a counter for counting a number of zeros until one is detected in a transmission string supplied from said detecting means; And a decoding circuit for generating an m-bit code based on the counter result of the counter. An apparatus for encoding and decoding data having (d, k, m, n) conditions representing minimum minimum run length, maximum zero run length, input code bits, and transmission code bits, respectively; Pre-coding means for adding the input codes to a plurality of offset values, respectively, accumulating each added result in block units, selecting an offset value having the largest value among the accumulated results, and adding the input code with the selected offset; An assembler for assembling a burst signal for controlling a PLL operation during sinking and decoding to a code supplied from the precoding unit and additional information on the selected offset; An actual encoding means for encoding by adding to the circle 1 a number of zeros corresponding to the sum of the input code value and the minimum zero run length for the m-bit input code supplied from the assembler; Conversion means for NRZI-converting the encoded data to generate a code string and to transmit the coded data through a channel; Detection means for NRZ transforming NRZI data transmitted through the channel to detect a code string; Decoding means for counting the number of zeros before one is detected from the detected signal sequence and generating an m-bit code having a code value corresponding to zero number; A deassembler for separating side information on the sink, the burst signal, and the offset value from the data decoded by the decoding means; And means for reconstructing the decoded code to the original code by adding the complement of the generated offset value to the original code. 26. The apparatus of claim 25, wherein said decoding means comprises: a counter for counting a number of zeros until one is detected in a transmission string supplied from said detecting means; And a decoding circuit for generating an m-bit code based on the count result of the counter.