KR0164825B1 - Semiconductor memory device having non-shared bit line sense amplifier - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor memory device having a non-shared sense amplifier of the semiconductor memory device.

2. The technical problem to be solved by the invention

According to the present invention, the discrete and N-type sense amplifiers facing each other are individually disposed in individual memory array array blocks so that the load applied to the pair of bit lines is equalized so that the bit line sensing speed is uniform even when the I / O line is increased and the area of the I / O circuit is expanded. This circuit controls the core circuit structure and the separation gate circuit between the memory array array block in the semiconductor memory device. The sensing enable signal and the row address signal are inputted to simultaneously separate the gate control signals of different logic signals. Generation, providing improved charge sharing voltage between the memory pin and the bit line and improved bit line sensing speed.

3. Summary of Solution to Invention

The present invention provides a semiconductor memory device having a plurality of memory array array blocks including one or more memory arrays and a plurality of bit line pairs connected between the memory array arrays and the memory arrays in the neighboring memory array array block. A plurality of equalization circuits located between the memory array array blocks adjacent to each other and connected to the bit line pairs to input a predetermined control signal to match the bit line pairs to the same voltage level, and between the equalization circuits. A sense amplification circuit comprising a sense sense amplifier and an n-type sense amplifier respectively located between the memory array array blocks connected to the bit line pair and adjacent to each other, and a predetermined control signal is input between the sense amplifier circuits. A plurality of separation gates connected to the pair of bit lines And a column select gate positioned between the separation gate circuits and connected to the bit line pair and the input / output line pair to receive and drive a column select signal.

4. Important uses of the invention

It is suitably used for a semiconductor memory device having a core structure including a sense amplifier.

Description

Semiconductor Memory Device Sharing Non-Bitline Sense Amplifier

1 is a specific circuit diagram of a core circuit according to the prior art.

2 is a specific circuit diagram of a core circuit according to the present invention.

3 is an operation timing diagram of a core circuit according to the present invention.

4 is a specific circuit diagram of a separation gate control circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

70,80: word line 100,200: memory chip array block

300,900: equalization circuit RA, : Low address

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a bit line sense that eliminates bit line loading connected to a neighboring memory array array block to increase the initial bit line sensing speed and to improve charge sharing voltage. The present invention relates to a semiconductor memory device for sharing an amplifier.

In general, in the core circuit of a semiconductor memory device, for example, a random access memory, the memory array array blocks share an input / output circuit and a sense amplifying circuit composed of an input sense amplifier and an n type sense amplifier. Also, in the core circuit of dual port memory, the memory array array blocks share not only the sense amplification circuit and the random access memory input / output circuit, but also serial access memory and serial access memory input / output circuit.

1 is a core circuit of a semiconductor memory device according to the prior art. Looking at the configuration of Figure 1 as follows. A word line 70 and a bit line pair BL / BLB, a gate is connected to the word line 70, a drain is connected to the bit line BL, and one side is connected to an internal power supply voltage 40 and an NMOS transistor 1 having a source connected to a capacitor 2, A memory 구성된 composed of the capacitor 2 having the other end connected to the MOS transistor 1, an MOS transistor 3 having a gate connected to a word line 80, a drain connected to the bit line BL, and a source connected to a capacitor 4, and an internal power supply. A memory 구성된 composed of the capacitor 4 having one side connected to a supply voltage 40 and the other side connected to the enMOS transistor 3, memory 쎌 array blocks 100 and 200 comprising a plurality of the memory 쎌, and a right side of the memory 쎌 array block 100. An equalization cycle consisting of enMOS transistors 5, 7, and 9, which is located at and connected between the bit line pairs BL / BLB The gate 300 and the right side of the equalization circuit 300 are connected to gates of the NMOS transistor 11 and the NMOS transistor 13 and the drains and the sources of the NMOS transistors 11 and 13 are respectively connected to the bit lines BL and BLB. One end of each of the connected isolation gate circuits 400 and the bit line pairs BL / BLB, which are located on the right side of the separation gate circuits 400, and the other ends thereof are interconnected to the PMOS transistors 15 and 17 and the PMOS transistors 15 and 17. A p-type sense amplifier 500 having a latch structure, one end of which is connected to an interconnected node of the second terminal and the other end of which is connected to a power supply voltage terminal (VCC); A column select gate composed of enMOS transistors 21 and 23 connected to a line pair BL / BLB, and the enMOS transistors 21 and 23, respectively. Profane O line pair IO / An n-type sense amplifier 700 comprising an input / output circuit 600 composed of an NMOS transistor 25, 27, and 29, which is disposed on the right side of the input / output circuit 600, and has the same latch structure as the type sense amplifier. And an equalization circuit 300 having an isolation gate circuit 800 formed of a connection of the NMOS transistors 31 and 33 in the same manner as the isolation gate circuit 400, and an NMOS transistor 35, 37 and 39 located on the right side of the isolation gate circuit 800. Equalization circuit 900 is configured in the same way as. It can be seen that the above configuration is symmetrical with respect to the input / output circuit 600. Referring to the principle of operation of Figure 1 as follows. In order to precharge the bit line pair BL / BLB of the memory array array block 100,200, each of the isolation gate driving signals PIISOL and PIISOR maintains a logic low, and each of the isolation gate circuits 400,800 is turned on. The equalization circuit 300,900 is operated by the bit line precharge voltage VBL having the voltage of VCC and the equalization control signal PIEQ to precharge the bit line pair BL / BLB to a voltage of 1/2 · VCC. At the same time word line 70,80 is selected, enMOS transistors 1 and 4 are turned on so that the charges stored in capacitors 2 and 4 of memory VII are charged and shared with the parasitic capacitors of bit line BL. 2 · VCC + α is changed. For example, when the memory array array 100 is selected by an external address signal, the isolation gate circuit 800 is turned off, and the isolation gate circuit 400 is turned on to provide the sense amplifier 500, the n-type sense amplifier 700, and the input / output circuit 600. The bit line pair BL / BLB of the memory V array block 100 is connected. The N-type sense amplifier 700 is driven by the N-type sense amplifier control signal LANG to direct the voltage of the bit line having the lower voltage among the bit lines BL and BLB to the ground voltage VSS through the N-type transistors 25, 27 and 29. Therefore, the voltage of one of the bit lines BL and BLB is lower than before. In addition, the sensed amplifier 500 is driven by the controlled sense amplifier control signal LAPG to direct the voltage of the bit line having the higher voltage among the bit lines BL and BLB to the power supply voltage VCC through the shaped MOS transistors 15, 17 and 19. . Therefore, the voltage of the selected bit line is higher than before. The amplified voltage as described above is applied to the input / output circuit 600 so that the column select gate enMOS transistors 21 and 23 receiving the column select signal CSL as inputs are turned on, respectively, so that the input / output line pair IO / Is applied to. I / O line pair IO / Voltage, i.e., data is sent to external output circuits. On the other hand, when the memory array array block 200 is selected, the isolation gate circuit 400 is turned off, and the separation gate circuit 800 is turned on so that the memory sense array block 200 of the memory sense array block 200, the N-type sense amplifier 700, and the input / output circuit 600 are connected to each other. Bit line pairs BL / BLB are connected. The operation principle thereafter is the same as the above-described operations. Accordingly, it can be seen that the type sense amplifier 500 and the N type sense amplifier 700 are shared by the memory array array blocks 100 and 200 adjacent to each other. Here, the shared sense amplifier 500 and the N-type sense amplifier 700 sense and amplify the data of the bit line pair for the selected one of the adjacent memory array array blocks 100 and 200. Accordingly, since the same sensing effect must be provided for the left and right memory array array blocks 100,200, the bit of the selected memory array array block in the sense sense amplifier 500 and the N sense amplifier 700, regardless of whether the left or right memory array array block is selected. The loading of the line pair BL / BLB should be even. In other words, the sensed amplifier 500 and the n-type sense amplifier 700 should have a symmetrical structure with the adjacent memory array array blocks 100 and 200. However, I / O line pair IO / in random access memory I / O circuit Symmetry of the sensed amplifier 500 and the N-type sense amplifier 700 when the random access memory input / output circuit and the serial access memory and the serial access memory input / output circuits are shared, and an extension of the serial access memory input / output circuit area is required. Of the device characteristics such as the sensing speed of the bit line pair BL / BLB and the sensed amplifier 500 and the n-type sense amplifier 700 are located at both sides of the input / output circuit 600. Since the loading is different from the length of the wire, it causes a problem of not being able to sense evenly. In addition, a split gate control circuit for outputting the split gate control signals PIISOL and PIISOR for controlling the split gate circuits 400 and 800 by the sensing enable signal PIS and the row address signals RA and RAB generated in an external system is shared in a memory array array block. The bit line pair BL / BLB of the type, n-type sense amplifier 500,700 and the input / output circuit 600 are connected to the memory array array blocks 100,200, and the charge sharing between the memory pin and the bit line is increased due to an increase in the length of the bit line pair BL / BLB. (Charge sharing) There is a problem that the voltage supply is reduced and the sensing speed of the bit line is lowered.

Accordingly, an object of the present invention is to separately arrange the P and N sense amplifiers facing each other in individual memory array array blocks to equalize the load applied to the pair of bit lines, thereby increasing the I / O line and increasing the area of the I / O circuit. It is to provide a core circuit structure that can make the sensing speed uniform.

Another object of the present invention is to improve the circuit for controlling the separation gate circuit between the memory array block, the sensing enable signal and the row address signal as an input to generate a separate gate control signal of different logic signals at the same time the memory It provides improved charge sharing voltage and improved bit line sensing speed between pin and bit line.

In order to achieve the above object, the present invention provides a plurality of pairs of bit lines connected between a plurality of memory array arrays including at least one memory array and memory arrays in a neighboring memory array array block. A semiconductor memory device comprising: a plurality of equalization circuits located between adjacent memory array array blocks and connected to the bit line pairs to input a predetermined control signal to match the bit line pairs to the same voltage level; A sense amplification circuit comprising a sense sense amplifier and an n sense amplifier, respectively, located between the equalization circuits and connected between the bit line pairs and adjacent to the memory array array block; The bit line by inputting a predetermined control signal And a plurality of separation gate circuits connected to the pair, and a column selection gate positioned between the separation gate circuits and connected to the bit line pair and the input / output line pair to drive the column selection signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a specific circuit diagram of a core circuit according to the present invention. 3 is an operation timing diagram of the core circuit according to the present invention. 2 will be described with reference to FIG.

Referring to the configuration of FIG. 2, the word line 70, 80 and the bit line pair BL / BLB, the gate line are connected to the word line 70, 80, the drain is connected to the bit line BL, and the source is connected to the capacitors 2 and 4 A memory array consisting of the capacitors 2 and 4 having one side connected to the transistors 1 and 3 and the internal power supply voltage 40 and the other side connected to the enMOS transistors 1 and 3, and a memory array array consisting of a plurality of the memory arrays. An equalization circuit 300 formed on the right side of the memory array array 100 and connected between the bit line pairs BL / BLB and composed of enMOS transistors 5, 7, and 9; One end is connected to each of the bit line pairs BL / BLB, and the other end is connected to the interconnected node of the PMOS transistors 15 and 17 and the interconnected node of the PMOS transistors 15 and 17. A sense amplifier 500 consisting of a pense transistor 19 connected to the power supply voltage terminal and having a latched structure, and an n-type sense amplifier consisting of enmos transistors 25, 27, and 29 formed of the same latch structure as the above described sense amplifier. And an NMOS transistor 11 and an NMOS transistor 13 connected to each other by a gate thereof located on the right side of the sense amplifier 500, and a drain and a source of each of the NMOS transistors 11 and 13 connected to the bit lines BL and BLB, respectively. A column select gate composed of a gate circuit 400, an NMOS transistors 21 and 23 positioned on the right side of the separation gate circuit 400 and connected to the bit line pair BL / BLB, respectively, and an input / output line pair connected to the enMOS transistors 21 and 23, respectively. IO / The circuit configuration of the input / output circuit 600 and the circuitry of the memory array array block 200 based on the input / output circuit 600, that is, the separation gate circuit 800, the sense amplifier 700, and the equalization circuit 900 of the memory array array block 100 side are described. Same as the circuit configuration and the layout is completely symmetrical. The operation of FIG. 2 will be described with reference to FIG. The operations of the memory chips of the memory array arrays 100 and 200, the operations of the sense amplifiers 500 and 700, the operations of the isolation gate circuits 400 and 800 and the input / output circuit 600 are the same as described above with reference to FIG. 1. Here, assuming that the memory V array block 100 is selected and the memory V array block 200 is not selected, the bit line pairs are turned on by turning on transistors 31 and 33 of the isolation gate circuit 800 on the side of the memory V array block 200 which are not selected. Precharge and equalize BL / BLB, and in the selected memory array array block 100, transistors 11 and 13 of the isolation gate circuit 400 on the memory array array block 100 side are turned on to precharge the bit line pair BL / BLB. Aji and equalize. This represents interval 1 in FIG. In the memory sharing between the memory array data of the memory array array 100 and the bit line, the transistors 31 and 33 of the isolation gate circuit 800 of the memory array array 200 are turned off, and then the memory array array 100 of the memory array array 100 is turned off. The transistors 11 and 13 of the isolation gate circuit 400 are turned off. That is, the loading of the bit line pair BL / BLB from the separation gate circuit 400 to the separation gate circuit 800 is removed. The word line is then enabled to improve the charge sharing voltage as shown in section 2 of FIG. In addition, during bit line initial sensing, transistors 11 and 13 of the isolation gate circuit 400 are turned off to remove the loading of the bit line pair BL / BLB from the isolation gate circuit 400 to the isolation gate circuit 800 to perform initial bit line sensing. Do it quickly. This is represented by interval 3 in FIG. When the bit line initial sensing is performed as desired, the transistors 11 and 13 of the isolation gate circuit 400 are turned on to improve the bit line voltage. The bit line pair IO.BL / IO of the input / output 600 between the two separation gate circuits 400 and 800. Send to .BLB This is represented by interval 4 in FIG. Therefore, the loading of the bit line pair BL / BLB that the sense amplifier sees at the time of bit line sensing is always the same regardless of whether the memory V array block 100 or the memory V array block 200 is selected. Therefore, since the sense amplifiers are independently included in the bit line pair BL / BLB for each memory array array block, the length of the bit line pair BL / BLB is shortened, thereby reducing the loading of the bit line pair BL / BLB.

4 is a specific circuit diagram of a separation gate control circuit according to the present invention. Looking at the configuration of Figure 4 as follows. The sensing enable control signal PIS generated from the external control signal generator is input to the second NOR gate 5 as one signal, and the row address signal pairs RA and RAB are input to the first NOR gate 3. The first NOR gate 3 and the second NOR gate 5 are connected in series, the second NOR gate 5 is connected to the first inverter 7, and the first inverter 7 is connected to one input terminal of the first NAND gate 15. One of the row address signals, RAB, is input to an input terminal of an inverter chain 9 connected in parallel with a first NOR gate 3 and a signal output from the inverter chain 9 is input to another input terminal of the first NAND gate 15. . The output signal of the first NAND gate 15 is input to an input terminal of the second inverter 17. The separation gate driving signal PIISOL which is an output signal of the second inverter 17 is input to the left separation gate circuit. Meanwhile, in another identical circuit, the sensing enable control signal PIS and the row address signal pair RA and RAB are input to the separation gate control circuit and are input to an input terminal of the inverter chain 29 having the same configuration as the inverter chain 9. Becomes RA. The other configuration is composed of Noah gates 23 and 25, NAND gate 35 and inverters 27 and 37, and is the same as the configuration of the above-described circuit. The split gate drive signal PIISOR, which is an output signal from the inverter 37, is also input to the right split gate circuit. Here, according to the sensing enable control signal PIS and the row address signal pair RA, RAB, the PIISOL and PIISOR have different waveforms as shown in FIG. 3. Accordingly, the two separation gate circuits can be controlled by the two separation gate control signals. By having the above-described improved configuration, it is possible to improve the charge sharing voltage between the memory 쎌 and the bit line, to sense more reliably, and to increase the bit line sensing speed.

Although the present invention has been described with reference to the drawings, for example, it is apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (5)

A semiconductor memory device comprising a plurality of memory array array blocks including one or more memory arrays, and a plurality of bit line pairs connected between memory arrays in the memory array array block and the memory array array block. A plurality of equalization circuits located between the memory array array blocks and connected to the bit line pairs to input a predetermined control signal to match the bit line pairs to the same voltage level, and are located between the equalization circuits. A pair of bit lines connected between bit line pairs adjacent to each other between the memory array array blocks and a sense amplifier circuit comprising a sense sense amplifier and an n-type sense amplifier, and positioned between the sense amplifier circuits and inputting a predetermined control signal to the bit line pair. A plurality of separation gate circuits connected to the phase And a column select gate positioned between the separate gate circuits and connected to the bit line pair and the input / output line pair to receive and drive a column select signal. 2. The semiconductor memory device according to claim 1, wherein the separation gate circuit is composed of two NMOS transistors whose gates are interconnected. A semiconductor memory device having a plurality of memory array array blocks including one or more memory arrays and a plurality of bit line pairs connected between the memory array arrays and the memory arrays in a neighboring memory array array block. A plurality of equalization circuits located between the memory array array blocks and connected to the bit line pairs to input a predetermined control signal to match the bit line pairs to the same voltage level, and are located between the equalization circuits. A sense amplification circuit comprising a sense sense amplifier and an n-type sense amplifier respectively connected between the memory array array blocks adjacent to the line pair, and located between the sense amplifier circuits and inputting a predetermined control signal to the bit line pair. A plurality of connected isolation gate circuits, The enable signal and the separation gate control circuit for a semiconductor memory device characterized in that it includes a by the address signal as inputs for generating a control signal of the isolation gate circuit. 4. The control signal of the isolation gate circuitry of claim 3, wherein the control signal of the isolation gate circuitry turns off the corresponding isolation gate circuitry before the word line of the memory array array block corresponding to the address signal is enabled, and the sensing signal is enabled. And turn on the isolation gate circuit. 5. The separation gate control circuit according to any one of claims 3 to 4, wherein the separation gate control circuit comprises: first logic means for inputting the address signal, second logic means for inputting the sensing enable signal, and the address signal. And third logic means for delaying, and fourth logic means for inputting outputs of the first and second logic means and outputs of the third logic means.