KR0162339B1 - Aspect ratio converter - Google Patents

Abstract

The present invention relates to a screen aspect ratio converting apparatus, which is configured to display an aspect ratio of a screen by changing the aspect ratio of the screen to 4: 3 through pixel compression and line interpolation in a wide TV having an aspect ratio of 16: 9.

The present invention as described above has scanning line processing means for generating a write / read signal and a different selection control signal with an input horizontal synchronization signal; Data storage means for storing and outputting the input image data in alternating order according to the first selection control signal and the recording / reading signal of the scanning line processing means; Line interpolation means for multiplying coefficient values by respective video data obtained by this data storage means; Line selection means for sequentially selecting and outputting each of the image data obtained by the line interpolation and the image data obtained from the data storage means in accordance with the second selection control signal of the scanning line processing means; Data summing means for summing and outputting the two selected image data; Horizontal synchronous counter means for counting a start portion of said horizontal synchronous signal to generate a write enable signal; Field memory means for storing and outputting image data zoomed out of the data summing means 3: 4 by field by the write enable signal of the horizontal synchronous counter means; It is achieved by configuring.

Description

Screen aspect ratio inverter

1 is a conventional 16; 9 Schematic of the Injector Inverter on a Widescreen TV.

FIG. 2 is a diagram showing a state in which a 4: 3 broadcast signal according to FIG. 1 is displayed in a zoom mode on a 16: 9 screen.

(a) is a figure showing a screen state of 4: 3 ratio,

(b) shows a state in which a 4: 3 broadcast signal is extended to a 16: 9 screen.

3 is an exemplary view showing a scan line input / output relationship according to FIG.

4 is an exemplary view showing an expanded state of the injection athlete according to FIG.

5 is a block diagram of a 3: 4 line interpolation processing apparatus for a video signal according to the present invention.

6 is a block diagram of a 4: 3 pixel compression processing apparatus for a video signal according to the present invention.

7 is a flowchart illustrating operations of the first and second first-in, first-out parts according to FIG.

(a) is a write / read order and coefficient change flowchart of the first-in first-out part,

(b) is a write / read order and coefficient change flowchart of the first-in first-out part.

FIG. 8 is a state diagram of video signal change by the horizontal compression process of FIG.

(a) is an input digital video signal,

(b) shows the compressed shape of the actual video section.

(c) shows a video signal with a side panel inserted.

9 is a configuration diagram of another embodiment of a 3: 4 line interpolation processing apparatus for a video signal according to the present invention.

10 is a configuration diagram of another embodiment of a 4: 3 pixel compression processing apparatus for video signals according to the present invention.

FIG. 11 is a diagram illustrating a screen change state according to FIGS. 5 and 9.

(a) is a screen state diagram displayed without changing the aspect ratio,

(b) shows the screen state when there is a change in aspect ratio through line interpolation.

FIG. 12 is a diagram illustrating a screen change state according to FIGS. 6 and 10.

(a) is a screen state diagram displayed without changing the aspect ratio,

(b) is a screen state diagram when there is a change in aspect ratio through pixel compression.

* Explanation of symbols for main parts of the drawings

202: scanning line processing unit 203: first data storage unit

204: first line interpolator 205: first line selector

206: first data summing unit 207: horizontal synchronous counter unit

402: pixel compression control unit 403: second data storage unit

404: pixel compression unit 405: third data storage unit

406: switching unit 410: luminance level selection unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to screen aspect ratio conversion in television receivers, and more particularly, to display broadcast signals in a 4: 3 ratio by varying the scanning player of a screen in a wide screen television receiver having a 16: 9 aspect ratio. It relates to a screen aspect ratio converter.

In general, in the NTSC broadcasting system and the PAL broadcasting system, the letter box type is black and the upper and lower sides of the screen with 3/4 of the original active video section as the low pass image, that is, letter box type. The video will be transmitted.

This is to transmit an image having a 16: 9 aspect ratio such as a movie without distortion of the screen in a television receiver having an aspect ratio of 4: 3.

However, the development of a wide television receiver having an aspect ratio of 16: 9 has led to the necessity of displaying a 4: 3 video signal on all screens of the wide television receiver.

Therefore, in accordance with the spread of wide television receivers, each broadcasting station mixes 4: 3 programs and 16: 9 programs for revolving television sets having aspect ratios of 4: 3 and wide television sets having aspect ratios of 16: 9. Is increasing.

In addition, the receiver detects a wide screen signal (WSS) indicating whether the program transmitted from the broadcasting station is a 4: 3 program or a 16: 9 program, and automatically expands the screen of the wide television receiver. Was born.

However, at this time, in order to receive and watch a 4: 3 program transmitted from the broadcasting station by using a 16: 9 wide television receiver, it is possible to watch by changing the scanning player of the screen.

As described above, a conventional scanning player converting apparatus for displaying a 4: 3 video signal on a 16: 9 wide television receiver has 4 input through the input terminal 100, as shown in FIG. A field memory section 101 for sequentially storing three digital video signals DCV in accordance with the aspect ratio of the screen and outputting the stored video data one line per horizontal scanning period; A first line memory unit 102 for storing image data stored in the field memory unit 101 every line; A second line memory section 103 for line storing the previous image data stored in the first line memory section 102; A first multiplier (104) for receiving and multiplying a predetermined coefficient value (1-k) from the coefficient input terminal (106) by the image data input line by line from the first line memory section (102); A second multiplier 105 for multiplying and receiving a predetermined coefficient value k from the coefficient input terminal 106 to video data delayed by one line from the second line memory section 103; A summator 107 configured to add the current image data obtained from the first and second multiplications 104 and 105 and the previous image data to output the converted image signal through the output terminal 108. It is.

The scanning player converting apparatus for viewing in a zoom mode by 4/3 times the number of lines in a widescreen television receiver having an aspect ratio of 16: 9 of the conventional screen configured as described above, first through the hysteresis terminal 100. When the digital video signal (DVC) of 3 is input, the field memory unit 101 sequentially stores the 4: 3 digital video signal inputted to match the aspect ratio of the screen in every field, that is, skips one by three lines. Will be saved.

This leaves the fourth line blank because it must make three lines four.

The field memory unit 101 supplies one line to the first line memory unit 102 every horizontal scanning period.

The first line memory unit 102 sequentially stores the digital image data input by skipping one line every three lines from the field memory unit 101, and then uses the stored image data as four lines again. The memory unit 103 and the first multiplier 104 are provided.

The second line memory unit 103 delays the image data input from the first line memory unit 102 by one line and provides it to the second multiplier 105.

The first and second multipliers 104 and 105 may determine a predetermined coefficient value (1-K) input from the coefficient input terminal 106 to image data input from the first and second line memory units 102 and 103. ) And multiply each K and provide the result to the summer 107.

The summer 107 sums the image data inputted from the first and second multipliers 104 and 105 and outputs the image data having the new scan lines obtained by the summation through the output terminal 108 to output the image data. A 4: 3 video signal as shown in (a) is displayed on the entire vertical side of the 16: 9 screen as shown in (b) of FIG. 2 by scanning line interpolation.

3 and 4, the first multiplier 104 multiplies the image data input from the first line memory unit 102 by a coefficient value of 1-K. The second multiplier 105 multiplies the image data input from the second line memory unit 103 by the coefficient value of K.

The image data multiplied by the first and second multipliers 104 and 105 are added through the summer 107 to generate a new scan line.

That is, as an example, as shown in FIG. 3, a scanning line C of one line of image data output from the first line memory unit 102, and a scanning line of one line of image data output from the second line memory unit 103 is shown. If the coefficient value K input from the coefficient input terminal 106 is 1 in the state where B is assumed to be 1, the first multiplier 104 adds 1 to the image data C inputted from the first line memory unit 102. By multiplying -K = 0, its output becomes zero, and the second multiplier 105 multiplies the image data B input from the second line memory section 103 by K = 1 At the output, the scan line B of the image data B is output as it is and input to the summer 107.

The summer 107 adds the scan lines of the two image data input from the first and second multipliers 104 and 105 to output the scan line b of the new image data through the output terminal 108.

In this manner, as shown in FIG. 3, four new image data scanning lines b, C1, C2 and d1 are made with three scanning lines B, C and D of the input image data.

After that, even if one horizontal period has elapsed, the output of the field memory unit 101 is lost.

As shown in FIG. 4, the scanning line B of the image data of the second line memory section 103 and the scanning line C of the image data of the first line memory section 102 are used to make four scanning lines with three scanning lines. ) Needs to be used once more, so that the output of the field memory unit 101 at this time does not enter any signal into the first line memory unit 102 as indicated by zero.

However, the coefficient value K from the coefficient input terminal 106 is changed to 1/4 and input to the second multiplier 105, and the coefficient value 1-K is changed to 3/4 so that the first multiplier 104 is changed. ), The first multiplier 104 multiplies the scanning line C of the image data input from the first line memory unit 102 by the input coefficient value 3/4, and provides the multiplier 107 to the summer 107. The second multiplier 105 multiplies the scan line B of the image data input from the second line memory unit 103 by the coefficient value 1/4 to provide it to the summer 107.

Accordingly, the summer 107 adds the scan lines of the two image data obtained from the first and second multipliers 104 and 105 to generate the scan line C1 of the new image data, and then outputs the output terminal 108. Will output via

In the next horizontal period, as shown in FIGS. 3 and 4, the coefficient value K from the coefficient input terminal 106 is changed to 1/2 and input to the second multiplier 105, and the coefficient When the value 1-K is changed to 1/2 and input to the first multiplier 104, the first multiplier 104 is input to the scan line D of the image data input from the first line memory unit 102. The multiplier 107 is multiplied and provided to the adder 107, and the second multiplier 105 multiplies the scan value C by the coefficient value 1/2 by the scan line C of the image data input from the second line memory unit 103. The summer 107 is provided.

The summer 107 sums the scan lines of the two image data input from the first and second multipliers 104 and 105 in the same manner as mentioned above to generate the scan line C2 of the new image data and outputs the scan line C2. And output via 108.

The coefficient values input to the coefficient input terminal 106 are K = 1, 1/4, 1/2, 3/4, 1. -----, and 1-K = 0, 3/4, 1 / 2, 1/4, 0, ----,

Since the sum of the coefficients multiplied by the output signals of the first and second line memory units 102 and 103 in the first and second multipliers 104 and 105 is always 1, there is no change in the video signal.

In this way, three scanning lines are formed into four scanning lines and displayed on the screen. As a result, 3/4 of the signals are vertically interpolated to the vertical side of the 4: 3 image signal as shown in FIG. ) Is displayed on the entire vertical side of the screen.

However, the conventional player for converting the scanning player in the 16: 9 wide television receiver is stored in the field memory from the horizontal line necessary in the zoom mode, and zooms only the corresponding part, thereby requiring a double screen that requires the entire screen. There is a problem that it is difficult to perform the freeze function because it cannot have a double window function and signal processing is performed after the field memory.

Accordingly, an object of the present invention, in view of such a conventional problem, in the wide television receiver having an aspect ratio of 216: 9 through the line interpolation method to extend the aspect ratio of the screen to the ratio of 4: 3 and to extend the 16: 9 range Remove more than 16; A screen aspect ratio converting apparatus for displaying a 4: 3 ratio broadcast signal on a screen of 9 is provided.

It is still another object of the present invention to display a wide aspect ratio of a screen by changing the aspect ratio of the screen to 4: 3 through a pixel compression method in a wide television receiver having an aspect ratio of 16: 9.

Still another object of the present invention is to perform a zoom function and a horizontal compression function using the above line interpolation method and pixel compression method, and to process and store signal processing before the field memory and store the image stored in the field memory. It is also possible to perform the stop and dual screen functions depending on the signal reading method.

The screen aspect ratio converting apparatus of the present invention for achieving the above object comprises a scanning line processing means for generating a recording / reading signal and a different selection control signal with an input horizontal synchronization signal to generate three horizontal scanning lines of four lines; ; Data storage means for storing and outputting the input digital image data in alternating order for three lines according to the selection control signal and the recording / reading signal generated by the scanning line processing means; Line interpolation means for multiplying and outputting coefficient values differently set to respective image data for the current and subsequent three lines obtained by the data storage means; Line selection means for sequentially selecting each image data obtained by interpolation in the line interpolation means and image data obtained in the data storage means sequentially for each line according to the selection control signal of the scanning line processing means and outputting different values; Data summing means for summing and outputting two different image data obtained by said line selecting means; Horizontal synchronous counter means for counting the start of the horizontal synchronous signal to be zoomed and generating a write enable signal when the horizontal synchronous signal reaches the zooming interval; And field memory means for storing and outputting image data zoomed out from the data summing means in units of fields by the write enable signal of the horizontal synchronous counter means.

Still another aspect aspect conversion device for achieving the object of the present invention comprises: pixel compression control means for generating different selection control signals and write enable signals with horizontal synchronization signals input for horizontal compression; Third data storage means for storing and outputting the image data input by the selection control signal obtained by the pixel compression control means in every pixel alternately; Pixel compression means for combining the image data obtained by the third data storage means into three pixels by combining them into three pixels and selectively outputting the image data according to a selection control signal of the pixel compression control means; Fourth data storage means for storing and outputting pixel data obtained by said pixel compression means in alternating order in accordance with a write enable signal of the pixel compression control means; Selection control of the pixel compression control means controls the luminance level value of the side panel which is preset and selected by sensing the average pixel level or the average beam current level from the outside to the pixel data alternately input from the fourth data storage means. Side panel inserting means for inserting and outputting the signal according to a signal; And a field memory means for storing the video signal into which the side panel is inserted from the side panel inserting means for each field and outputting a horizontally compressed digital video signal.

Hereinafter, described in detail with reference to the accompanying drawings of the present invention.

5 shows three of the video signals according to the present invention; As a configuration diagram of a four-line interpolation processing apparatus, as shown therein, a recording / reading signal has a horizontal synchronizing signal Hsy input through the synchronization input terminal 200 to generate three horizontal scanning lines as four lines. A first scan line processing unit 202 which generates and outputs (WR / RD) and different first and second selection control signals S1 and S2; The digital image data input through the image input terminal 201 according to the first selection control signal S1 and the write / read signal WR / RD generated by the first scan line processor 202 are respectively provided for three lines. A first data storage unit 203 for alternately storing and outputting the first-in first-out unit 203a and the second-in first-out unit 203b which are line memories; A first line beam that multiplies and outputs coefficient values differently set to respective image data for two lines input from the first and second first-in, first-out units 203a and 203b of the first data storage unit 203. Cadre 204; Each of the image data obtained by interpolation by the first line interpolation unit 204 and the image data directly input by the first data storage unit 203 are selected by the second scanning line processing unit 202. A first line selector 205 for sequentially selecting every line according to the control signal S2 and outputting different values; A first data adder 206 for summing and outputting two different image data selected by the first line selector 205; A first horizontal synchronization counter unit 207 for counting the beginning of the horizontal synchronization signal Hsy to zoom and generating a write enable signal WE when the horizontal synchronization signal reaches the zooming section; The output terminal stores the image data zoomed out 3: 3 from the first data summing unit 206 in every field by the write enable signal WE generated by the first horizontal synchronous counter unit 207. A first field memory unit 208 outputs through 209.

In the above description, the first scan line processing unit 202 may include the first and second first-in, first-out (first, first-out) units of the first data storage unit 203 whenever the horizontal synchronization signal Hsy input through the synchronization input terminal 200 is input. A first clock generator 202b for generating a write signal WR to 203a and 203b; A second body which multiplies the recording signal WR generated by the first clock generator 202b by 4/3 to generate the read signal RD at the first and second first-in, first-out 203a and 203b. Distribution 202e; A first multiplier (202c) for multiplying the horizontal synchronous signal (Hsy) input through the synchronous input terminal (200) by 4/3; The horizontal synchronization signal multiplied by the first multiplier 202c is counted to generate a second 3-bit selection control signal S2, and is cleared when the vertical synchronization signal Vsy from the synchronization input terminal 202g is input. A first module counter unit 202d; A first counter unit 202a which divides the horizontal synchronous signal Hsy input through the synchronous input terminal 200 into two and generates a first selection control signal S1; The digital image data input through the image input terminal 201 is alternately switched by the first selection control signal S1 divided and input by the first counter unit 202a to alternately convert the digital image data. It consists of the 1st switching part 202f provided to the 1st, 2nd first-in, first-out part 203a, 203b.

The first line interpolator 204 may include: a first multiplier 204a multiplying 1/4 of the image data input from the first first-in, first-out unit 203a of the first data storage unit 203; A second multiplier 204b that multiplies two quarters of the image data input from the first first-in, first-out 203a; A third multiplier 204c for multiplying 3/4 of the image data input from the first first-in, first-out 203a; And fourth to sixth multipliers 204d to 204f that multiply coefficient values of 3/4, 2/4, and 1/4 by the image data input from the second first-in, first-out 203b.

In addition, the second line selector 205 may include 1-bit image data input from the first-in first-out unit 203a of the first data storage unit 203 and the first line interpolator 204. Two-bit second selection control signal S2 generated by the first module counter unit 202d and the image data input by two bits, respectively, from the first to third multipliers 204a to 204c. A first multiplexing unit 205a, which is sequentially selected by the step S) and provided to the second data summing unit 206; 1-bit image data input from the second first-in first-out 203b of the first data storage unit 203 and the fourth to sixth multipliers 204d to 204f of the first line interpolation unit 204, respectively. Image data inputted by two bits and its own 1-bit ground potential are sequentially selected by the 2-bit second selection control signal S2 generated by the first module counter unit 202d, and the data summing unit 206. It consists of a 2nd multiplexing part 205b provided to ().

9 is a diagram illustrating another embodiment of a 3: 4 line interpolation processing apparatus of an image signal according to the present invention. As shown in FIG. 9, the synchronization input terminal 300 is used to generate 3 lines of horizontal scan lines as 4 lines. The second scan line processing unit 302 which generates and outputs the write / read signal WR / RD and different first and second selection control signals S1 and S2 with the horizontal synchronization signal Hsy input through the second signal. Wow ; The digital image data input through the image input terminal 301 according to the first selection control signal S1 and the write / read signal WR / RD generated by the second scan line processor 302 for each of three lines, respectively. The second data storage unit 303 which stores alternately the third to fifth first-in first-out units 303a to 303c every line and divides and outputs the image data for the stored three lines in two lines. )Wow ; A second line multiplying image values of two different lines input from the third to fifth first-in first-out units 303a to 303c of the second data storage unit 303 by multiplying coefficient values set differently. Interpolation unit 304; A second data summing unit 305 for summing two different pairs of image data obtained by interpolation in the second line interpolation unit 304 and outputting three lines of image data; Image data of three lines obtained by the second data summing unit 305 and image data of one line of the third first-in first-out unit 303a are generated by the second scanning line processing unit 302. A second line selector 306 sequentially selecting and outputting every line according to the selection control signal S2; A second horizontal synchronization counter unit 307 for counting the start of the horizontal synchronization signal Hsy to zoom and generating a write enable signal WE when the horizontal synchronization signal reaches the zooming section; The output terminal stores the image data zoomed out from the second line selection unit 306 by 3: 4 by the write enable signal WE generated by the second horizontal synchronization counter unit 307 in every field. A second field memory unit 308 outputs through 309 is configured.

In the above, the second scanning line processing unit 302 is the third to fifth first-in first-out 303a to the second data storage unit 303 whenever the horizontal synchronization signal Hsy is input through the synchronization input terminal 300. A second clock generator 302b for generating a write signal WR to 303c; A fourth multiplier that multiplies the recording signal WR generated by the second clock generator 302b by 4/3 to generate the read signal RD in the third to fifth first-in, first-out 303a to 303c. 302e and; A third multiplier 302c multiplying the horizontal synchronous signal Hsy input through the synchronous input terminal 300 by 4/3; The second synchronization unit 302c generates a 2-bit selection control signal S2 by counting the horizontal synchronization signal multiplied by the third multiplier 302c and is cleared when the vertical synchronization signal Vsy is input from the synchronization input terminal 302g. 2 module counter section 302d; A second counter unit 302a for counting a horizontal synchronization signal Hsy input through the synchronization input terminal 300 and generating a first selection control signal S1 with a number from 0 to 2; The second data storage unit 303 alternately switches digital image data input through the image input terminal 301 in three directions by the first selection control signal S1 generated by the second counter unit 302a. The second switching unit 302f is provided to the third to fifth first-in, first-out units 303a to 303c of the controller.

The second line interpolator 304 is a seventh and twelfth multiplier 304a that multiplies one-quarter of the image data input from the third first-in first-out part 303a of the second data storage means 303. 304f and; Eighth and ninth multipliers 304b and 304c multiplying 3/4 and 2/4 by the image data input from the fourth first-in first-out 303b; And a tenth and eleventh multipliers 304b and 304e that multiply the image data input from the fifth first-in first-out 303c by 2/4 and 3/4, respectively.

The second data summing unit 305 is a first adder 305a which adds and outputs two different pairs of image data which are multiplied by the seventh and eighth multipliers 304a and 304b respectively. ; A second adder (305b) for adding and outputting two different pairs of image data multiplied by the ninth and tenth multipliers (304c, 304d), respectively; And a third adder 305c which adds and outputs two different pairs of video data which are respectively multiplied by the eleventh and twelfth multipliers 304e and 304f.

A three-to-four line interpolation processing apparatus of a video signal according to the present invention of FIG. 5 in the screen aspect ratio converting apparatus of the present invention configured as described above will be described with reference to FIGS.

Here, the 3: 4 line interpolation is a process of making the 3 lines of the horizontal scan line into 4 lines. First, when the horizontal synchronous signal Hsy is input through the synchronization input terminal 200, the first scanning line processor 202 is horizontal as described above. In order to make three scanning lines into four lines, the input horizontal synchronization signal Hsy is multiplied, divided, and counted to perform a write signal WR, a read signal RD, and two different first and second pairs. 2, the selection control signal S1 (S2) is generated.

That is, the first scan line processing unit 202 includes a first counter unit 202a, a first clock generator 202b, first and second multiplication units 202c and 202e, and a first module counter unit 202d. And a first switching unit 202f.

The first clock generator 202b generates a clock, that is, a write signal WR every time the horizontal synchronous signal Hsy is input through the synchronous input terminal 200, so that the first data storage 203 is a line memory. To the first and second first-in, first-out (203a) and 203b, and the second multiplier (202e) provides 4/3 of the write signal (WR) generated by the first clock generator (202b). The multiplication is performed to provide the read signal RD to the first and second first-in, first-out 203a and 203b.

In addition, the first multiplier 202c multiplies the horizontal synchronous signal Hsy input through the synchronous input terminal 200 by 4/3 for each line to provide the first module counter 202d. The first module counter unit 202d multiplies 4/3 to make the horizontal synchronous signal input to the second synchronization control signal by setting the number from 0 to 7 every 3 lines to make the selection control signal every line. (S2) is generated, and is cleared every field by the vertical synchronization signal Vsy input to the synchronization input terminal 202g.

On the other hand, the first counter unit 202a of the first scan line processing unit 202 divides the input horizontal synchronization signal Hsy by half to divide the first selection control signal S1 into the first switching unit 202f. To be provided.

At this time, when the digital image data is input through the image input terminal 201, the first switching unit 202f is switched every line by the first selection control signal S1 of the first counter unit 202a. The input digital image data is alternately inputted to the first first-in first-out 203a and the second first-in first-out 203b of the first data storage unit 203.

The first and second first-in, first-out 203a and 203b of the first data storage unit 203 are generated by the first clock generator 202b and input by the write signal WR. The image data input through 202f are stored in alternating order.

In other words, the first three lines are stored in the order of first first-in first-out 203a, second first-in first-out 203b, and first first-in first-out 203a.

However, subsequent three lines are stored in the second first-in first-out 203b, the first first-in first-out 203a, and the second first-in first-out 203b.

Referring to FIG. 7, it is assumed that image data of the first three lines is A, B, and C, and that image data of three subsequent lines is D, E, and F. As shown in (a) and (b) of FIG. 7, the image data A for the first line in the image data for the first three lines is transferred to the first first-in, first-out 203a of the first data storage unit 203. The image data B for the second line is sent to the second first-in first-out 203b, and the image data C for the third line is sent to the first first-in first-out 203a. And by the recording signal WR.

Then, the image data D for the first line is the first-in first-out unit 203b, and the image data E for the second line is the first-in first-out unit 203a. ), The image data F for the third line is stored in the second first-in first-out part 203b by the first selection control signal S1 and the recording signal WR.

The image data for the three lines stored in the first and second first-in first-out parts 203a and 203b, which are the line memories, are 4/3 times the frequency of the recording signal WR provided from the second multiplier 202e. The read signal RD is read and provided to the first line interpolation unit 204 as shown in Figs. 7A and 7B.

That is, when the image data is recorded in one of the first and second first-in, first-out 203a and 203b by the first clock generator 202b, the first data generator 202b records the first data in the first-in first-out unit. The video data is AA, BB, and B as shown in (a) and (b) of FIG. 7 by the read signal RD which is 4/3 times the frequency of the recording signal WR input from the second multiplier 202e. It is read as CC, DD, EE, and FF because it is necessary to use image data A to F once again for the current and subsequent three lines to make the three horizontal scan lines into four lines.

Subsequently, the first line interpolator 204 is outputted from the first and second first-in, first-out 203a and 203b of the first data storage 203 to make three lines into four lines. Multiply the four coefficients (K) set in the image data for each of the three lines of K. The four coefficients (K) are K = 1, 1/4, 2/4, 3/4, , 1-k = 0, 3/4, 2/4, 1/4.

Accordingly, the first to third multipliers 204a to 204c of the first line interpolator 204 may be separated from the first first-in first-out part 203a of the first data storage unit 203 in FIG. Similarly, the first data selection unit is loaded with coefficients K, 1/4, 2/4, and 3/4 of the image data A, C, E, A, etc., which are read and input every line. The first multiplexer 205a of 205 is inputted, and the fourth to sixth multipliers 204d to 204f are each line from the second first-in, first-out 203b as shown in FIG. The first data selection unit 205 by multiplying the coefficient (1-K) values 3/4, 2/4, and 1/4 by the read and input image data (B) (D) (F) (B) --- and so on. Input to the second multiplexer 205b.

The first multiplexer 205a of the first data selector 205 is connected to a 3 bit second select control signal S2 input from the first module counter 202d of the first scan line processor 202. As a result, the image data of the first first-in first-out unit 203 and the image data multiplied by the first to third multipliers 204a to 204c and their ground potentials are selected and output for each line, and the second multiplexer 205b The first data summing unit 206 selects the image data multiplied by the second first-in first-out unit 203b, the image data multiplied by the fourth to sixth multipliers 204d to 204f, and its ground potential every line. To be provided.

That is, the detailed description will be made with reference to FIG. 7. First, when the second selection control signal S2 output as 3 bits from the first module counter unit 202d is input to 0 for the first 3 lines, the first multiplexing is performed. The unit 205a selects the image data A output from the first-in, first-out unit 203a and provides it to the first data summing unit 206, as shown in FIG. The unit 205b selects the ground potential, ie, 0, and provides it to the data summing unit 206, as shown in FIG. 7 (b).

When the second selection control signal S2 is input as 1, the first multiplexer 205a selects the image data A multiplied by 1/4 from the first multiplier 204a, and the second multiplexer 205b selects the image data B multiplied by 3/4 from the fourth multiplier 204d, and if the second selection control signal S2 is input as 10, the first multiplexer 205a selects the second multiplier. In step 204b, the image data C multiplied by 2/4 is selected, and the second multiplexer 205b selects the image data B multiplied by 2/4 in the fifth multiplier 204e. When the second selection control signal S2 is input as 11, the first multiplexer 205a selects the image data C multiplied by 3/4 in the third multiplier 204c, and the second multiplexer 205b The original image data input by the second first-in first-out 203b is selected and output.

In this way, when the 3 bit second selection control signal S2 _ generated from the first module counter unit 202d is sequentially input to 100, 101, 110, and 111, the first multiple call unit 205a is grounded. The original image of the potential, the image data E multiplied by 3/4, the image data E multiplied by 2/4, the image data A multiplied by 1/4, and the original image of the second first-in, first-out 203a. The data A is selected for each line, and the second multiplexer 205b uses the same method as the original image data D of the second first-in first-out 203b, the image data multiplied by 1/4, and 2 /. The image data F multiplied by 4, the image data F multiplied by 3/4, and the ground potential are selected for each line and input to the data summing unit 206.

In other words, the coefficient multiplied by the video signal output from the first-in first-out unit 203a becomes four coefficients of K in the first three horizontal line periods, and then four coefficients of 1-K after the next three horizontal line periods. Is multiplied by the video signal output from the second first-in, first-out 203b. The coefficients multiplied by the first three lines become four coefficients of 1-K in the first three lines. Must be multiplied.

As such, the image data selected by the first and second multiplexers 205a and 205b of the first data selector 205 is added through the data adder 206, which is multiplied for each signal line. The sum of the coefficients is always one.

The image data added to each line by the data summing unit 206 is input to the first field memory unit 208, where the first horizontal synchronization counter unit 207 counts the start of the horizontal scanning line to zoom. The horizontal enable signal Hsy input through the inter-synchronization input terminal 200 is counted so that when the horizontal scan line reaches the zooming interval, the write enable signal WE is provided to the first field memory unit 208.

The first field memory unit 208 is activated when the write enable signal WE is input from the first horizontal synchronization counter unit 208, and the image is zoomed out as 3: 4 by the data summing unit 206. The data is collected and recorded, and the zoomed digital image data is output through the output terminal 209.

9 is a configuration diagram of another embodiment of a 3: 4 line interpolation processing apparatus for a video signal according to the present invention.

Here, the same three line memories, that is, the third to fifth first-in first-out sections 303a to 303c, are used, and image data is recorded in three third to fifth first-in first-out sections 303a to 303c alternately every three lines. This is followed by multiplying them using the appropriate coefficients as shown in FIG. 5 and then synthesizing four lines.

This is briefly described with reference to FIG. 9 as follows.

First, when the horizontal synchronization signal Hsy from the synchronization input terminal 300 is input, the second clock generator 302b of the second scanning line processing unit 302 receives a recording signal every time the horizontal synchronization signal Hsy is input. WR is generated and provided to the third to fifth first-in first-out parts 303a to 303c and the fourth multiplying part 302e of the second data storage part 303, and the fourth multiplying part 302e The input write signal WR is multiplied by 4/3 to provide the read signal RD to the third to fifth first-in first-out parts 303a to 303c.

The horizontal synchronization signal Hsy input through the synchronization input terminal 300 is multiplied by 4/3 through the third multiplier 302c of the second scan line processor 302, and the multiplied signal is multiplied by each field. Is supplied to the second line selection section 306 to be described later as a two-bit second selection control signal S2 via the second module counter section 302d, which is cleared by the synchronization input terminal 302g. .

On the other hand, the second counter unit 302a of the second scanning line processing unit 302 counts the input horizontal synchronization signal Hsy for each line and sets a number from 0 to 2 as the first selection control signal S1. The second switching unit 302f is provided.

At this time, when the digital image data is input to the second switching unit 302f through the image input terminal 301, the second switching unit 302f is provided with a first selection control signal provided by the second counter unit 302a. Switched by S1) to input the input digital image data alternately every three lines.

The third to fifth first-in first-out units 303a to 303c of the second data storage unit 303 each time the second switching unit is input whenever a write signal WR is input from the second clock generator 302b. The image data input at 302f is recorded, and the recorded image data is read out by the read signal RD which is 4/3 times the frequency of the recording signal WR provided from the fourth multiplication unit 302e. The second to 12th multipliers 304a to 304f and the second line selector 306 of the second line interpolation unit 304 are input.

The seventh and twelfth multipliers 304a and 304f of the second line interpolator 304 multiply the image data input from the third first-in first-out unit 303a by a coefficient value 1/4 to obtain a second data adder ( 305 inputs to the first and third adders 305a and 305c, and the eighth and ninth multipliers 304b and 304c input coefficient values 3/3 to the image data input from the fourth first-in first-out 303b. 4 and 2/4 are respectively multiplied and input to the first and second adders 305a and 305b.

The tenth and eleventh multipliers 304d and 304e of the second line interpolator 304 multiply the image data input from the fifth first-in first-out 303c by coefficient values 2/4 and 3/4. Inputs are made to the second and third adders 305b and 305c.

The first adder 305a of the second data summing unit 305 adds and outputs image data input by multiplying 1/4 and 3/4 by the seventh and eighth multipliers 304a and 304b, respectively. The second adder 305b is multiplied by 2/4 in the ninth and tenth multipliers 304c and 304d to add the input image data, and the third adder 305c is an eleventh and twelfth multiplier. 3/4 and 2/4 are multiplied by 304e and 304f, respectively, to add and output the input image data.

The image data output from the first to third adders 305a to 305c is input to the second line selector 306.

The second line selection unit 306 receives the third first-in first-out unit 303a by the second bit selection control signal S2 input from the second module counter unit 302d of the second scanning line processing unit 302. Image data or image data added by the first to third adders 305a to 305c is selected and provided to the second field memory unit 308.

That is, when the 2-bit second selection control signal S2 is input as 0,0, the second line selector 306 selects original image data input from the third first-in first-out 303a and selects the second field. When the second selection control signal S2 is input to 0.1, the second data is added to the memory unit 308, and the second selection control signal S2 is input as 1,0 to the image data added by the first adder 305a. Image data of the second adder 305b, and image data of the third adder 305c when the second selection control signal S2 is inputted as 1, 1 to the second field memory unit 308. Will be provided.

The second field memory section 308 writes from the second horizontal sync counter section 307 the same as the first horizontal sync counter section 207 in FIG. 5 described above. The second line selector 306 records the image data zoomed to 3: 4, and outputs the zooming digital image data through the output terminal 309.

Thus 3; When the image data zoomed in at 4 is shown on the screen, as shown in FIG. 11 (b), the screen is expanded in a 4: 3 ratio and a dotted line portion exceeding the 16: 9 range is removed.

11A shows a state in which a 4: 3 video signal is displayed without changing an aspect ratio on a screen having an aspect ratio of 16: 9.

6 is a block diagram of a 4: 3 compression processing apparatus for a video signal according to the present invention.

In this case, a horizontal compression process for displaying a normal mode using the same line memory, that is, two first-in first-out units, is shown. As shown in this figure, the horizontal line is input through the synchronization input terminal 400 for horizontal compression. A pixel compression control unit 402 for generating and outputting the first to fourth selection control signals S1 to S4 and the write enable signal WE different from each other with a synchronization signal Hsy; Image data input through the image input terminal 401 by the first selection control signal S1 and the fourth selection control signal S4 generated by the pixel compression control unit 402 is second and third for each pixel. A third data storage unit 403 which alternately stores and outputs the Philip flops 403a and 403b; The image data input from the third data storage unit 403 is combined with each of the four pixels and synthesized into three pixels, and the image data is combined according to the second and third selection control signals S2 and S3 of the pixel compression control unit 402. A pixel compression unit 404 for switching and outputting every line; The pixel data selected and input from the pixel compression unit 404 every line are alternated to the sixth and seventh first-in first-out parts 405a and 405b according to the write enable signal WE of the pixel compression control unit 402. A fourth data storage unit 405 for storing and outputting the data in order; A 2-bit luminance level selection control signal LS is generated according to an average picture level (APL) or an average beam current level (ABL) sensed and input from the input terminal 408. Romans 409 and; A luminance level selector for selecting and outputting any one of the luminance level values D1 to D4 of the side panel according to the 2-bit luminance level selection control signal LS generated in the ROM 409. 410 and; The luminance level values D1 to D4 of the side panel selected by the luminance level selecting unit 410 are alternately input to the pixel data alternately input from the fourth data storage unit 405. A side panel inserting portion 406 for inserting and outputting in accordance with the fourth selection control signal S3 or S4; And a third field memory unit 407 for storing image data into which the luminance level values of the side panel from the side panel inserting unit 406 are inserted for each field and outputting a horizontally compressed digital video signal.

The pixel compression control unit 402 includes a third clock generation unit 402a for generating a clock pulse whenever a horizontal synchronization signal Hsy is input through the synchronization input terminal 400; A third module counter unit 402e for counting clock pulses generated by the third clock generator 402a to generate a second 2-bit selection control signal S2 and providing the same to the pixel compression unit 404; ; A logic sum element 402f for performing a logical sum of the second 2-bit selection control signal S2 generated by the third module counter 402e and generating it as a write enable signal WE; A clock counter unit 402c for counting up to a clock pulse setting value generated by the third clock generator 402a to generate a fourth selection control signal S4; A third counter unit 402b, which is a T-flip-flop that receives the clock pulse from the third clock generator 402a and changes and outputs the first selection control signal S1 every clock; A third horizontal synchronous counter 402d for counting the horizontal synchronous signal Hsy input from the synchronous input terminal 400 every line to generate a third selection control signal S3; The image data input through the image input terminal 401 by the first selection control signal S1 of the third counter unit 402b and the fourth selection control signal S4 of the clock counter unit 402c is converted into a third image. The first and second flip-flops 403a and 403b of the data storage unit 403 comprise a third switching unit 402g which writes alternately every pixel.

The pixel compression unit 404 is a fourteenth and fifteenth multiplier for multiplying the pixel values input from the first flip-flop 403a of the third data storage unit 403 by coefficient values 1/3 and 2/3, respectively. 404b and 404c; Thirteenth and sixteenth multipliers (404a) (404d) for multiplying coefficient values 2/3 and 1/3 by the pixels input from the second flip-flop (403b) of the third data storage unit (403); A fourth adder (404e) for adding two pixel values obtained in the 213th and 14th multipliers (404a) and (404b), respectively; A fifth adder (404f) for adding two pixel values obtained in the fifteenth and sixteenth multipliers (404c) (404d), respectively; A third module counter of the pixel compression control unit 402 for the two pixels added by the fourth and fifth adders 404e and 04f, the first pixel input from the twenty-first flip-flop 403, and its ground potential. A third multiplexer 404g for selecting and outputting every four clocks by the second bit selected control signal S2 to be generated in the unit 402e; The pixel selected by the third multiplexer 404g is switched every line by the third selection control signal S3 of the third horizontal synchronization counter 402d, so that the sixth, The fourth switching unit 404h is recorded in the seventh first-in first-out units 405a and 405b.

The side panel inserting unit 406 is switched every line by the third selection control signal S3 generated by the third horizontal synchronization counter unit 402d of the pixel compression control unit 402, and thus is the sixth and seventh. A fifth switching unit 406a for selecting and outputting pixels input from the first-in first-out units 405a and 405b; The luminance level value of the pixel of the fifth switching unit 406a and the luminance level selection unit 410 are switched by the fourth selection control signal S4 generated by the clock counter unit 402c of the pixel compression control unit 402. The sixth switching unit 406b is configured to mix (D1-D4) and provide it to the third field memory unit 407.

4 of the video signal according to the invention shown in FIG. 6 in the screen aspect ratio converting apparatus of the present invention configured as described above; A three pixel compression processing apparatus will be described with reference to FIGS. 8 and 12 as follows.

In this case, the horizontal compression processing operation for displaying the normal mode using the same line memory, that is, the sixth and seventh first-in first-out shaft units 405a and 405b of the fourth data storage unit 405, is performed first. When the synchronization signal Hsy is input through the synchronization input terminal 400, the pixel compression control unit 402 compresses the horizontal pixels as described above, so that the horizontal synchronization signal (Hsy) is input through the synchronization input terminal 400. Hsy) generates and outputs the first to fourth selection control signals S1 to S4 and the write enable signal WE which are different from each other.

That is, the pixel compression control section 402 includes a third counter section 402b, a third clock generator 402a, a clock counter section 402c, and a third horizontal synchronization counter section 402d, which are T-flip flops. ), A third module counter section 402e, a logic sum element 402f, and a third switching section 402g.

The third clock generator 402a generates a clock whenever the horizontal synchronization signal Hsy is input through the synchronization input terminal 400 to generate a third counter 402b, click counter 402c, and third. The module counter unit 402e is provided.

The first counter unit 402b changes the first selection control signal S1 to a high potential and a low potential every time the clock from the third clock generator 402a is input, thereby causing the third switching unit 402g to operate. The clock counter unit 402c counts a clock input from the third clock generator 402a to switch the fourth selection control signal S4 to a third switch, which will be described later. The chip enable terminal CE of the unit 402g is provided.

In addition, the third module counter unit 402e uses a 2-bit number from 0 to 4 for every four lines to generate a selection control signal for each line of the horizontal synchronous clock input from the third clock generator 402a. As a result, the second selection control signal S2 is generated and provided to the logic sum element 402f and the third multiplexer 404g of the pixel compression unit 404.

The third horizontal synchronization counter unit 402d generates a third selection control signal S3 by counting a start portion of the horizontal synchronization signal Hsy input through the synchronization input terminal 400 every line. The fourth switching unit 404h of the pixel compression unit 404 and the fifth switching unit 406a of the side panel insertion unit 406 are provided.

At this time, when digital image data such as (a) of FIG. 8 is input through the image input terminal 401, the third switching unit 402g receives the first selection control signal S1 of the third counter unit 402b. And a first flip-flop 403a of the third data storage unit 403, which is a D-flip-flop, which is switched every line by the fourth selection control signal S4 of the clock counter 402c. And the second flip-flop 403b are alternately stored.

That is, as shown in (a) of FIG. 8, in the actual image section T, since image data should be compressed by 3/4 as shown in (b) of FIG. 8, the pixels alternately every pixel during the image section T. Written in the first flip-flop 403a and the second flip-flop 403b.

Pixels of the image data recorded in the first and second flip-flops 403a and 403b of the third data storage unit 403 are alternately provided to the pixel compression unit 404.

When the pixels of the image data are alternately inputted from the first and second flip-flops 403a and 403b of the third data storage unit 403, the pixel compression unit 404 combines them with every four pixels to form three pixels. Will be synthesized.

That is, the pixels output from the first flip-flop 403a of the third data storage unit 403 are the 14th, 15th multipliers 404b and 404c and the third multiplexer 404g of the pixel compression unit 404. ) And the output from the second flip-flop 403b are input to the thirteenth and sixteenth multipliers 404a and 404d of the pixel pressure pursuit 404.

The thirteenth multiplier 404a multiplies the second pixel input from the second flip-flop 403b by the coefficient value 2/3 (or 5/8 to simplify the calculation) and inputs it to the fourth adder 404e. The fourteenth multiplier 404b multiplies the third pixel input from the first flip-flop 403 by the coefficient value 1/3 (or 3/8) to provide it to the fourth adder 404e. The multiplier 404c multiplies the third pixel input from the first flip-flop 403a by the coefficient value 2/3 (or 5/8) and provides it to the fifth adder 404f. Finally, the 16th multiplier 404d multiplies the fourth pixel input from the second flip-flop 403b by the coefficient value 1/3 (or 3/8) to provide it to the fifth adder 404f.

The fourth adder 404e is multiplied by the thirteenth and fourteenth multipliers 404a and 404b, respectively, and adds the second pixel and the third pixel to the third multiplexer 404g. 404f adds the third pixel and the fourth pixel, which are multiplied by the fifteenth and sixteenth multipliers 404c and 404d, to be provided to the third multiplexer 404g.

In this case, the third multiplexer 404g may receive the second multiplexer 404a from the second flip-flop 403a by a 2-bit second selection control signal S2 input from the third module counter 402e of the pixel compression controller 402. The first pixel directly input and the sum value obtained from the fourth and fifth adders 404e and 404f and their ground potentials are alternately selected every four clocks, and the outputs are alternately selected. During this time, the ground potential (or no signal) is selected.

That is, in detail, first, when the second 2-bit selection control signal S2 input from the third module counter unit 402e is 0, 0, the third multiple call unit 404g has no ground potential (or zero). 6) of the fourth data storage unit 405 through the fourth switching unit 404h which is switched every line by the third selection control signal S3 of the third horizontal synchronization counter unit 402d. And the seventh first-in first-out part 405a and 405b. In this case, since the second selection control signal S2 is 0 and 0, the output enable signal WE of the logic sum element 402f is also 0, so that the sixth In this case, the seventh first-in first-out parts 405a and 405b are disabled to not record the sub-signals.

When the second selection control signal S2 is input as 0, 1, the third multiplexer 404g selects and outputs the first pixel input from the first flip-flop 403a, and the second selection control signal. When S2 is input as 1,0, the sum of the second pixel and the third pixel added by the fourth adder 404a is selected and outputted. Finally, when the second selection control signal S2 is input as 1,1 The sum of the third pixel and the fourth pixel added by the fifth adder 404f is selected and output.

As such, by combining the three pixels by the pixel compression unit 404 for each of the four pixels, the actual image section T as shown in FIG. 8A is only 3/4 as shown in FIG. 8B. It is compressed and output.

Subsequently, the synthesized signal selected for three pixels in the third multiplexer 404g is alternately recorded to the sixth and seventh first-in first-out units 405a and 405b every line through the fourth switching unit 404h. In the unrecorded first-in first-out section, previously recorded pixels are read and provided to the fifth switching section 406a of the side panel inserting section 406.

The fifth switching unit 406a of the side panel inserting unit 406 is connected to the sixth and seventh first-in, first-out unit in each line by the third selection control signal S3 of the third horizontal synchronization counter unit 402d. The pixels of 406a are alternately selected and provided to the sixth switching unit 406b.

In this case, in order to display the compressed 3/4 ratio image signal in the form as shown in (b) of FIG. 12 on a screen having an aspect ratio of 16: 9 as shown in FIG. On the right side, the luminance level value of the side panel should be inserted, as shown in FIG.

The luminance level value insertion may be given only a black level unconditionally, but the input terminal detects the average pixel level (APL) or the average beam current level (ABL) at each time by a difference of luminescence decay of a phosphor (DLDP) of a fluorescent material. When provided to the ROM 409 through 408, the ROM 409 is a predetermined 2-bit luminance level selection control signal LS according to the input average pixel level APL or average beam current level ABL. ) Is provided to the luminance level selector 410.

The luminance level selector 410 selects an appropriate value among the preset luminance level values D1-D4 according to the input 2-bit luminance level selection control signal LS, and then selects an appropriate value of the side panel inserter 406. 6 to the switching unit 406b.

The sixth switching unit 406b includes left and right portions of the video signal compressed at 3/4 by the fourth selection signal S4 provided from the clock counter unit 402c, as shown in FIG. The luminance level value is inserted into T1 and T2 and stored in the third field memory unit 407, and the horizontally compressed digital video signal is output through the output terminal 411.

10 is a configuration diagram of another embodiment of a 4: 3 pixel compression processing apparatus for an image signal according to the present invention. Unlike FIG. 6, four third to sixth flip-flops 403c to 403f are used. As the horizontal compression processing, the coefficient values of FIG. 6 may be separately processed for each of the third to sixth flip-flops 403c to 403f, and thus the outputs corresponding to the outputs of the respective third to sixth flip-flops 403c to 403f. The coefficients are multiplied.

That is, referring to the configuration thereof, the fourth counter unit 402i, which is a module counter that counts a clock input from the third clock generator 402a of FIG. 6 and generates a first 2-bit selection control signal S1. Wow ; Through the image input terminal 401 by the first 2-bit selection control signal S1 input from the fourth counter unit 402i and the fourth selection control signal S4 input from the clock counter unit 402c. A seventh switching unit 402h for switching input digital image data every line and outputting the same; Third to sixth flip-flops 403c to 403f for alternately storing and outputting image data input for each line by the seventh switching unit 402h; A seventeenth multiplier 404i for multiplying the pixel value input from the fourth flip-flop 403d by the coefficient value 2/3 and inputting the fourth adder 404e; 18th and 19th multipliers 404j and 404k input to the fourth and fifth adders 404e and 404f by multiplying each pixel input from the fifth flip-flop 403e by 1/3; And a twelfth multiplier 404l which multiplies the pixel value inputted by the sixth flip-flop 403f by the coefficient value 2/3 and inputs it to the fifth adder 404f. And the operation description thereof is omitted.

In the 4: 3 pixel compression processing apparatus of the video signal according to the present invention configured as described above, first, the clock input from the third clock generator 402a is input from the third counter unit 402b of the pixel compression controller 402. Each bit is counted to generate the first 2-bit selection control signal S1 and is provided to the selection terminal S of the seventh switching unit 402h.

The seventh switching unit 402h is connected to the two-bit first selection control signal S1 input from the third counter unit 402b and the fourth selection control signal S4 input from the clock counter unit 402c. The digital image data, which is switched every line, is input through the image input terminal 401 and is recorded in the third to sixth flip-flops 403c to 403f of the third data storage unit 403.

The pixel of the image data recorded in the third flip-flop 403c is provided to the third multiplexer 404g of the pixel compression unit 404, and the pixel recorded in the fourth flip-flop 403d is the seventeenth multiplier ( 404i) and the pixels recorded in the fifth flip-flop 403e are input to the eighteenth and nineteenth multipliers 404i and 404k, respectively, and the pixels recorded in the sixth Philip flop 403f are input to the twentieth multiplier 404l. do.

The seventeenth multiplier 404i multiplies the second pixel input from the fourth flip-flop 403d by the coefficient value 2/3 to provide it to the fourth adder 404e, and the eighteenth and nineteenth multiplier 404j ( 404k may multiply the third pixel input from the fifth flip-flop 403e by the coefficient value 1/3 to provide the fourth and fifth adders 404e and 404f, and the twentieth multiplier 404l may be used as the third pixel. In the sixth flip-flop 403f, the fourth pixel inputted every line is multiplied by a coefficient value 2/3 to be provided to the fourth and fifth adders 404f, thereby providing the fourth and fifth adders 404e and 404f. As shown in FIG. 6, in the same manner, the second pixel, the third pixel, and the third and fourth pixels are summed and provided to the third multiplexer 404g to the third multiplexer 404g. Have the user alternate between every four clocks.

As such, the image data selected every four clocks are alternately recorded in the sixth and seventh first-in first-out units 405a and 405b of the fourth data storage unit 405, and the image data is stored through the side panel insertion number 406. Luminance level values are inserted to the left and right sides of the signal and are written to the third field memory unit 407 and output.

As described in detail above, according to the present invention, line interpolation and horizontal compression are performed using a line interpolation method and a pixel compression method in a wide television receiver having an aspect ratio of 16: 9, thereby providing a zoom function as well as a horizontal compression function. By simply processing and storing the signal processing before the field memory, there is an effect that the freeze and double screen functions can be performed according to the read method of the stored image data.

Claims (33)

A scanning line processing unit for generating a recording / reading signal and a selection signal from the input horizontal synchronization signal; A data storage unit for selectively storing input image data according to the first selection signal and the recording / reading signal of the scanning line processing unit; A line interpolation unit for multiplying coefficient values by respective image data for the current and subsequent three lines obtained by the data storage unit; A line selector which sequentially selects and outputs the image data interpolated by the line interpolation unit and the image data of the data storage unit every line according to a selection signal of the scan line processor; A data summing unit for summing two image data obtained by the line selecting unit; And a field memory unit installed at a rear end of the line interpolator and configured to store and output image data from the data summing unit in field units. The display apparatus of claim 1, wherein the scan line processor comprises: a clock generator which generates a write signal to the data storage unit whenever a horizontal synchronization signal is input; A second multiplier for multiplying the clock signal of the clock generator by a predetermined value to generate a read signal in a data storage unit; A first multiplication unit multiplying the input horizontal synchronization signal to a predetermined value; A module counter unit which counts the horizontal synchronization signal multiplied by the first multiplier to generate a second selection signal of a predetermined bit and is cleared every field; A counter unit for counting the input horizontal synchronization signal and generating a first selection signal; And a switching unit which alternately switches input digital image data according to the first selection signal of the counter and provides the data storage unit. The apparatus of claim 1, wherein the data storage unit has two identical line memories. The multiplier of claim 1, wherein the line interpolation unit comprises: first to third multipliers that multiply coefficient values k, 1/4, 2/4, and 3/4 by the image data input from any one of the line memories of the data storage unit; ; The other one of the data storage units is composed of fourth to sixth multipliers for multiplying the coefficient (1-k) values 3/4, 2/4, and 1/4 by the image data input from the line memory. Screen aspect ratio inverter. The module counter unit of claim 4, wherein the line selector generates image data input from one of the line memories of the data storage unit, image data input from the first to third multipliers, and a ground potential of the module counter unit. A first multiplexer which sequentially selects the second select signal to be provided to the data adder; Image data obtained from the other line memory of the data storage unit, image data input from the fourth to sixth multipliers of the line interpolator unit, and its ground potential by the second selection signal generated by the module counter unit. And a second multiplexing unit which is sequentially selected and provided to the data summing unit. The apparatus of claim 2, wherein the second selection signal generated by the module counter unit is configured to be output in 3 bits. The screen aspect ratio converting apparatus according to claim 2, wherein the multiplication values of the first and second multiplication parts are configured to be 4/3, respectively. The method according to claim 5, wherein the first multiplexer sequentially selects coefficients (k) values 1, 1/4, 2/4, and 3/4 of the image signal for the first three lines by the second selection signal, And a coefficient (1-k) value of 0, 3/4, 2/4, and 1/4 is sequentially selected after the line period. The method of claim 5, wherein the second multiplexer sequentially selects 0, 3/4, 2/4, and 1/4 values of coefficient values (1-k) of the video signal for the first three lines by the second selection signal. And a coefficient (k) value of 1, 1/4, 2/4, and 3/4 after the three line periods are sequentially output. The apparatus of claim 2, wherein the counter unit is configured to divide the input horizontal synchronization signal into two and output the first selection signal. The apparatus of claim 2, wherein the switching unit is configured to divide the input image data in two directions for each line by the second selection signal of the counter unit and output the divided image data. The apparatus of claim 2, wherein the counter unit is configured to count an input horizontal synchronization signal every line and generate a number from 0 to 2 as the first selection signal. The apparatus of claim 2, wherein the switching unit is configured to divide the input image data into three directions for each line by the first selection signal of the counter unit and output the divided image data. The data storage unit of claim 1, wherein the data storage unit comprises three line memories each storing image data of three lines inputted to each line through the scan line processing unit in alternating order and providing them to the line interpolation unit and the line selection unit. Screen aspect ratio converter, characterized in that. The apparatus of claim 2, wherein the module counter unit is configured to generate a second selection signal of two batts. The first and second lines of claim 1 or 14, wherein the line interpolation unit multiplies one-fourth the pixels of the image data obtained in the first line memory among the three line memories and provides them to the data summing unit for three horizontal lines. A sixth multiplier; Second and third multipliers for multiplying 3/4 and 2/4 by pixels obtained from the other line memories and providing them to the data summing section; And a fourth and fifth multipliers provided by multiplying 2/4 and 3/4 to pixels obtained by another line memory of the data storage unit, and provided to the data adding unit. 17. The apparatus of claim 16, wherein the data summing unit comprises: a first adder for adding different pixel values obtained from the first and second multipliers of the line interpolation unit to provide the line selecting unit for three line periods; A second adder which adds pixel values obtained by the third and fourth multipliers of the line-interval part and provides them to the line selector; And a third adder which adds the image data obtained by the fifth and sixth multipliers of the line interpolator and provides the line selector to the line selector. 18. The 2-bit second device according to claim 14 or 17, wherein the line selector adds a pixel value obtained from any one line memory of the data storage unit and a coefficient value added from the first to third adders. And an input signal is sequentially selected for every line by the selection signal and recorded in the field memory unit. 18. The apparatus of claim 1 or 17, wherein a sum of two coefficients multiplied by the video signal of each line is configured to be one. Pixel compression control means for generating different first to fourth selection signals and write enable signals having horizontal synchronization signals input for horizontal compression; First data storage means for storing and outputting image data input by the first and fourth selection signals obtained by the pixel compression control means in every pixel alternately; Pixel compression means for combining the image data obtained by the first data storage means into three pixels by combining them every four pixels and selectively outputting the image data according to a second selection signal of the pixel compression control means; Second data storage means for storing the pixels obtained by the pixel compression means in alternating order according to the write enable signal of the pixel compression control means; The luminance level value of the side panel, which is preset and selected by sensing the average pixel level or the average beam current level from the outside, is alternately input to the pixel data alternately input by the second data storage means. Side panel inserting means for inserting and outputting according to a fourth selection signal; And field memory means for storing a video signal into which the side panel is inserted from the side panel inserting means for each field and outputting a horizontally compressed digital video signal. 21. The memory device of claim 20, further comprising: a ROM for generating a predetermined brightness level selection signal according to a detected value of the average pixel level or the average beam current level; And a luminance level selecting means for selecting an appropriate value among the luminance level values differently set according to the luminance level selection signal generated in the ROM and providing the value to the side panel inserting means. 21. The apparatus of claim 20, further comprising: clock generation means for generating a clock pulse each time the horizontal compression signal is input to the pixel compression control means; Module counter means for counting clock pulses generated by said clock generating means to generate a second 2-bit selection signal and to provide it to the pixel compression means; A logic sum element for ORing the second selection signal of the two bits generated by the module counter means and generating it as a write enable signal; Clock counter means for counting a clock pulse generated by the clock generating means to a predetermined value and generating a fourth selection signal; Counter means for receiving a clock pulse of the clock generating means and changing and outputting a first selection signal every clock; Horizontal synchronous counter means for counting the input horizontal synchronous signal every line and generating a third selection signal; And first switching means for recording the input digital image data in the first data storage means alternately every pixel by the first selection signal of the counter means and the fourth selection signal of the clock counter means. Screen aspect ratio inverter. 21. The apparatus of claim 20, wherein the first data storage means consists of two identical D flip-flops. 21. The apparatus of claim 20, wherein the pixel compression means comprises: second and third multipliers for multiplying and outputting coefficient values 1/3 and 2/3 to pixels input from one flip-flop of the first data storage means; First and fourth multipliers for multiplying the pixel values input from the other flip-flop of the first data storage means by 2/3 and 1/3 respectively; A first adder for adding two pixel values obtained in the first and second multipliers, respectively; A second adder for adding two pixel values respectively obtained by the third and fourth multipliers; The two pixels added by the first and second adders, the first pixel input from the second flip-flop and the ground potential of the pixel are controlled by a two-bit second selection signal generated by the module counter of the pixel compression control means. Multiplexing means for selecting and outputting every four clocks; And second switching means for switching the pixels selected by the multiplexing means every line by the third selection control signal of the horizontal synchronous counter means and writing them to the second data storage means. 21. The apparatus of claim 20, wherein the side panel inserting means is switched every line by the third selection signal generated by the horizontal synchronization counter means of the pixel compression control means to select the pixel input from the second data storage means every line. Third switching means for outputting; A fourth switching means which is switched by the fourth selection signal generated by the clock counter means of the pixel compression control means and mixes the pixel of the third switching means and the luminance level value of the brightness level selecting means to provide to the field memory means; Screen aspect ratio converter, characterized in that. 21. The screen aspect ratio converting apparatus according to claim 20, wherein the second data storage means has two identical line memories and is configured to store alternately by a write signal of a logic element. 23. The apparatus of claim 22, wherein the counter means is a T-flip flop. 23. The apparatus of claim 22, wherein the counter means is a module counter that counts a clock generated by the clock generating means and generates a number from 0 to 3 as a first selection signal. 29. The apparatus of claim 22 or 28, wherein when the counter means is a module counter, the first switching means is a switch for shunting the input digital image data in four directions every line. . 23. The method of claim 22, wherein the first data storage means is composed of four identical first to fourth D-flip flops to alternately store pixels that are divided in four directions from the first switching means. And the first pixel of the stored four pixels is provided directly to the multiplexing means, and the remaining pixels are provided to the first to fourth multipliers of the pixel compression means. 31. The method of claim 24 or 30, wherein when there are four D-flip flops, the first multiplier and the fourth multiplier multiply the second and fourth pixels obtained from the second and fourth flip flops by 2/3, respectively. The first and second adders, and the second and third multipliers are configured to multiply the third pixel obtained from the third flip-flop by the coefficient value 1/3 to provide the first and second adders. Aspect ratio inverter. 25. The screen according to claim 24, wherein the multiplexing means is configured to select the ground potential, the output of the first flip-flop, the output of the first adder, and the output of the second adder by the second selection signal of the module counter means. Aspect ratio inverter. 25. The apparatus of claim 24, wherein the sum of two coefficients multiplied for each pixel line of the first and second adders is configured to be one.