KR0161756B1 - Cell generating apparatus by using multiplexer - Google Patents

Abstract

The present invention relates to a cell generator using a multiplexer, to provide a cell generator using a multiplexer for stably generating cell data having various structures for the functional test of switches and other equipment, the external central processing Cell generation control means for receiving the generation information data and the first control signal from the means and outputting the cell generation rate and the number of cell generations according to the cell generation mode; The second control signal B-CLK, / CEN, and SYN is received by determining the cell generation time by receiving the first control signal from the central processing means and the cell generation rate and the number of cell generations from the cell generation control means. Multiplexing control means for outputting to an external device and outputting a cell region generation control signal and a multiplexing control signal; Cell region generation means for receiving a cell region generation control signal from the multiplexing control means and receiving routing card data from the central processing means to generate a cell region; And multiplexing means for multiplexing the output of the cell region generating means according to the multiplexing control signal of the multiplexing control means and outputting cell data to the external device to ensure stable and continuous cell generation, By minimizing the number of gates for cell generation, there is an effect that it can be easily extended to a modular concept when expanding a larger number of channels later.

Description

Cell Generator Using Multiplexer

1 is an exemplary configuration diagram of a general cell generator.

2 is a structural example of a cell for an 8 × 8 ATM switch test.

3 is a temporary configuration diagram of a cell generator using a multiplexer according to the present invention.

4 is a timing diagram of a cell data bus and a second control signal according to the present invention.

4 is a timing diagram of a register control signal according to the present invention.

6 is a timing diagram of a multiplexer and a cell region generation control signal according to the present invention.

* Explanation of symbols for the main parts of the drawings

31: generation control register 32: multiplexing control unit

33: cell region generator 34: multiplexer

35: tag area generator 36: SID area generator

37: SN region generator 38: TP region generator

The present invention includes an 8 × 8 Asynchronous Transfer Mode (ATM) switch, which is being performed as part of the research and development of distributed router functions in the development of a Broadband Integrated Service Digital Network (B-ISDN) transmission device. The present invention relates to a cell generator using a multiplexer that stably generates cell data having various structures for the functional test of other equipment.

As the next generation communication network (B-ISDN) of Asynchronous Transfer Mode (ATM) method, which is in the spotlight as the next generation communication network, has been researched and developed worldwide, time division multiplexing based on the existing Synchronous Transfer Mode (STM) method Unlike the time division multiplexing (TDM) scheme, a fixed length packet exchange scheme suitable for the asynchronous transfer mode (ATM) scheme is required. In order to test the function of the exchange, which is an important component of the communication network, in the development stage or to diagnose the state of the network, a device generating a fixed length cell having a certain shape and applying it to a specific channel or several channels simultaneously It became necessary.

Such a cell generator can be configured in a general form as shown in the first block. The external hard disk stores a cell transmission start index and temporarily stores the cell transmission start index in a first-in-first-out circuit (FIFO) by the hard disk controller. The internal timer value and the value of the generation time storage first-in first-out circuit (FIFO) are received by the cell generation timing unit to drive the RAM and the counter unit. Finally, the cells from the RAM are temporarily stored in the cell feed-in first-in-first-out circuit (FIFO) and then discharged.

The general cell generator as described above requires a hard disk, RAM, FIFO control logic, and the like, and is subject to the length of the cell generation time depending on the capacity of the memory device. There was a problem that it is not easy to manufacture a custom semiconductor.

Therefore, a cell generator for testing basic functions of 8 × 8 asynchronous transfer mode (ATM) switches or larger switches and other equipment should have a simple but continuous and stable cell generation function. There is a need for a cell generator structure that can provide stable and continuous supply of cells with little or no use.

In order to solve the above problems, the present invention, to generate a test asynchronous transfer mode (ATM) cell and the like to ensure a stable and continuous cell generation by having several registers, multiplexers and multiplexing control unit for controlling the multiplexer, The cell generation time is determined by combining the cell generation rate and the number of occurrences, and minimizing the number of gates for cell generation in one channel, so that a multiplexer can be easily extended to a modular concept in the future when a larger number of channels are expanded. It is an object of the present invention to provide a cell generating apparatus used.

In order to achieve the above object, the present invention includes: cell generation control means for receiving the generation information data and the first control signal from an external central processing means and outputting the cell generation rate and the number of cell generations according to the cell generation mode; The second control signal B-CLK, / CEN, and SYN is received by determining the cell generation time by receiving the first control signal from the central processing means and the cell generation rate and the number of cell generations from the cell generation control means. Multiplexing control means for outputting to an external device and outputting a generation control signal and a multiplexing control signal to a cell area; Cell region generation means for receiving a cell region generation control signal from the multiplexing control means and receiving routing tag data from the central processing means to generate a cell region; And multiplexing means for multiplexing the output of the cell region generating means in accordance with the multiplexing control signal of the multiplexing control means and outputting cell data to the external device.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

2 is a structural diagram of a cell for 8 × 8 asynchronous transfer mode (ATM) switch testing.

The routing tag part is 3-byte information for self-routing inside an 8 × 8 Asynchronous Transfer Mode (STM) switch, and the SID (Source IDentifier) part is one byte that identifies the originating port of the cell generated by the unique name of each of the eight channels. Information, and the SN (Sequence Number) part is 1-byte information of a modular concept indicating an order in a cell generated in each channel, and the TP (Test Pattern) part is 51 byte information indicating a payload component of a generated cell. . In FIG. 2, the transmission direction means the order in which the asynchronous transfer mode (ATM) cells are transmitted. That is, cells are exported in order of routing tag, SID, SN, and TP.

3 is a configuration diagram of a cell generator using a multiplexer according to the present invention, and receives generation information data and a first control signal from an external central processing unit and multiplexes the cell generation rate and the number of cell generations according to the cell generation mode. A generation control register 31 to be output to 32, a first control signal from the central processing unit; a cell generation rate and a number of cell generations from the generation control register 31; Outputs 2 control signals (B-CLK, / CEN, SYN) to an external device (asynchronous transfer mode switch, etc.), outputs the cell region generation control signal to the cell region generation unit 33, and multiplexes the control with the multiplexer 34 Multiplexing control unit 32 for outputting a signal, the cell area generation control signal from the multiplexing control unit 32 is input and routing tag data is input from the CPU to generate a cell area. The cell region generator 33 and the cell region generator 33 output to the multiplexer 34 are multiplexed according to the multiplexing control signal of the multiplexing controller 32 to transfer cell data to the external device (asynchronous transmission). And a multiplexer 34 for outputting to a mode switch).

In addition, the cell region generator 33 receives a tag region generation control signal from the multiplexing controller 32 and receives routing tag data from the CPU, and performs self-routing in an asynchronous transfer mode (ATM) switch. SID area generating a SID area for generating a tag area for generating a cell generated under the unique name of each channel by receiving the SID area generation control signal from the tag area generation unit 35 and the multiplexing control unit 32 generating a tag area for The generation unit 36 receives the SN region generation control signal from the multiplexing control unit 32, and generates the SN area generating unit 37 and the multiplexing control unit generating the SN area indicating the order of cells generated in each channel. 32) a TP region generation section 38 for receiving a TP region generation control signal and generating a TP region for displaying the payload component of the generated cell. It has an expandable structure.

In addition, since the bus connected to the external central processing unit in FIG. 3 is a data bus shared with other functional blocks other than the present invention, the data of FIG. 3 includes, in addition to the occurrence information data and the routing tag data used in the present invention. Other information may be included.

The operation is described below with reference to the timing diagrams of FIGS. 4 to 6.

First, routing tag information is input from the external central processing unit to the register of the tag region generation unit 35 at the register control timing as shown in FIG. 5 and generation information data is input to the generation control register 31. At this time, when the SID area generating unit 36, the SN area generating unit 37, and the TP area generating unit 38 are configured using a general register or an external storage element, the generation control is finally made after designating the value of the register. The register 31 may directly instruct the multiplexer 34 to start generating cells. However, when a cell generation start signal is to be transmitted from an external central processing unit (when it is necessary to apply a cell to all channels simultaneously), the multiplexing control unit 32 sends a 1-bit cell generation start signal as shown in FIG. The principal multiplexing control unit 32 starts cell generation and can arbitrarily input the registers.

Since the TP area generating unit 38 is regarded as the most general form, the TP area generating unit 38 is composed of registers corresponding to the number of bytes of the corresponding area, or the number of necessary registers is large. It is composed of logic circuits because it changes with repeating patterns or regular rules.

The tag area generating unit 35, the SID area generating unit 36, and the SN area generating unit 37, when considered in the most general form, are composed of registers as many as the number of bytes of the corresponding area, or simply have a repeating pattern or a predetermined rule. As it changes, it consists of logical recall.

Considering that the second control signal and the cell data satisfying the timing shown in FIG. 4 are outputted to the output, the multiplexer 34 combines four lines of eight bytes of data into one data line. If the cell configuration is more subdivided into N, for example, it is responsible for N: 1 multiplexing.

In FIG. 4, B_CLK (Byte CLocK) among the second control signals is a signal for distinguishing cell data in byte units, and an / CEN (Cell ENable) signal among the second control signals is an active low signal indicating the existence time of a valid cell. The SYN (SYNchronous of cell) signal of the second control signal is a control signal indicating the start point of the effective cell.

When the multiplexing control signal and the cell region generation control signal are stably supplied, the entire cell generation is reliable, so the multiplexing control unit 32 signals / CEN and SYN signals indicating the start and existence period of each cell region generating unit 33 and the cell. It is important to control them simultaneously. That is, while the two control signals / CEN and SYN representing the completed cell are generated by the multiplexing control unit 32, the multiplexing control signal and each cell region must be generated based on these signals.

The multiplexing control unit 32 receives the generation rate and the number of occurrences of the cell from the generation control register 31 to determine the cell generation time. The generation control register 31 is connected to the data bus of the external central processing unit to receive information, and when the register is used in the tag area generation unit 35 of the cell area generation unit 33, the same data bus is also connected to the corresponding register. do.

5 is a register control signal and timing diagram according to the present invention, and can be regarded as a general register write operation. That is, the value is written to the register at the moment the write control signal is applied to the rising edge in accordance with the valid data existence period among the data on the data bus. Since data input from an external central processing unit is connected to the generation control register 31 in FIG. 3 in the form of a shared bus, when a certain value is to be written to the generation control register 31 in FIG. Is shown in the timing chart. That is, the first control signal (which can be regarded as a write control signal) in accordance with the section in which valid data to be written to the destination register (the occurrence control register becomes the destination register in Fig. 5) exists in the third error data. The rising edge of must be applied.

6 is a timing diagram of a multiplexer and a cell region generation control signal. The tag region generator 35 and the SID region generator 36 are configured with internal registers, and the SN region generator 37 and the TP region are generated. The section 38 is a timing diagram when the general logic circuit is configured. There are two multiplexing control signals. The cell region generating unit 33 is coupled with the multiplexing unit 34 to avoid the timing at which the two control signals change simultaneously. The cell region generation control signal includes a tag region generation control signal, an SID region generation control signal, an SN region generation control signal, and a TP region generation control signal. In addition, the hatched portion in FIG. 6 is a don't care area, meaning that the value may be 0: or 1.

As described above, the present invention includes several registers, a multiplexer, and a multiplexing control unit for controlling the multiplexer to ensure stable and continuous cell generation, and to minimize the number of gates for cell generation in one channel, thereby increasing the number of gates. When the number of channels is expanded, the modular concept can easily be extended.

In other words, the conventional cell generating apparatus (FIG. 1) has a structure in which cell information is read from an external storage function block such as an external hard disk and generated. Therefore, not only an external storage function block is required but also according to its capacity. Cell generation time is limited. However, in the present invention, all cells can be generated without any limitation of time without using any external memory function block (by distinguishing each cell through the cell generation region of FIG. 3 and combining the cell configuration information distinguished through the multiplexing unit. Occurs).

In addition, the effect of minimizing the number of gates for cell generation can be obtained by not using an external memory function block as shown in FIG. 1 primarily, and the four small function blocks constituting the cell generation region of FIG. By using a simple logic circuit, the memory device is also not used, minimizing the number of gates. For example, logic such as generating the TP region generating unit repeatedly changed in the order of 0, 1, 0, 1, or generating a pattern in which the pattern increases from 0 to a certain size can be easily implemented.

Claims (7)

Cell generation control means for receiving the generation information data and the first control signal from an external central processing means and outputting the cell generation rate and the number of cell generations according to the cell generation mode; The second control signal B-CLK, / CEN, and SYN is received by determining the cell generation time by receiving the first control signal from the central processing means and the cell generation speed and the number of cell generations from the cell generation control means. Multiplexing control means for outputting to an external device and outputting a cell region generation control signal and a multiplexing control signal; Cell region generating means for receiving a cell region generation control signal from the multiplexing control means and receiving routing tag data from the central processing means to generate a cell region; And multiplexing means for multiplexing the output of the cell region generating means in accordance with the multiplexing control signal of the multiplexing control means and outputting cell data to the external device. The method of claim 1, wherein the cell region generation control signal comprises: a tag region generation control signal, a source identifier (SID) region generation control signal, a sequence number (SN) region generation control signal, and a test pattern (TP) region generation control signal. Cell generating apparatus using a multiplexer comprising a. The tag region generating apparatus according to claim 1 or 2, wherein the cell region generating unit receives a tag region generation control signal from the multiplexing control unit and receives routing tag data from the central processing unit. Tag region generating means for generating a; SID area generation means for receiving a SID area generation control signal from the multiplexing control means and generating an SID area for distinguishing a generation port of a cell generated under a unique name of each channel; Generation means for generating an SN region for receiving an SN region generation control signal from the multiplexing control means and generating an SN region for displaying a sequence in a cell generated in each channel; And TP region generating means for receiving a TP region generation control signal from the multiplexing control means and generating a TP region for displaying the payload component of the generated cell. 4. The cell generating apparatus using a multiplexer according to claim 3, wherein said TP region generating means comprises one of a logic circuit changing with a constant repetition pattern or a specific rule or a register combination corresponding to the number of bytes of the region. 4. The cell generating apparatus using a multiplexer according to claim 3, wherein said TP area generating means uses either a first-in first-out circuit (FIFO) or RAM (RAM) of the minimum size because the number of necessary registers is large. 4. The tag area generating means, the SID area generating means and the SN area generating means each comprise one of a logic circuit changing with a constant repetition pattern or a specific rule or a register combination of as many bytes as the byte of the corresponding area. Cell generating apparatus using a multiplexer, characterized in that. The cell data output to the external device comprises: a 3-byte routing tag portion for self-routing in an asynchronous transfer mode (ATM) switch, and a generation port of a cell generated under a unique name of each channel. A one-byte source identifier (SID) portion, a one-byte sequence number (SN) portion of the modular concept that indicates the order in which cells originate from each channel, and a 51-byte TP that indicates the payload component of the generated cell. Cell generation apparatus using a multiplexer, characterized in that it comprises a (Test Pattern) portion.