KR0161199B1 - Method for fabricating compound semiconductor device - Google Patents
Method for fabricating compound semiconductor device Download PDFInfo
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- KR0161199B1 KR0161199B1 KR1019950050532A KR19950050532A KR0161199B1 KR 0161199 B1 KR0161199 B1 KR 0161199B1 KR 1019950050532 A KR1019950050532 A KR 1019950050532A KR 19950050532 A KR19950050532 A KR 19950050532A KR 0161199 B1 KR0161199 B1 KR 0161199B1
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 150000001875 compounds Chemical class 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims description 14
- 239000012535 impurity Substances 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 230000010354 integration Effects 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 2
- 230000003213 activating effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 60
- 239000010408 film Substances 0.000 description 13
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910001120 nichrome Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
본 발명은 화합물 반도체 소자의 제조방법은 기존 HBT 소자의 에피층들에서 베이스층의 일부를 이온주입 및 활성화 방법으로 높은 저항값을 갖도록 하고, HBT 소자를 형성한 후, 소자분리 식각 공정시 저항체를 패턴닝하여 원하는 저항값을 갖는 저항체 패턴을 형성하였으므로, 하나의 기판에 HBT와 고정항값을 갖는 저항체를 MMIC화시켜 소자의 고집적화에 유리하고, 하이브리드 공정이 생략되고 기존의 공정에 이온주입 공정만이 추가되므로 공정이 간단하여 제조 단가를 절감할 수 있으며, 기생저항이나 기생용량을 감소시켜 고속 및 고주파 특성이 향상된다.According to the present invention, a method of manufacturing a compound semiconductor device has a high resistance value by implanting and activating a part of a base layer in epitaxial layers of a conventional HBT device, and after forming an HBT device, Since the resist pattern having the desired resistance value was formed by patterning, MMIC of the resistor having the HBT and the fixed term value in one substrate is advantageous for high integration of the device, and the hybrid process is omitted and only the ion implantation process is used in the existing process. As a result, the process is simple and manufacturing costs can be reduced, and parasitic resistance or parasitic capacity is reduced to improve high speed and high frequency characteristics.
Description
제1도는 종래 기술에 따른 화합물 반도체 소자와 연결되는 저항체의 단면도.1 is a cross-sectional view of a resistor connected to a compound semiconductor device according to the prior art.
제2도(a) 내지 (g)는 본 발명에 따른 화합물 반도체 소자의 제조 공정도.2 (a) to (g) are manufacturing process diagrams of the compound semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10,20 : 화합물 반도체 기판 12 : 절연막10,20 compound semiconductor substrate 12 insulating film
4,30 : 저항체 16 : 층간절연막4,30: resistor 16: interlayer insulating film
18 : 콘택홀 19 : 전극18 contact hole 19 electrode
21 : 완충층 22 : 부컬렉터층21: buffer layer 22: sub-collector layer
23 : 컬렉터층 24 : 베이스층23 collector layer 24 base layer
25 : 에미터층 26 : 에미터 캡층25 emitter layer 26 emitter cap layer
27 : 에미터 전극 28 : 절연막27 emitter electrode 28 insulating film
29 : 감광막 패턴 31 : 베이스 전극29 photosensitive film pattern 31 base electrode
32 : 홈 33 : 컬렉터 전극32: groove 33: collector electrode
본 발명은 화합물 반도체 소자의 제조방법에 관한 것으로서, 갈륨비소(GaAs)와 알루미늄 갈륨비소(AlGaAs)와 같이 밴드갭의 차이가 큰 화합물 반도체 물질간에 이종접합으로 형성되는 이종접합을 바이폴라 트랜지스터(Heterojunction Bipolar Transistor ; 이하, HBT라 칭함)를 중심으로 하여 다양한 형태의 소자를 동일한 기판위의 동일한 칩상에 구현하는 엠.엠.아이.씨(monolithic microwave IC ; 이하 MMIC라 칭함)를 형성할 경우 동일한 기판상에 높은 저항값을 갖는 저항체를 함께 구현하는 경우에 칩면적을 감소시켜 소자의 고집적화에 유리하고, 제조 공정이 간단하며, 기생저항등을 감소시켜 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 화합물 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a compound semiconductor device, wherein a heterojunction is formed by heterojunction between compound semiconductor materials having a large difference in bandgap such as gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs). Transistors (hereinafter referred to as HBT) are formed on the same substrate when M.M.C. (monolithic microwave IC; referred to as MMIC) for implementing various types of devices on the same chip on the same substrate. Compounds that can improve the process yield and reliability of the device by reducing the chip area, and simplifying the manufacturing process, and reducing the parasitic resistance when implementing a resistor having a high resistance to A method for manufacturing a semiconductor device.
일반적으로 화합물 반도체는 실리콘 반도체에 비하여 전자의 이동속도가 1000배 이상 빠르고 내방사선 특성이 우수하며, 발광특성이 뛰어난 등의 장점 때문에 재료 및 공정단가가 매우 높음에도 불구하고 이종접합 바이폴라 트랜지스터(Heterojunction bipolar transistor ; 이하 HBT라 칭함), 메스펫(metal-semiconductor field effect transistor ; 이하 MESFET라 칭함), 고 전자이동도 트랜지스터(high electron mobility transistor ; 이하 HEMT라 칭함) 등의 초고속 전자소자에 사용되며, 화합물 반도체의 특성중 전도대의 전자가 에너지 레벨이 가전도대로 떨어질 때 빛을 방사하는 특성을 이용하여 레이저 다이오드(laser diode ; LD)와 수광 다이오드(photo diode; PD) 등의 광소자에도 활발히 응용되고 있다.In general, compound semiconductors are heterojunction bipolar transistors despite the high material and process cost due to the advantages of the electrons moving speed is more than 1000 times faster than the silicon semiconductors, excellent radiation resistance, and excellent light emission characteristics. transistors; referred to as HBT), metal-semiconductor field effect transistors (hereinafter referred to as MESFETs), and high electron mobility transistors (hereinafter referred to as HEMTs). Among the characteristics of semiconductors, electrons in conduction bands emit light when the energy level drops to home appliances, so they are actively applied to optical devices such as laser diodes (LDs) and photodiodes (PDs). .
상기의 MESFET이나 HEMT등은 반절연성 화합물반도체(S.I. GaAs) 기판상에 전기적 활성층을 형성하고, 횡방향으로 게이트, 소스 및 드레인을 구성하여 전류를 횡적으로 조정하므로 제조 공정이 간단하고, 공정단가의 절감되는 장점이 있다.The MESFET and HEMT, etc., form an electrically active layer on a semi-insulating compound semiconductor (SI GaAs) substrate, and laterally adjust the current by forming gates, sources, and drains in a transverse direction, thereby simplifying the manufacturing process. It has the advantage of being saved.
또한 HBT는 소자분리 영역내의 매우 얇은 에피층에 수직적으로 에미터, 베이스, 컬렉터가 형성되어 있어 전류의 흐름을 수직적으로 제어하므로 동종 접합으로 형성되는 실리콘 바이폴라 트랜지스터나 MESFET 또는 HEMT 등에 비해 고속 및 고주파 특성이 우수하고, 전류 구동능력이 우수하며, 파괴전압이 큰 장점을 갖는다.In addition, HBT has high speed and high frequency characteristics compared to silicon bipolar transistors, MESFETs, HEMTs, etc. formed by homogeneous junction because emitter, base, and collector are vertically formed in a very thin epitaxial layer in the isolation region. It has excellent advantages, excellent current driving capability, and large breakdown voltage.
특히 최근 신속한 대량정보의 제공에 대한 요구가 커지면서 화합물 반도체를 이용한 HBT소자는 10Gbps(giga bit per second)이상의 광통신 시스템 전자회로에의 응용성은 매우 크다.In particular, with the recent demand for rapid provision of large amounts of information, HBT devices using compound semiconductors have great applicability to optical communication system electronic circuits of 10 Gbps (giga bit per second) or more.
그런데 이와같은 집적회로의 제조를 위해서는 HBT 등의 능동소자뿐만 아니라 캐패시터(capacitor), 저항(resistor), 인덕터(inductor)와 같은 수동소자의 형성이 중요한 과제가 되고 있다.However, for the manufacture of such integrated circuits, the formation of passive devices such as capacitors, resistors, and inductors, as well as active devices such as HBTs, has become an important problem.
제1도는 종래 기술에 따른 이종접합 바이폴라 트랜지스터와 연결되는 저항의 단면도이다.1 is a cross-sectional view of a resistor connected to a heterojunction bipolar transistor according to the prior art.
먼저, 화합물 반도체 기판(10)상에 소자분리 산화막이나 층간절연막 등과 같은 절연막(12)이 형성되어 있으며, 상기 절연막(12)상에 NiCr이나 TaN와 같은 금속층 패턴으로 된 소정의 저항값을 갖는 저항체(14)가 형성되어 있다.First, an insulating film 12 such as an element isolation oxide film or an interlayer insulating film is formed on the compound semiconductor substrate 10, and a resistor having a predetermined resistance value formed of a metal layer pattern such as NiCr or TaN on the insulating film 12. 14 is formed.
또한 상기 구조의 전표면에는 상기 저항체(14) 양측에서 콘택으로 예정되어 있는 부분을 노출시키는 콘택홀(18)을 구비하는 층간절연막(16)이 형성되어 있으며, 상기 콘택홀(18)을 통하여 저항체(14)와 접촉되어 외부전원선(도시되지 않음)과 연결되는 전극(19)이 형성되어 있다.In addition, an interlayer insulating film 16 is formed on the entire surface of the structure and includes contact holes 18 exposing portions intended to be contacts on both sides of the resistor 14, and the resistors are formed through the contact holes 18. An electrode 19 is formed in contact with 14 to be connected to an external power line (not shown).
상기와 같은 종래 기술에 따른 이종접합 바이폴라 트랜지스터와 연결되는 저항은 수십∼수백 Ω 정도의 저항범위에서는 NiCr이나 TaN와 같은 금속저항체를 사용하여 형성할 수 있으나, 수십 ㏀ 정도의 큰 저항이 요구될 경우 저항의 총길이가 너무 길어져 많은 칩면적을 차지하므로 MMIC화하지 못하고 HBT와는 다른 기판에 형성된 저항을 와이어로 연결하는 하이브리드 형태로 제작하게 된다.The resistor connected to the heterojunction bipolar transistor according to the prior art as described above may be formed using a metal resistor such as NiCr or TaN in a resistance range of several tens to several hundreds of kΩ, but a large resistance of several tens of kΩ is required. Since the total length of the resistor is too long to occupy a large amount of chip area, it cannot be MMIC and is manufactured in a hybrid form in which a resistor formed on a substrate different from HBT is connected by wire.
그러나 상기의 하이브리드 소자는 와이어로 연결되므로 기생저항 및 기생용량이 증가되어 고속 및 고주파 특성이 떨어지는 문제점이 있다.However, since the hybrid device is connected by a wire, parasitic resistance and parasitic capacitance are increased, thereby deteriorating high speed and high frequency characteristics.
이를 해결하기 위하여 GaAs를 기판으로 사용하는 MESFET에서는 기판에 적절한 수준의 이온주입 및 활성화열처리를 실시하여 기판을 저항으로 이용하거나, 고저항 특수재료를 사용하기도 한다.In order to solve this problem, MESFETs using GaAs as substrates are subjected to appropriate levels of ion implantation and activation heat treatment to use the substrates as resistors or high-resistance special materials.
그러나 GaAs 기판을 사용하는 HBT 소자에는 매우 정밀한 에피구조를 사용하기 때문에 통상적인 이온 주입기술이나 고온 열처리공정이 불가능하여 기판을 저항으로 사용할 수 없고, 도성합금(cermet) 같은 고저항재료를 사용하는 방법은 스퍼터링(sputtering)이나 전자빔(electron beam)으로 도성합금 박막을 형성하고, 사진 식각 공정에 의해 저항체 패턴을 정의해야 하므로, 기판과의 식각선택비가 작고 식각 자체가 어려워 공정수율 및 소자 동작의 신뢰성이 떨어지는 문제점이 있다.However, because HBT devices using GaAs substrates use very precise epi-structures, conventional ion implantation techniques or high-temperature heat treatment processes cannot be used, so substrates cannot be used as resistances, and high-resistance materials such as cermets are used. Since the conductive alloy thin film must be formed by sputtering or electron beam and the resist pattern is defined by a photolithography process, the etching selectivity with the substrate is small and the etching itself is difficult, so that the process yield and device operation reliability are high. There is a problem falling.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 AlGaAs/GaAs HBT에서 p형 불순물이 고농도로 도핑된 베이스층에 적절한 이온주입과 열처리를 병행 처리하여 얇은 베이스층의 일부를 기판 저항체로서 활용하며, 상기 베이스 전극의 일부분을 마스크 처리하여 오믹접촉특성을 향상시켜, 고저항 소자를 HBT와 MMIC화하여 소자의 고집적화에 유리하고, 제조 단가를 절감하며, 기생저항 및 기생용량 등을 감소시켜 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 화합물 반도체 소자의 제조방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to process a portion of a thin base layer by performing an appropriate ion implantation and heat treatment on a base layer doped with a high concentration of p-type impurities in AlGaAs / GaAs HBT. It is utilized as a resistor, and the part of the base electrode is masked to improve ohmic contact characteristics, and the high resistance device is converted into HBT and MMIC, which is advantageous for high integration of the device, reducing manufacturing cost, and parasitic resistance and parasitic capacitance. It is to provide a method for manufacturing a compound semiconductor device that can be reduced to improve the process yield and the reliability of device operation.
상기 목적을 달성하기 위한 본 발명에 따른 화합물 반도체 소자 제조방법은 반절연성의 화합물 반도체 기판상에 완충층을 형성하는 공정과, 상기 완충층상에 부컬렉터층을 형성하는 공정과, 상기 부컬렉터층상에 컬렉터층을 형성하는 공정과, 상기 컬렉터층상에 베이스층을 형성하는 공정과, 상기 베이스층상에 에미터층을 형성하는 공정과, 상기 에미터층상에 에미터캡층을 형성하는 공정과, 상기 에미터 캡층의 일측 상부에 에미터 전극을 형성하는 공정과, 상기 에미터 전극 양측의 노출되어 있는 에미터 캡층과 에미터층을 순차적으로 식각하여 베이스층의 표면을 노출시키는 에미터 캡층 패턴과 에미터층을 형성하는 공정과, 상기 에미터 전극 양측에서 소정간격 이격되어 있는 베이스층에 불순물 이온을 주입하여 저항체를 형성하는 공정과, 상기 베이스층 상에 베이스 전극을 형성하는 공정과, 상기 베이스 전극 양측의 저항체 및 컬렉터층을 순차적으로 식각하여 상기 부컬렉터층의 일부를 노출시키는 홈을 형성하는 공정과, 상기 홈을 통하여 노출되어있는 부컬렉터층상에 컬렉터 전극을 형성하는 공정과, 상기 구조의 이종접합 바이폴라 트랜지스터를 고립시키기 위한 소자분리 식각 공정을 상기 컬렉터 잔극 양측의 저항체에서 완충층까지를 순차적으로 식각하여 화합물 반도체 기판을 노출시키되, 상기 이종접합 바이폴라 트랜지스터 일측의 저항체도 함께 패턴닝하여 원하는 저항값을 갖는 저항체 패턴을 형성하는 공정을 구비함에 있다.A compound semiconductor device manufacturing method according to the present invention for achieving the above object is a step of forming a buffer layer on a semi-insulating compound semiconductor substrate, a step of forming a sub-collector layer on the buffer layer, and a collector on the sub-collector layer Forming a layer; forming a base layer on the collector layer; forming an emitter layer on the base layer; forming an emitter cap layer on the emitter layer; Forming an emitter electrode on one side and forming an emitter cap layer pattern and an emitter layer which expose the surface of the base layer by sequentially etching the exposed emitter cap layer and the emitter layer on both sides of the emitter electrode; And implanting impurity ions into the base layer spaced a predetermined distance from both sides of the emitter electrode to form a resistor; Forming a base electrode on the base layer, forming a groove to expose a portion of the sub-collector layer by sequentially etching the resistors and the collector layers on both sides of the base electrode, and a portion exposed through the groove. A method of forming a collector electrode on a collector layer and an element isolation etching process for isolating heterojunction bipolar transistors having the above structure are sequentially performed to etch the resistive layer from the resistors on both sides of the collector residual to the buffer layer to expose the compound semiconductor substrate. A method of forming a resistor pattern having a desired resistance value by patterning the resistors on one side of the junction bipolar transistor is also provided.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2도(a) 내지 (g)는 본 발명에 따른 화합물 반도체 소자의 제조 공정도로서, 반절연성 GaAs 기판을 사용한 HBT의 예이다.2 (a) to 2 (g) are manufacturing process diagrams of the compound semiconductor device according to the present invention, which is an example of HBT using a semi-insulating GaAs substrate.
제2도(a)를 참조하면, 반절연성 갈륨비소(S.I GaAs) 화합물 반도체 기판(20) 상에 통상의 HBT 구조의 완충층(21), 부컬렉터층(22), 컬렉터층(23), 베이스층(24), 에미터층(25) 및 에미터캡층(26)을 순차적으로 성장시킨다.Referring to FIG. 2A, a buffer layer 21, a subcollector layer 22, a collector layer 23, and a base of a conventional HBT structure are formed on a semi-insulating gallium arsenide (SI GaAs) compound semiconductor substrate 20. Layer 24, emitter layer 25 and emitter cap layer 26 are grown sequentially.
제2도(b)를 참조하면, 상기 에미터 캡층(26)상의 일측에 금속재질의 에미터전극(27)을 형성하고, 상기 에미터전극(27)을 식각 마스크로 하여 베이스층(24)의 표면이 노출되도록 에미터캡층(26)과 에미터층(25)을 패터닝한다.Referring to FIG. 2B, a metal emitter electrode 27 is formed on one side of the emitter cap layer 26, and the base layer 24 is formed using the emitter electrode 27 as an etching mask. The emitter cap layer 26 and emitter layer 25 are patterned to expose the surface of the emitter cap layer 26.
제2도(c)를 참조하면, 상기 구조의 전표면에 실리콘 질화막이나 실리콘산화막으로 된 절연막(28)을 도포한다.Referring to FIG. 2C, an insulating film 28 made of a silicon nitride film or a silicon oxide film is coated on the entire surface of the structure.
제2도(d)를 참조하면, 상기 에미터캡층(26)과 에미터층(25) 및 에이터 전극(27)을 감싸는 감광막 패턴(29)을 상기 절연막(28)상에 형성한 후, 상기 감광막 패턴(29) 양측의 노출되어있는 베이스층(24)에 소정의 불순물 이온을 이온주입한 후, 열처리하여 저항체(30)를 형성하며, 상기 감광막 패턴(29)에 의해 보호되어 있는 베이스층(24)은 후에 베이스 전극과 연결된다.Referring to FIG. 2 (d), after the photoresist pattern 29 is formed on the insulating layer 28, the photoresist pattern 29 surrounding the emitter cap layer 26, the emitter layer 25, and the emitter electrode 27 is formed. Predetermined impurity ions are implanted into the exposed base layer 24 on both sides of the pattern 29, followed by heat treatment to form a resistor 30, and the base layer 24 protected by the photosensitive film pattern 29. ) Is later connected with the base electrode.
이때 상기 이온주입되는 불순물 이온은 비교적 가벼운 원소인 붕소(B) 혹은 산소(O)를 사용하며, 도핑농도 및 에너지는 고농도의 p형으로 도핑되어 있는 노출된 베이스층(24)을 저농도로 보상(compensation)하여 예정된 저항을 갖는 기판 저항체(30)로 활용할 수 있는 조건을 계산하여 결정한다.At this time, the ion implanted impurity ions use boron (B) or oxygen (O), which are relatively light elements, and doping concentration and energy are compensated with low concentration of the exposed base layer 24 doped with a high concentration of p-type ( Compensation) to determine the condition that can be utilized as the substrate resistor 30 having a predetermined resistance.
또한 이온주입후 열처리 공정은 상기 에미터 전극(27)의 오믹접촉 특성이 열화되지 않을 정도의 온도 및 시간으로 급속 열처리를 하여 후에 형성되는 베이스 금속전극이 양호한 오믹접촉 특성을 갖도록한다.In addition, the heat treatment process after the ion implantation allows rapid base heat treatment at a temperature and time such that the ohmic contact characteristics of the emitter electrode 27 are not deteriorated so that the base metal electrode formed later has good ohmic contact characteristics.
제2도(e)를 참조하면, 상기 감광막 패턴(29)과 절연막(28)을 제거하여 이온주입되지 않은 베이스층(24)과 저항체(20)를 노출시킨 후, 상기 베이스층(24)의 양측과 접촉되는 베이스 전극(31)을 금속재질로 형성한다.Referring to FIG. 2E, the photoresist pattern 29 and the insulating layer 28 are removed to expose the base layer 24 and the resistor 20 which are not ion implanted, and then the base layer 24 The base electrode 31 in contact with both sides is formed of a metal material.
이때 상기 베이스 전극(31)의 일측은 이온주입에 의해 손상되지 않은 베이스층(24)과 접촉되어 오믹 접촉 특성 저하가 방지되고, 타측은 저항체(30)와 접촉되어 있다.At this time, one side of the base electrode 31 is in contact with the base layer 24 which is not damaged by ion implantation, thereby preventing degradation of ohmic contact characteristics, and the other side is in contact with the resistor 30.
제2도(f)를 참조하면, 상기 베이스 전극(31) 양측의 저항체(28) 및 컬렉터층(23)을 순차적으로 메사식각하여 컬렉터 전극 형성을 위하여 부컬렉터층(22)의 일부를 노출시키는 홈(32)을 형성한 후, 상기 홈(32)의 내측의 노출되어 있는 부컬렉터층(22)상에 컬렉터 전극(33)을 형성한다.Referring to FIG. 2 (f), the resistor 28 and the collector layer 23 on both sides of the base electrode 31 are mesa-etched sequentially to expose a part of the sub-collector layer 22 to form the collector electrode. After the groove 32 is formed, the collector electrode 33 is formed on the exposed subcollector layer 22 inside the groove 32.
제2도(g)를 참조하면, 상기 구조의 HBT 양측의 저항체(30)에서 완충층(21)까지를 순차적으로 메사식각하여 화합물 반도체기판(20)을 노출시켜 HBT를 고립시키는 소자분리 식각을 행하되, 일측의 저항체(30)도 함께 패턴닝하여 원하는 저항값을 갖는 저항체(30) 패턴을 형성한다.Referring to FIG. 2 (g), device isolation etching is performed to isolate the HBT by exposing the compound semiconductor substrate 20 by sequentially mesa-etching the resistors 30 on both sides of the HBT of the structure to the buffer layer 21. In addition, the resistor 30 on one side is also patterned to form a resistor 30 pattern having a desired resistance value.
이상에서 설명한 바와 같이, 본 발명에 따른 화합물 반도체 소자의 제조방법은 기존 HBT 소자의 에피층들에서 베이스층의 일부를 이온주입 및 활성화 방법으로 높은 저항값을 갖도록 하고, HBT 소자를 형성한 후, 소자분리 식각 공정시 저항체를 패턴닝하여 원하는 저항값을 갖는 저항체 패턴을 형성하였으므로, 하나의 기판에 HBT와 고정항값을 갖는 저항체를 MMIC화시켜 소자의 고집적화에 유리하고, 하이브리드 공정이 생략되고 기존의 공정에 이온주입 공정만이 추가되므로 공정이 간단하여 제조 단가를 절감할 수 있으며, 기생저항이나 기생용량을 감소시켜 고속 및 고주파 특성이 향상되어 소자 동작의 신뢰성이 향상되는 이점이 있다.As described above, in the method of manufacturing the compound semiconductor device according to the present invention, a part of the base layer in the epilayers of the existing HBT device has a high resistance value by ion implantation and activation method, and after forming the HBT device, In the device isolation etching process, the resistor was patterned to form a resistor pattern having a desired resistance value. HMM and a resistor having a fixed term value in one substrate were MMIC-ized, which is advantageous for high integration of the device. Since only the ion implantation process is added to the process, the manufacturing process can be simplified and the manufacturing cost can be reduced. The high speed and high frequency characteristics are improved by reducing the parasitic resistance or the parasitic capacitance, thereby improving the reliability of device operation.
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