KR0160719B1 - A decoder - Google Patents

Abstract

The present invention relates to a Viterbi decoder of a digital signal, comprising: a difference calculator for calculating a difference between a received signal and a value that feedbackly updates a difference evaluation amount for a survival path of a previous signal; A comparator for comparing the threshold value with the value obtained by the difference calculator; A multiplexer for selecting a threshold level value by the compared survival path selection signal; An adder for adding the selected threshold level value and the received signal; A switch unit for selecting whether to update the value by the adder by ORing two survival path selection signals; A state memory for storing the updated difference evaluation value; And a pass memory having a trellis type which decodes the original signal by two survival path selection signals.

According to the present invention, the use of the Viterbi decoder as the best decoding device using the Viterbi algorithm has the effect of reducing the amount of hardware and improving the signal reproduction performance. In addition, cost reduction can be achieved by applying the product.

Description

Viterbi decoder of digital signal

1 is a block diagram of an entire system showing encoding and decoding of a general digital signal.

2 is an NRZI system modeling characteristics of a precoder and a magnetic channel of FIG.

FIG. 3a is a state diagram showing the characteristics of a signal according to the characteristics of the NRZI system of FIG.

3b to 3d are diagrams showing survival paths that can occur in FIG. 3a.

4 is a block diagram of a Viterbi decoder having simplified hardware according to the present invention.

5 is a detailed block diagram of the threshold level detector of FIG.

6 is a detailed block diagram of the pass memory of FIG.

The present invention relates to a Viterbi decoder for decoding a reproduction signal, and more particularly, to a Viterbi decoder for reducing the amount of hardware by calculating a difference evaluation amount to simplify the configuration of the decoder.

In general, the convolution code has a remarkable difference from the block code in the code and the decoding method of the structure, and has a somewhat complicated structure, but the error correction capability is very excellent. The Viterbi decoder of the convolutional code decoding method is known to be very effective for sporadic error correction even though the complexity of hardware is increased by the code length and the double-word exponential function.

The digital signal input from the Partial Response (PR) system is output as a ternary signal through the channel, and the reproduced signal is distorted due to the characteristics of the channel and noise. The Viterbi algorithm, which is the maximum likelihood sequence estimator, is used to detect and decode the original signal from the distorted reproduction signal. This method has good performance as a signal detection method, but the amount of hardware increases considerably compared to the threshold detection method.

In addition, the Viterbi decoder according to the related art improves the performance by adding an adaptive algorithm to the existing Viterbi algorithm and decodes the signal. This is not a method of decoding a signal using a difference evaluation amount. The complexity of the hardware decoding the signal is not simplified.

It is a first object of the present invention to provide a method for reducing the amount of hardware. That is, the difference evaluation value between two survival paths in the decoder which detects the signal in the magnetic channel for recording and reproducing the digital signal is calculated, and the signal is decoded while updating the evaluation amount.

On the other hand, the amplitude of the global amplitude of the signal changes according to the characteristics of the channel, and the size of the reproduced data may be different from the assumed data size due to the error of the amplitude of the signal, and thus the adaptive correction of the error Is required. To this end, the present invention detects a threshold level value to adaptively change a threshold level value of a reproduced trilevel signal and compares it with an input signal reproduced by a comparator of a Viterbi decoder. The second purpose is to configure to improve the performance of the bit error rate (BER).

A Viterbi decoder which decodes a reproduced signal in a device for recording and reproducing a digital signal according to the present invention for achieving the above objects returns a differential evaluation amount for a survival path of a received signal and a previous signal input to the decoder. A first adder for obtaining a difference from the updated value; two first and second comparators for comparing a value by the first adder and a threshold level value; a survival pass compared in the first and second comparators; A multiplexer configured to select a threshold level value by a selection signal; a second adder configured to add a threshold level value selected by the multiplexer and a received signal; OR of two survival path selection signals output from the first and second comparators (OR A switch unit for selecting whether or not to update a value by the second adder; a state memory using a conventional latch to store a difference evaluation value updated through the switch unit; And a pass memory having a trellis type for decoding the original signal by means of four survival path selection signals.

In addition, the Viterbi decoder for decoding the reproduced signal in the apparatus for recording and reproducing the digital signal adaptively has a threshold level value corresponding to the change in the signal level due to the perturbation of the signal reproduced by the input signal and the selection signal. And a threshold level detector for detecting a threshold level value to be varied.

The threshold level detector may include: a first latch configured to receive and latch an input signal and a signal of the first comparator; a second latch configured to receive an input signal and an output signal of the second comparator; and a latch of the first latch output signal; A third adder which feedbackly adds the output signal of the first memory; a first multiplier that multiplies the output of the third adder by one half; a general D flip-flop that stores the output of the first multiplier A first adder configured to feedback-add the second latch output signal and the output signal of the second memory; a second multiplier multiplying the output of the fourth adder by one half; an output of the second multiplier A fifth adder for obtaining a difference between the first memory and the second memory, which is usually configured as a D flip-flop; multiplying the output of the fifth adder by a quarter and outputting one as it is and inverting one 3rd multiplier It characterized.

And a Viterbi decoder for decoding the reproduced signal in the apparatus for recording and reproducing the digital signal, wherein the pass memory receives as input a value to be decoded according to a survival path selection signal and a state diagram, and a multiplexer (MUX) and the like. A pass memory cell consisting of a D flip flop is made of a pass memory consisting of trellis memory cells for decoding an original signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 shows a block diagram of an entire system for encoding and decoding a general digital signal. First, the digital signal is recorded on a magnetic tape corresponding to a channel through a precoder 100 converted to a non return to zero invertor (NRZI) signal. The signal reproduced through the magnetic channel 110 is corrected by the amplitude of the signal through the linear equalizer 120, and then converted into a digital signal by an analog-to-digital (A / D) converter 130 is converted to a Viterbi decoder ( 140). Viterbi decoder 140 decodes the original signal from the received signal.

FIG. 2 shows the NRZI system modeling the characteristics of the precoder 100 and the magnetic channel 110 of FIG. In FIG. 2, D 210 and 220 denote a memory device representing a delay of a signal, and a '+' block 220 denotes an adder. In FIG. 2, the input digital signal A (k) is precoded through an exclusive OR (XOR) gate with B (k-1), which delays the output B (k) of the precoder 100 by a symbol interval. It is precoded to an output B (k), and this output B (k) is output as a reproduction signal R (k) through a channel having a channel characteristic of (1-D).

FIG. 3 shows a state diagram showing the characteristics of signals according to the characteristics of the NRZI system of FIG. In FIG. 3, the input / output relation according to the change of state between the digital input signal A (k) and the output signal R (k) reproduced through the channel is shown. When the input signal is -1 and the current state is SO (k), the output is O and the next state is SO (k + l) .When the input signal is 1 and the current state is SO (k), the output is 2 and next. The state becomes S1 (k + l). When the input signal is 1 and the current state is S1 (k), the output is -2 and the next state is SO (k + l) .When the input signal is -1 and the current state is S1 (k), the output is O And the next state becomes S1 (k + l).

As shown in the state diagrams in FIG. 2 and FIG. 3A, the value of the evaluation amount of the next state is determined by the calculation of the value of the current state and the estimated value according to the received value and state diagram. In other words, the state evaluation value of the next state is the path evaluation amount for the two passes by adding the evaluation value of the current state to the value obtained by obtaining the branch evaluation value between the value R (k) received in the current state and the assumed value of the path. Comparing the two paths to obtain a more optimal evaluation value of the path is selected as a survival pass.

That is, the amount of evaluation of the next state for the -1 state is

And the evaluation amount of the next state for one state is

Becomes

Therefore, the evaluation amount of the next state selects the smaller value of the evaluation amount by comparing the evaluation amounts of the two passes with each other. In the above formulas (1) and (2), the parts common to each other are omitted to simplify the expressions.

It becomes

FIG. 3b is when S1 (k + l) = S1 (k), SO (k + l) = SO (k) in equations (3) and (4), and the probability is Sl (k) -S0 (k ) + R (k) + l ≧ O, Sl (k) -SO (k) + R (k) −l ≦ O. That is, the above equation is a survival path when the third equation is -1 ≤ S1 (k)-S0 (k) + R (k) ≤ 1. Similarly, Figure 3c is a survival pass when S1 (k) -S0 (k) + R (k) ≥ 1. 3D is a survival pass when S1 (k) -S0 (k) + R (k) ≤ -1.

If the difference evaluation amount in the present state is Δ (k), Δ (k) = S1 (k) -S0 (k). Then, the difference evaluation amount of the next state for the survival pass of FIG. 3c is in the region Δ (k) + R (k) ≤ 1, and the difference evaluation amount Δ (k + 1) of the next state in FIG. 3c = -R ( k) + l. Also. The difference evaluation amount of the next state with respect to the survival pass of FIG. 3d is when it is in the area of (k) + R (k) ≥ 1, and the difference evaluation amount Δ (k + 1) = -R (k) -1 of the next state. do. Similarly, the evaluation amount of the next state with respect to the survival pass of FIG. 3b is when it is in the range of -1?? (K) + R (k)?

As shown in FIG. 3C, when the previous pass is summed at the -1 state at the k node, Δ (k + 1) = -R (k) + l, and the signal reproduced through the channel includes the noise component n (k) Thus the received signal R (k) = B (k)-B (k-1) + n (k), which is R (k) = [A (K) + B (k-1) mod2-B (K) It is expressed as -1) + n (k). And 3c shows the state diagram when B (kl) = -1, so R (k) = A (k)-(-1) + n (k), that is, R (k) = A (k) + 1 + n (k). Therefore, Δ (k + 1) =-(A (k) +1) + 1 + n (k), and Δ (k + 1) = -A (k) + n (k).

On the other hand, in Figure 3c, A (k) has values of +1 and -1, so A (k) is -1 for a path given from -1 to -1. 1) = +1 + n (k), and the value of A (k) is +1 for a given path from -1 to +1, △ (k + 1) = -1 + n (k ).

In summary, since Δ (k + 1) = -R (k) + 1 = -1 + n (k), it means that R (k) = 2-n (k), that is, R (k) = 2. Since Δ (k + 1) = -R (k) + 1 = 1 + n (k), R (k) = 0-n (k), that is, R (k) = 0.

However, in FIG. 3C, Δ (k + 1) = -R (k) + 1 to +1, which constitute the difference evaluation amount, is a threshold level value for the assumed signal value and a threshold level value of the reproduction signal is Distortion caused by the characteristics of the channel causes amplitude to fluctuate, and adaptively detects the threshold level and compares it with the received signal to calculate the difference estimate, thereby improving the decoding performance of the signal. .

4 shows a Viterbi decoder configured to improve performance by simplifying the Viterbi decoder by using the difference evaluation amount of the survival path and adaptively supplementing the perturbation of the amplitude of the reproduction signal by the channel characteristics according to the above method. It is. The received signal R (k) reproduced in FIG. 4 is input to a threshold level detector 400, and the received signal R (k) is added to a threshold level value to calculate a difference evaluation amount. 410 is entered. The output of the first adder 410 is input to the first comparator 450 and the second comparator 460 for comparing with a threshold level value. The PSO signal, which is one of the path select signals that are outputs of the first comparator 450 and the second comparator 460, is input as a control signal of the multiplexer (Mux. 420), and is OR gate 470. And pass memory 480 is input. The PS1 signal, which is one of the path selection signals output from the first comparator 450 and the second comparator 460, is input to the OR gate 470 and the pass memory 480. Output values (+ TH, -TH) of the threshold level detector 400 are input to two comparators 450 and 460, respectively, and to the multiplexer 420. The output signal of the multiplexer 420 is input to the second adder 430. The output signal of the OR gate 470 is input as a control signal of the switch unit 490, and the output signal of the second adder 430 is input to the switch unit 490. The output signal of the switch unit 490 is input to a state memory 440 which is typically latched to store the difference evaluation amount, and the output value of the state memory 440 is input to the first eyepiece 410.

5 is a detailed block diagram of the threshold level detector 400 of FIG. In FIG. 5, the received signal value R (k) is input to the first latch 500 and the second latch 502, and the path selection signals PS0 and PS1 are input to the first latch 500 and the second latch. It is inputted as a control signal of 502. When the path selection signal PS0. PS1 is 1, the first and second latches 500 and 502 are enabled. The outputs of the first and second latches 500 and 502 are the third and fourth adders 504 and 506, the first and second multipliers 508 and 510 to multiply by 1/2, and the first and second, typically D flip-flops. It is input to the third and fourth adders 504.506 of the first and second integrators 522.524, which are composed of two memories 512 and 514, and adds the current integrated value and the previous integrated value and adds this value to 1. It is stored in the first and second memories 512 and 514 by multiplying by two. The outputs of the first and second integrators 522 and 524 are added through a fifth adder 5101 and the outputs of the fifth adder 516 are 1/4 by a third multiplier 518 multiplying by 1/4. After being reduced to, one is output as it is and the other is inverted through the inverter 520 and output as a threshold level value (+ TH, -TH).

6 shows a detailed block diagram of the pass memory 480 of FIG. The pass memory of FIG. 6 has a multiplexer (MUX) and a D flip-flop in a trellis shape along the trellis degree. The pass memory has a value (0 or 1) to be decoded, and the decoded value is decoded as it passes along the trellis type memory by the path selection signals PS0 and PS1. The path select signal is input to all MUXs of the trellis type memory as a select signal.

As described above, according to the present invention, when detecting a signal in a magnetic channel for recording and reproducing a digital signal, a Viterbi decoder is used as the best decoding device using the Viterbi algorithm for performance improvement in a state in which the characteristics of the reproduction signal are poor. In use, there is an effect of reducing the amount of hardware and improving the signal reproduction performance. This is to simplify the hardware implementation and improve the SNR in the partial response system such as the magnetic channel, and it can reduce the cost of applying the actual product.

Claims (4)

A Viterbi decoder that decodes a reproduced signal in an apparatus for recording and reproducing digital signals, the Viterbi decoder comprising: obtaining a difference between a received signal input to the decoder and a value that reductively updates a difference evaluation amount for a survival path of a previous signal; Monoaddition group; Two first and second comparators for comparing a value by the first adder and a threshold level value; A multiplexer which uses the comparison result values compared in the first and second comparators as a survival path selection signal and thereby selects a threshold level value; A second adder for adding the received signal with a threshold level selected by the multiplexer; A switch unit for selecting whether to update a value by the second adder by performing a logical OR between two survival path selection signals output from the first and second comparators; A state memory for storing the value of the difference evaluation value updated through the switch unit; A Viterbi decoder of a digital signal, comprising: a pass memory configured in trellis form for decoding an original signal by two survival path selection signals. The apparatus of claim 1, further comprising a threshold level detector for detecting a threshold level value such that the threshold level is adaptively changed by a change in signal level caused by perturbation of the signal reproduced by the input signal and the selection signal. Viterbi decoder of the digital signal characterized in that. 3. The apparatus of claim 2, wherein the threshold level detector comprises: a first latch for receiving and latching an input signal and an output signal of the first comparator; A second latch receiving and latching an input signal and an output signal of the second comparator; A third adder for feedback adding the first latch output signal and an output signal of a first memory; A first multiplier that multiplies the output of the third adder by one half; A first memory for storing the output of the first multiplier; A fourth adder which feedbackly adds the second latch output signal and the output signal of the second memory; A second multiplier that multiplies the output of the fourth adder by one half; A second memory for storing the output of the second multiplier; A fifth adder for obtaining a difference between the I memory and the second memory; And a third multiplier configured to multiply the output of the fifth adder by a quarter to output one as it is and invert one to output the fifth adder. The pass memory of claim 1, wherein the pass memory receives a decoded value according to a survival path selection signal and a state diagram, and a pass memory cell including a multiplexer (MUX) and a flip-flop (D Flip Flop) receives an original signal. A Viterbi decoder of a digital signal, characterized in that it consists of a pass memory consisting of trellis memory cells for decoding.