KR0158686B1 - Integrated semiconductor memory - Google Patents

Abstract

In an integrated semiconductor memory with parallel test devices, each internal bitline pair BL, Bitline of BL, Can be controlled separately from each other. Therefore, in case of error, the internal bitline BL where the error occurred, The internal weighting circuit of BWS is prevented from flipping.

Description

Integrated semiconductor memory

The present invention is controllable through an internal bit line forming a word line and an internal bit line pair, and is a memory cell arranged in a matrix form in a memory cell device, one internal weighting circuit for each internal bit line pair, and common to an internal bit line. One pair of isolation transistors for each internal bit line pair for electrically separating the internal bit line pair from an external bit line pair, one bit line decoder for controlling the isolation transistor pair, one external weighting circuit, and an external bit line pair An integrated semiconductor memory having one discriminating device and a preliminary charging device connected thereto.

Modern integrated semiconductor memories contain very many memory cells. For example, modern DRAMs have memory capacities of 4 or 16 megabits. Typical functional test times increase at least twice linearly as the number of memory cells increases, as is known. Many test samples increase the test time squared with increasing memory capacity. For this reason, we have been trying to install devices that shorten the test time in the semiconductor memory itself. Shortening the test time is such that, for example, a plurality of memory cells operating independently of each other in standard operation are operated in parallel with each other in a test operation, test results are detected in the memory and eventually used as error signals at a normal data output stage. By doing so.

Such circuits are known, for example, from EP 0 283 907. The circuit can simultaneously read (test-) data from memory cells arranged along word lines. That is, the memory can be tested in parallel line by line. However, the circuit has two disadvantages as follows. The first is to provide a potential that lies between two normal supply potentials of the semiconductor memory for the control of the isolation transistor in the test operation, which requires independent potential generation in the semiconductor chip itself. Secondly, when an error occurs in a memory cell on one word line during a test operation, the weighting circuit belonging to the memory cell first flips incorrectly to a position indicating that the memory cell is correct (actually in error) according to the correct weighting. Can be pinged. This means, for example, that when the setting of the voltage magnitude at the gate of the isolation transistor is undesirable, the data read (correct) from the remaining memory cells of the same word line is transferred as its potential to the external bit line through its internal bit line and thus defects are detected. By being transferred to a bit line connected to a memory cell in which it resides, the bit line is squeezed at a potential that flips the internal weighting circuit. Thus, the internal weighting circuit is flipped from the original correctly indicating the defect of the memory cell to the correct-case indicating.

An object of the present invention is to improve a semiconductor memory so that the above-described error does not occur.

This object is achieved in accordance with the present invention by allowing the bit lines of each inner bit line pair to be controlled separately from each other, thereby allowing the bit lines of each inner bit line pair to be separated from each other and connected to the external bit line pair.

When described in detail with reference to the accompanying drawings of the present invention.

1 to 4 are preferred embodiments, and 5 to 6 are preferred details of the invention.

1 shows a memory cell SZ, an internal bit line pair BL, A memory cell device MEM with a word line WL and an internal weighting circuit BWS is shown. Only a few of these devices are shown for clarity. Typically each one internal bitline BL and an internal bitline Is a pair of internal bitlines BL, It is connected to the internal weighting circuit BWS. Pair of each internal bitline BL, And the internal weighting circuit BWS and a pair of external bit lines XB, A pair of isolation transistors TT are arranged in between. Each transistor pair TT is connected to a bit line detector DEC by a gate. In the prior art according to EP 0 283 907, the content of which is a part of the description to the extent consistent with the present invention, is commonly connected with the bit line detector DEC of the gates of each transistor pair TT. In this case, each transistor pair TT is an internal bit line pair BL, belonging to the transistor. Depending on the output of the bitline detector DEC, a pair of external bitlines XB, Is used to couple to or decouple from a pair of internal bitlines BL, Is the same as the choice. External bitline pair XB, Is connected to the external weighting circuit BWSext.

In the first embodiment of the present invention shown in Figs. 1 and 2, the transistors TT of each pair of transistors are separated from each other in a test operation and controlled through their gates. Therefore, during the test operation, a pair of internal bit lines BL, One internal bitline BL is controlled or the other internal bitline Is controlled, the external bitline pair XB, Either external bitline XB or the other external bitline Connected with. For example, a device in which the bitline detector DEC can control multiple to all pairs of (or other) isolation transistors TT of isolation transistors TT in a test operation (corresponding decoders are described, for example, in EP 0 282 975 and 0 283 908). With an internal bitline BL (or another internal bitline), External bit line XB (or another external bit line) in which information stored in a plurality of to all memory cells SZ in parallel along one word line WL is parallel to each other. Can be read. For the separation control of the isolation transistor TT, a pair of switching transistors ST for controlling the gate of the isolation transistor TT, for example, is provided in each isolation transistor pair TT.

Before describing the preferred embodiment in detail, the operation will be described in detail as follows: When a plurality of all the memory cells SZ arranged in the selected wordline WL are tested in parallel with each other in the test, all the memory cells SZ along the wordline WL are tested. The stored information (= data) is one internal bit line BL (or is the memory cell SZ connected to one internal bit line BL or another internal bit line) connected to the memory cell SZ from all the memory cells SZ at the same time. Internal bit line depending on whether or not Is read). The read data is then weighted and amplified in the internal weighting circuit BWS. By weighting, the weighting circuit BWS is flipped to a state corresponding to the data to be weighted, as is generally known.

As assumed in the example, if the word line WL is controlled to read data from the memory cell SZ so that the memory cell SZ is connected with one internal bitline BL, then each one internal bitline BL if correct after weighting With this read data (eg, logic 1, as assumed in another specification). Therefore, another internal bitline Has complementary data (e.g., logical 0). External bitline pair XB, where logic 1 is expected if correct at this point at the latest One external bit line, XB, is precharged to logic one. Another external bitline Can be precharged to logic zero. However, this is unnecessary as described later. Each internal bit line pair BL to which one memory cell is read; One isolation transistor TT is conducted for. External bitline pair XB, if correct One external bitline XB precharged with heavy logic 1 remains in a state generated by precharging similar to that described in EP 0 283 907. In case of an error (i.e. at least one of the inner bitline BLs has data of logic 0) precharged to the original logic 1 until equilibrium is made through the remaining inner bitline BLs with correct value logic 1 The potential of one external bit line XB drops by the value [Delta] U _ERRPR . During this process the external weighting circuit BWSext is in an inactive state. The discriminating device DISC identifies the drop and transmits an error signal. The action of the present invention described above is similar to the action known from EP 0 283 907. However, the present invention is in addition to the memory cell SZ or the internal bit line pair BL, This prevents the internal weighting circuit (incorrectly) in which an error occurs, from being incorrectly flipped to a state corresponding to the state in which it is placed. The flipping is an internal bitline pair BL, Bitline of BL, Each of these external bit line pairs XB, With other external bit lines in the device connected at the same time, ie in the device according to the prior art Caused by. In the prior art, this has a state of logic zero, so that the inner bitline pair BL, Bitline of BL, Other internal bit lines placed in logic 1 due to errors during concurrent connections of This logic is placed at zero. This of course causes flipping of the internal weighting circuit BWS. However, for example, the external bit line pair XB, according to the present invention, which can be implemented by separate control of the isolation transistor TT of each isolation transistor pair TT, And internal bitline pair BL, Bitline of BL, The possibility of a disconnected connection of reliably prevents this because the other disconnected transistor TT is blocked. Different external bit lines by blocking the other isolation transistor TT of each isolation transistor pair TT This is because it does not need to be precharged to logic zero.

Other internal bitlines The detailed description of the operation and operation method of the present invention for the case of testing the memory cell SZ connected to is omitted. The reason is that if the term is changed correspondingly (eg, one inner bitline BL is replaced by another inner bitline One external bitline XB to another external bitline The transistors TT of the isolation transistor pair TT may be replaced by another transistor TT of the isolation transistor pair TT and vice versa. In such a case, it will be readily apparent to those skilled in the art that the above embodiment may be applied.

If the memory cell SZ to be tested should have a logical zero, as described in EP 0 283 907, each internal bitline pair BL on an internal bitline not connected to the memory cell SZ to be tested , The complementary signal to the read signal which is read and amplified at s, i.e., the effect that logic 1 is formed in the correct case, is used. Accordingly, in this case, another external bit line This is precharged to logic 1. Also, other internal bit lines Is another external bitline through another isolation transistor TT Is electrically connected to and electrically disconnected while one isolation transistor TT is cut off.

The foregoing embodiment of associating a test with logic 1 allows a person skilled in the art to make sure that the external bitline Maintains its value logic 1 and therefore the discriminator does not generate an error signal; According to this potential, it can be made to move in the direction of logic 0 by the value (DELTA) U _ERROR mentioned above. This is again identified by the discriminator DISC and the corresponding error signal is activated. Even in this case, flipping of the internal weighting circuit BWS is reliably prevented. Detailed description is omitted since it is similar to the test for logic 1 described above.

A preferred embodiment of the present invention will be described in more detail as follows: Internal bit line pair BL, by isolation transistor TT, Bitline of BL, Separation control of the pair of test signals Test 1, Test 2 and (internal bit line pair BL, ) By a bitline detector DEC using a pair of switching transistors ST. Instead of the switching transistor ST, a transfer gate composed of parallel connected p-channel transistors and n-channel transistors which are mutually controlled may be used. In the use of the switching transistors ST shown in Figs. 1 and 2, a series circuit consisting of switching transistor pairs ST is provided in the decoder output DEC _BL of the bit line detector DEC (ordinarily unique according to the prior art). The source of the switching transistor is commonly connected to the inherent detector output DEC _BL . The drain of the switching transistor is connected to the gate of one or another isolation transistor TT. The drain of the switching transistor forms the output of the modified bit line detector DEC. The gate of one switching transistor ST is connected to one test signal Test 1. The gates of the other switching transistors ST are connected to another test signal Test 2. Thus, during the test operation, one of the switching transistors ST of the switching transistor pair is always shut off and the other is switched to conduct. This prevents the two isolation transistors of the isolation transistor pair TT from conducting during the test operation. In contrast, in the normal standard operation, all the switching transistors ST are switched so as to be conductive, so that the standard operation is not limited compared to the semiconductor memory according to the prior art.

As can be readily seen, the switching transistor ST requires an additional surface in the integrated semiconductor memory. However, when the present invention is applied to an integrated semiconductor, the integrated semiconductor memory includes a so-called shared bit decoder (in this case, the memory cell device MEM is subdivided into a plurality of blocks controlled in parallel to each other through one bit line decoder). Only an additional surface for the bit line decoder is required, and no surface for every block of the memory cell device MEM is needed. That is, the additional surface is minimal with respect to the surface of the entire integrated semiconductor memory.

As shown in FIG. 6, according to another preferred embodiment of the present invention, an external bitline pair XB, which does not need to be precharged to logic 0 in accordance with the present invention, Other external bit lines (Or XB) is one external bitline XB (or precharged to logic 1 as described above) in case of an error than the value of logic 1 for the aforementioned test purposes. ) When occupied by free a small electric potential U _{P0 ^1/2} value of a value △ U _ERROR is dropping, activates the external weighting circuit BWSext, which by itself is acting as a discriminating device DISC and flipping to a position corresponding to the error if The output acts as an error signal. Thus, a separate discriminating device DISC and a practically necessary multiplexer MUX as shown in FIG. 1 and EP 0 283 907 can be omitted.

In the second embodiment shown in FIGS. 3 and 4, each pair of isolation transistors TT is commonly connected to the output of the decoder DEC by a gate. Thus, the isolation transistor pair TT can be controlled in parallel to each other through its gate. For this purpose, for example, the decoder DEC has a device that can control many to all pairs of isolation transistors TT in parallel in the test case. Corresponding decoders are known, for example, from the European publications 0 282 975 and 0 283 908. Therefore, information stored in a plurality of memory cells SZ along the word line WL can be read in parallel with each other. In the test operation according to the present invention, each internal bit line BL, Pair of bitlines BL, In order to isolate and control each pair of separation transistors TT, if a pair of isolation transistors TT1 and TT2 are provided, the transistors TT1 and TT2 are connected in series with the isolation transistor TT of the pair of isolation transistors TT. The gate of one transistor TT1 of the other pair of isolation transistors TT1 and TT2 is controlled by the first test signal Test 1 during operation. The gates of the other pair of isolation transistors TT1 and TT2 are controlled by the second test signal Test 2 during operation. In standard operation, the two test signals Test 1 and Test 2 have potentials for conducting different pairs of isolation transistors TT1 and TT2 (ordinary supply potential VDD when the isolation transistors TT1 and TT2 are implemented as n-channel transistors).

If a plurality of to all the memory cells SZ arranged in the selected wordline WL are tested in parallel with each other during the test, the information (= data) stored in all the memory cells SZ along the wordline WL is simultaneously stored from all the memory cells SZ. An internal bit line BL connected to the bit line (or, is the memory cell SZ connected to a bit line BL or a bit line) Depending on whether or not Is read). The read data is then weighted and amplified in the internal weighting circuit BWS. By weighting the weighting circuit BWS is flipped to a state corresponding to the data to be weighted, as is generally known. The above process has already been described with reference to the first embodiment.

As assumed in the example, if the word line WL is controlled to read data from the memory cell SZ so that the memory cell SZ is connected with the internal bitline BL, then each internal bitline BL is read data if correct after weighting. (E.g., logic 1 as assumed in another specification). Internal bitline Has data that is complementary to it (eg, logical zero). External bitline pair XB, where logic 1 is expected if correct at this point at the latest One external bit line XB of X is precharged to logic one. Another external bitline Can be precharged to logic zero. However, this is unnecessary as already described with reference to the first embodiment. The pair of transistors TT is conducted by the decoder DEC. The first test signal Test 1 has a value of logic 1, while the second test signal Test 2 has a value of logic 0. External bitline pair XB, if correct An external bit line XB, precharged to logic 1, maintains the state generated by precharging similar to that described in EP 0 283 907. In case of an error (i.e. at least one of the internal bitlines BL has data of logic 0), the potential of the external bitline XB precharged to the original logic 1 has the correct value logic 1 by the value ΔU _ERROR described above. It is dropped until equilibrium is achieved through the remaining internal bitline BL. The external weighting circuit BWSext is inactive during this process. The discriminating device DISC identifies the drop and transmits an error signal. The above process is the same as already described with respect to the first embodiment. In the second embodiment of the present invention, the memory cell SZ or the internal bit line pair BL, This prevents the internal weighting circuit BWS, which has an error, from being flipped to a state corresponding to the state that is placed (wrongly) correct. In the first embodiment of the present invention (see Figs. 1 and 2), flipping is prevented by separating and controlling one separation transistor TT by the switching transistor ST, while the second embodiment shown in Figs. In this case, flipping is reliably prevented by the other isolation transistors TT1 and TT2. In this case, since another isolation transistor TT2 is blocked due to the control by the second test signal Test 2 = logic 0, this isolation transistor prevents flipping. Also, in the second embodiment, another external bit line Another isolation transistor TT2 is shut off because it does not need to be precharged to logic zero.

Other internal bitlines The detailed description of the operation and operation method of the second embodiment with respect to the case of testing the memory cell SZ connected thereto is omitted. The reason is that if the term is changed correspondingly (eg, one inner bitline BL is replaced by another inner bitline One external bitline XB to another external bitline It is to be understood by one skilled in the art that one embodiment TT1 of isolation transistor pair TT1, TT2 can be replaced by another transistor TT2 of isolation transistor pair TT1, TT2 and vice versa.

If the memory cell SZ to be tested should have a logical zero, as described already in connection with the first embodiment, each internal bit line pair BL on the inner bitline not connected to the memory cell SZ to be tested, The complementary signal to the read signal which is read and amplified at s, i.e., the effect that logic 1 is formed in the correct case, is used. Accordingly, in this case, the other external bit line Is precharged to logic one. The first test signal Test 1 also has a value of logic 0, thereby blocking one other isolation transistor TT1, which prevents the flipping described above in case of an error. The second test signal Test 2 has a value of logic one.

By virtue of the embodiment described above relating test to logic 1, those skilled in the art will be able to Maintains its logic 1 value and the discriminator therefore does not generate an error signal, in case of an error According to this potential, it can be made to move in the direction of logic 0 by the value (DELTA) U _ERROR mentioned above. This is again identified by the discriminator DISC and the corresponding error signal is activated. Even in this case, flipping of the internal weighting circuit BWS is reliably prevented. The detailed description is omitted because it is similar to the test for logic 1 described above.

In the first aspect of the second embodiment as shown in FIG. 3, it is preferable to arrange different isolation transistor pairs TT1 and TT2 between the memory cell device MEM and the pair of isolation transistors TT. However, in the second embodiment of the second embodiment as shown in FIG. 4, the other isolation transistor pairs TT1 and TT2 are replaced with a pair of isolation transistors TT and an external bit line pair XB, It is preferable to arrange in between.

It is also preferable to form a common diffusion region D for each one of the other isolation transistor pairs TT1 and TT2 and a transistor connected to it of the pair of isolation transistors TT, since the space is saved. The diffusion zone D acts as a source or drain region for two transistors TT1 and TT or TT2 and TT and is shown in FIG.

In the implementation of the invention, in particular in the implementation of the second embodiment, the lines of the test signals Test 1, Test 2 are the external bit line pair XB, It is formed parallel to the line of. In this case, the lines of the two test signals Test 1 and Test 2 are the external bit line pair XB, It is preferable to install the shielding line with respect to the line (Fig. 4).

The same applies to the form according to FIG. 4 as well as to the form according to FIG. 2: the external bitline pair XB, which does not need to be precharged to logic 0 according to this embodiment, Other external bit lines (Or XB) one external bitline XB (or precharged to logic 1 as described above in case of an error than the value of logic 1 for the aforementioned test purposes) ), When precharged to _^1/2 by a small electric potential U _P0 value of △ U _ERROR is dropping to activate an external weighting circuit BWSext this device itself determines DISC (the working and the error in the 2, 4, 6, see Fig.) In that case, the output acts as an error signal by flipping to the corresponding position. Therefore, in the second embodiment, the separate determination device DISC and the actually required multiplexer MUX can be omitted. This is shown in FIG.

Claims (9)

Word line WL and internal bit line pair BL, Internal bit lines BL, Memory cells SZ arranged in a matrix form in the memory cell device MEM, and each internal bit line pair BL, One internal weighting circuit (BWS),-internal bit line (BL, External bit line pair (XB, common to From the internal bitline pair (BL, ), Each internal bitline pair (BL, A pair of isolation transistors TT, one bit line decoder DEC for controlling the isolation transistor pair TT, one external weighting circuit BWSext, and one external bit line pair XB, In the integrated semiconductor memory having one discriminating device DISC and a precharging device PC connected to each other, each internal bit line pair BL, Bit lines BL) ) Can be controlled separately from each other so that each internal bit line pair (BL, Bit lines BL) ) Is the external bitline pair (XB, And) can be connected separately from each other. 2. The integrated semiconductor memory according to claim 1, wherein separation control by a bit line decoder (DEC) is performed in dependence on a pair of test signals (Test 1, Test 2). The method of claim 2, wherein the separation control of each pair of separation transistors (TT) is made by a switching transistor (ST) connected in series with each other, the source of the switching transistor (ST) and one decoder line (DEC _BL ) And the drain is connected in common with the gate of the isolation transistor (TT), and the gate is connected with a test signal pair (Test 1, Test 2). The transistor of claim 1, wherein the transistors of each of the isolation transistor pairs TT can be controlled in parallel with each other, and each of the internal bit line pairs BL, Bit lines BL) Another pair of isolation transistors TT1 and TT2 are installed in series with respect to the isolation transistor pair TT in each isolation transistor pair TT for separation control of Wherein one transistor (TT1) is controlled by a first test signal (Test 1) and the other transistor (TT2) is controlled by a second test signal (Test 2). 5. The integrated semiconductor memory according to claim 4, wherein another pair of isolation transistors (TT1, TT2) is arranged between the memory cell device (MEM) and a pair of isolation transistors (TT). The method of claim 4, wherein another pair of isolation transistors TT1 and TT2 includes an external bit line pair XB, ) And a pair of isolation transistors (TT). The common diffusion according to any one of claims 7 to 6, wherein each one of the other pair of isolation transistors TT1 and TT2 and one of the pair of isolation transistors TT connected thereto are common. A region D is formed, wherein the diffusion region serves as a source region or a drain region for two transistors (TT1, TT; TT2, TT). The strip conductor of any one of the preceding claims, wherein the strip conductor having the test signals Test 1, Test 2 is an external bit line pair XB, Arrayed as a shielding strip conductor with respect to the strip conductor. The method according to any one of the preceding claims, wherein the external bit line pair XB,One of the two bit lines XB;) Is precharged to logic 1 and the external bitline pair (XB,The other one of the two bit lines (XB;) Is greater than the value of logic 1, in case of an error an external bit line pair (XB,One of the bit lines XB precharged to logic 1;) Drops (△ U)_ERROR)of One/₂As little potential (△ U_ERRORAn integrated semiconductor memory, characterized in that it is precharged.